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author | John Crispin <john@openwrt.org> | 2012-04-16 12:31:48 +0000 |
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committer | John Crispin <john@openwrt.org> | 2012-04-16 12:31:48 +0000 |
commit | 83948d6385c9ce23545a159ffd64f5b2854332ed (patch) | |
tree | 1d79b701055f05ca319d5ac3623af6615f394844 /target/linux/lantiq/patches-3.3/0063-MIPS-lantiq-irqs-were-not-cleared-properly-on-boot.patch | |
parent | fb2b2b958e9da0d9ea0195a0829da52a0eda667c (diff) | |
download | upstream-83948d6385c9ce23545a159ffd64f5b2854332ed.tar.gz upstream-83948d6385c9ce23545a159ffd64f5b2854332ed.tar.bz2 upstream-83948d6385c9ce23545a159ffd64f5b2854332ed.zip |
adds 3.3 patches and files
SVN-Revision: 31307
Diffstat (limited to 'target/linux/lantiq/patches-3.3/0063-MIPS-lantiq-irqs-were-not-cleared-properly-on-boot.patch')
-rw-r--r-- | target/linux/lantiq/patches-3.3/0063-MIPS-lantiq-irqs-were-not-cleared-properly-on-boot.patch | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/target/linux/lantiq/patches-3.3/0063-MIPS-lantiq-irqs-were-not-cleared-properly-on-boot.patch b/target/linux/lantiq/patches-3.3/0063-MIPS-lantiq-irqs-were-not-cleared-properly-on-boot.patch new file mode 100644 index 0000000000..85573284be --- /dev/null +++ b/target/linux/lantiq/patches-3.3/0063-MIPS-lantiq-irqs-were-not-cleared-properly-on-boot.patch @@ -0,0 +1,34 @@ +From 875a7139535da541aa2e9de308b3f6f791a131d0 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Tue, 20 Mar 2012 09:44:27 +0100 +Subject: [PATCH 63/70] MIPS: lantiq: irqs were not cleared properly on boot + +--- + arch/mips/lantiq/irq.c | 10 +++++----- + 1 files changed, 5 insertions(+), 5 deletions(-) + +diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c +index f17caec..7224231 100644 +--- a/arch/mips/lantiq/irq.c ++++ b/arch/mips/lantiq/irq.c +@@ -326,12 +326,12 @@ void __init arch_init_irq(void) + panic("Failed to remap eiu memory\n"); + } + +- /* make sure all irqs are turned off by default */ +- for (i = 0; i < 5; i++) ++ for (i = 0; i < 5; i++) { ++ /* make sure all irqs are turned off by default */ + ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET)); +- +- /* clear all possibly pending interrupts */ +- ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET)); ++ /* clear all possibly pending interrupts */ ++ ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET)); ++ } + + mips_cpu_irq_init(); + +-- +1.7.9.1 + |