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| author | John Crispin <john@openwrt.org> | 2015-08-17 06:17:47 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2015-08-17 06:17:47 +0000 |
| commit | 6b775f4517b31f4226fbf08fa4e35e9100c92635 (patch) | |
| tree | 2d8fdc29190b1b0fe9c8ba54ea3cd70a0f9cbaa6 /target/linux/ipq806x/patches-3.18/115-add-pcie-aux-clk-dts.patch | |
| parent | 6856535e290aefcebd257b19a6b7d8d9c70c1171 (diff) | |
| download | upstream-6b775f4517b31f4226fbf08fa4e35e9100c92635.tar.gz upstream-6b775f4517b31f4226fbf08fa4e35e9100c92635.tar.bz2 upstream-6b775f4517b31f4226fbf08fa4e35e9100c92635.zip | |
ipq806x: add hwspinlock support
This change cherry-picks the following 3 changes from linux-next:
*fb7737 hwspinlock/core: add device tree support
*19a0f6 hwspinlock: qcom: Add support for Qualcomm HW Mutex block
*bd5717 hwspinlock: qcom: Correct msb in regmap_field
We're also adding a patch to add the hardware spinlock device nodes on
IPQ806x platforms (033-soc-qcom-Add-sfbp-device-to-IPQ806x-dts.patch).
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
SVN-Revision: 46655
Diffstat (limited to 'target/linux/ipq806x/patches-3.18/115-add-pcie-aux-clk-dts.patch')
| -rw-r--r-- | target/linux/ipq806x/patches-3.18/115-add-pcie-aux-clk-dts.patch | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target/linux/ipq806x/patches-3.18/115-add-pcie-aux-clk-dts.patch b/target/linux/ipq806x/patches-3.18/115-add-pcie-aux-clk-dts.patch index 13ff921ba4..83c5f55247 100644 --- a/target/linux/ipq806x/patches-3.18/115-add-pcie-aux-clk-dts.patch +++ b/target/linux/ipq806x/patches-3.18/115-add-pcie-aux-clk-dts.patch @@ -1,6 +1,6 @@ --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -336,15 +336,21 @@ +@@ -341,15 +341,21 @@ clocks = <&gcc PCIE_A_CLK>, <&gcc PCIE_H_CLK>, @@ -26,7 +26,7 @@ status = "disabled"; }; -@@ -377,15 +383,21 @@ +@@ -382,15 +388,21 @@ clocks = <&gcc PCIE_1_A_CLK>, <&gcc PCIE_1_H_CLK>, @@ -52,7 +52,7 @@ status = "disabled"; }; -@@ -418,15 +430,21 @@ +@@ -423,15 +435,21 @@ clocks = <&gcc PCIE_2_A_CLK>, <&gcc PCIE_2_H_CLK>, |