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author | Nick Hainke <vincent@systemli.org> | 2021-07-28 23:18:01 +0200 |
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committer | Daniel Golle <daniel@makrotopia.org> | 2021-07-29 15:08:17 +0100 |
commit | e8e2b88f5feb852904598cbe8746cc5b3c0022ab (patch) | |
tree | 2b9577a6afe5c7f0b03b2de8fb1ed404f037e67e /target/linux/generic/backport-5.10/821-v5.13-let-pci-host-bridges-declar-their-reliance-on-msi-domains.patch | |
parent | e88ab3b6292a78dd8a21436dfae78f8bfcfd82b0 (diff) | |
download | upstream-e8e2b88f5feb852904598cbe8746cc5b3c0022ab.tar.gz upstream-e8e2b88f5feb852904598cbe8746cc5b3c0022ab.tar.bz2 upstream-e8e2b88f5feb852904598cbe8746cc5b3c0022ab.zip |
mediatek: mt7623: import patch to fix msi warning
The 1st generation MediaTek PCIe host bridge cannot handle Message
Signaled Interrupts (MSIs). The core PCI code is not aware that MSI is
not available. This results in warnings of the form:
WARNING: CPU: 2 PID: 112 at include/linux/msi.h:219
pci_msi_setup_msi_irqs.constprop.8+0x64/0x6c
Modules linked in: ahci(+) libahci libata sd_mod scsi_mod
gpio_button_hotplug
CPU: 2 PID: 112 Comm: kmodloader Not tainted 5.10.52 #0
Hardware name: Mediatek Cortex-A7 (Device Tree)
Import patches that introduce the 'no_msi' attribute to signal missing
MSI support to the core PCI.
Refresh patches:
- 000-spi-fix-fifo.patch
- 330-mtk-bmt-support.patch
- 510-net-mediatek-add-flow-offload-for-mt7623.patch
- 601-PCI-mediatek-Use-regmap-to-get-shared-pcie-cfg-base.patch
- 610-pcie-mediatek-fix-clearing-interrupt-status.patch
- 700-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch
- 710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch
Signed-off-by: Nick Hainke <vincent@systemli.org>
Diffstat (limited to 'target/linux/generic/backport-5.10/821-v5.13-let-pci-host-bridges-declar-their-reliance-on-msi-domains.patch')
-rw-r--r-- | target/linux/generic/backport-5.10/821-v5.13-let-pci-host-bridges-declar-their-reliance-on-msi-domains.patch | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/target/linux/generic/backport-5.10/821-v5.13-let-pci-host-bridges-declar-their-reliance-on-msi-domains.patch b/target/linux/generic/backport-5.10/821-v5.13-let-pci-host-bridges-declar-their-reliance-on-msi-domains.patch new file mode 100644 index 0000000000..9cf63af333 --- /dev/null +++ b/target/linux/generic/backport-5.10/821-v5.13-let-pci-host-bridges-declar-their-reliance-on-msi-domains.patch @@ -0,0 +1,44 @@ +From 94e89b145371b68fa0ea294855adebcd03e0522e Mon Sep 17 00:00:00 2001 +From: Marc Zyngier <maz@kernel.org> +Date: Tue, 30 Mar 2021 16:11:41 +0100 +Subject: PCI/MSI: Let PCI host bridges declare their reliance on MSI domains + +There is a whole class of host bridges that cannot know whether +MSIs will be provided or not, as they rely on other blocks +to provide the MSI functionnality, using MSI domains. This is +the case for example on systems that use the ARM GIC architecture. + +Introduce a new attribute ('msi_domain') indicating that implicit +dependency, and use this property to set the NO_MSI flag when +no MSI domain is found at probe time. + +Link: https://lore.kernel.org/r/20210330151145.997953-11-maz@kernel.org +Signed-off-by: Marc Zyngier <maz@kernel.org> +Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> +Acked-by: Bjorn Helgaas <bhelgaas@google.com> +--- + drivers/pci/probe.c | 2 ++ + include/linux/pci.h | 1 + + 2 files changed, 3 insertions(+) + +--- a/drivers/pci/probe.c ++++ b/drivers/pci/probe.c +@@ -925,6 +925,8 @@ static int pci_register_host_bridge(stru + device_enable_async_suspend(bus->bridge); + pci_set_bus_of_node(bus); + pci_set_bus_msi_domain(bus); ++ if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev)) ++ bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI; + + if (!parent) + set_dev_node(bus->bridge, pcibus_to_node(bus)); +--- a/include/linux/pci.h ++++ b/include/linux/pci.h +@@ -545,6 +545,7 @@ struct pci_host_bridge { + unsigned int native_dpc:1; /* OS may use PCIe DPC */ + unsigned int preserve_config:1; /* Preserve FW resource setup */ + unsigned int size_windows:1; /* Enable root bus sizing */ ++ unsigned int msi_domain:1; /* Bridge wants MSI domain */ + + /* Resource alignment requirements */ + resource_size_t (*align_resource)(struct pci_dev *dev, |