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| author | Koen Vandeputte <koen.vandeputte@ncentric.com> | 2019-05-28 12:28:11 +0200 |
|---|---|---|
| committer | Koen Vandeputte <koen.vandeputte@ncentric.com> | 2019-06-03 12:40:53 +0200 |
| commit | 405e08bee63d030956aeb77a1f2b09d0d35a867d (patch) | |
| tree | 038d33c990f0b0548d98a750965573d854bb709b /target/linux/cns3xxx/patches-4.19 | |
| parent | 8f6fd53db9abc347467ace5696353ceebe1d76cb (diff) | |
| download | upstream-405e08bee63d030956aeb77a1f2b09d0d35a867d.tar.gz upstream-405e08bee63d030956aeb77a1f2b09d0d35a867d.tar.bz2 upstream-405e08bee63d030956aeb77a1f2b09d0d35a867d.zip | |
kernel: bump 4.19 to 4.19.46
Refreshed all patches.
Compile-tested on: cns3xxx, imx6
Runtime-tested on: cns3xxx, imx6
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
Diffstat (limited to 'target/linux/cns3xxx/patches-4.19')
| -rw-r--r-- | target/linux/cns3xxx/patches-4.19/130-Extend-PCIE_BUS_PEER2PEER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/linux/cns3xxx/patches-4.19/130-Extend-PCIE_BUS_PEER2PEER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch b/target/linux/cns3xxx/patches-4.19/130-Extend-PCIE_BUS_PEER2PEER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch index b17a61392d..3276000fe4 100644 --- a/target/linux/cns3xxx/patches-4.19/130-Extend-PCIE_BUS_PEER2PEER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch +++ b/target/linux/cns3xxx/patches-4.19/130-Extend-PCIE_BUS_PEER2PEER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch @@ -1,6 +1,6 @@ --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c -@@ -2629,7 +2629,8 @@ static void pcie_write_mrrs(struct pci_d +@@ -2634,7 +2634,8 @@ static void pcie_write_mrrs(struct pci_d * In the "safe" case, do not configure the MRRS. There appear to be * issues with setting MRRS to 0 on a number of devices. */ @@ -12,7 +12,7 @@ /* --- a/include/linux/pci.h +++ b/include/linux/pci.h -@@ -866,7 +866,7 @@ enum pcie_bus_config_types { +@@ -868,7 +868,7 @@ enum pcie_bus_config_types { PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ |