brcm63xx: switch to 3.14

Now that BB is branched off, we can now switch to 3.14 and start
breaking stuff again.

Signed-off-by: Jonas Gorski <jogo@openwrt.org>

SVN-Revision: 41941

1 files changed, 0 insertions, 48 deletions

diff --git a/target/linux/brcm63xx/patches-3.10/059-MIPS-BMIPS-fix-hardware-interrupt-routing-for-boot-C.patch b/target/linux/brcm63xx/patches-3.10/059-MIPS-BMIPS-fix-hardware-interrupt-routing-for-boot-C.patch
deleted file mode 100644
index a838f1a2d4..0000000000
--- a/target/linux/brcm63xx/patches-3.10/059-MIPS-BMIPS-fix-hardware-interrupt-routing-for-boot-C.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From fcfa66de8a2f0631a65a2cec0f6149dafd36ec81 Mon Sep 17 00:00:00 2001
-From: Florian Fainelli <florian@openwrt.org>
-Date: Mon, 5 Aug 2013 11:50:25 +0100
-Subject: [PATCH] MIPS: BMIPS: fix hardware interrupt routing for boot CPU != 0
-
-The hardware interrupt routing for boot CPU != 0 is wrong because it
-will route all the hardware interrupts to TP0 which is not the one we
-booted from. Fix this by properly checking which boot CPU we are booting
-from and updating the right interrupt mask for the boot CPU. This fixes
-booting on BCM3368 with bmips_smp_emabled = 0.
-
-Signed-off-by: Florian Fainelli <florian@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Cc: blogic@openwrt.org
-Cc: jogo@openwrt.org
-Cc: cernekee@gmail.com
-Patchwork: https://patchwork.linux-mips.org/patch/5650/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/kernel/smp-bmips.c | 10 ++++++++--
- 1 file changed, 8 insertions(+), 2 deletions(-)
-
---- a/arch/mips/kernel/smp-bmips.c
-+++ b/arch/mips/kernel/smp-bmips.c
-@@ -66,6 +66,8 @@ static void __init bmips_smp_setup(void)
- 	int i, cpu = 1, boot_cpu = 0;
- 
- #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
-+	int cpu_hw_intr;
-+
- 	/* arbitration priority */
- 	clear_c0_brcm_cmt_ctrl(0x30);
- 
-@@ -80,8 +82,12 @@ static void __init bmips_smp_setup(void)
- 	 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
- 	 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
- 	 */
--	change_c0_brcm_cmt_intr(0xf8018000,
--					(0x02 << 27) | (0x03 << 15));
-+	if (boot_cpu == 0)
-+		cpu_hw_intr = 0x02;
-+	else
-+		cpu_hw_intr = 0x1d;
-+
-+	change_c0_brcm_cmt_intr(0xf8018000, (cpu_hw_intr << 27) | (0x03 << 15));
- 
- 	/* single core, 2 threads (2 pipelines) */
- 	max_cpus = 2;