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authorFlorian Fainelli <florian@openwrt.org>2009-03-20 15:08:02 +0000
committerFlorian Fainelli <florian@openwrt.org>2009-03-20 15:08:02 +0000
commit0972ee5331eec00b2fbebfdd8b849d2bbc1a08eb (patch)
tree9ce2e90d15bf66eeae7a703e8d0eafb893600410 /target/linux/brcm63xx/files
parent08b7cbe44e178861cc6bbc11c83272363ae645e6 (diff)
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add support for bcm6345 SoC, needs testing
SVN-Revision: 14953
Diffstat (limited to 'target/linux/brcm63xx/files')
-rw-r--r--target/linux/brcm63xx/files/arch/mips/bcm63xx/Kconfig5
-rw-r--r--target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c31
-rw-r--r--target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h48
3 files changed, 82 insertions, 2 deletions
diff --git a/target/linux/brcm63xx/files/arch/mips/bcm63xx/Kconfig b/target/linux/brcm63xx/files/arch/mips/bcm63xx/Kconfig
index b21c03e6df..a3ac72a43f 100644
--- a/target/linux/brcm63xx/files/arch/mips/bcm63xx/Kconfig
+++ b/target/linux/brcm63xx/files/arch/mips/bcm63xx/Kconfig
@@ -8,6 +8,11 @@ config BCM63XX_CPU_6338
select USB_OHCI_BIG_ENDIAN_DESC
select USB_OHCI_BIG_ENDIAN_MMIO
+config BCM63XX_CPU_6345
+ bool "support 6345 CPU"
+ select USB_OHCI_BIG_ENDIAN_DESC
+ select USB_OHCI_BIG_ENDIAN_MMIO
+
config BCM63XX_CPU_6348
bool "support 6348 CPU"
select HW_HAS_PCI
diff --git a/target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c b/target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c
index f9b6eeba46..bc7ed50f89 100644
--- a/target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c
+++ b/target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c
@@ -72,6 +72,26 @@ static const unsigned long bcm96338_regs_spi[] = {
};
/*
+ * 6345 register sets and irqs
+ */
+
+static const unsigned long bcm96345_regs_base[] = {
+ [RSET_PERF] = BCM_6345_PERF_BASE,
+ [RSET_TIMER] = BCM_6345_TIMER_BASE,
+ [RSET_WDT] = BCM_6345_WDT_BASE,
+ [RSET_UART0] = BCM_6345_UART0_BASE,
+ [RSET_GPIO] = BCM_6345_GPIO_BASE,
+};
+
+static const int bcm96345_irqs[] = {
+ [IRQ_TIMER] = BCM_6345_TIMER_IRQ,
+ [IRQ_UART0] = BCM_6345_UART0_IRQ,
+ [IRQ_DSL] = BCM_6345_DSL_IRQ,
+ [IRQ_ENET0] = BCM_6345_ENET0_IRQ,
+ [IRQ_ENET_PHY] = BCM_6345_ENET_PHY_IRQ,
+};
+
+/*
* 6348 register sets and irqs
*/
static const unsigned long bcm96348_regs_base[] = {
@@ -217,9 +237,11 @@ static unsigned int detect_cpu_clock(void)
{
unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
- if (BCMCPU_IS_6338()) {
+ if (BCMCPU_IS_6338())
return 240000000;
- }
+
+ if (BCMCPU_IS_6345())
+ return 140000000;
/*
* frequency depends on PLL configuration:
@@ -294,6 +316,11 @@ void __init bcm63xx_cpu_init(void)
bcm63xx_irqs = bcm96338_irqs;
bcm63xx_regs_spi = bcm96338_regs_spi;
break;
+ case CPU_BCM6345:
+ expected_cpu_id = BCM6345_CPU_ID;
+ bcm63xx_regs_base = bcm96345_regs_base;
+ bcm63xx_irqs = bcm96345_irqs;
+ break;
case CPU_BCM6348:
expected_cpu_id = BCM6348_CPU_ID;
bcm63xx_regs_base = bcm96348_regs_base;
diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
index 74e553f7da..2ad2c9dc99 100644
--- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
+++ b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
@@ -12,6 +12,7 @@
* arm mach-types)
*/
#define BCM6338_CPU_ID 0x6338
+#define BCM6345_CPU_ID 0x6345
#define BCM6348_CPU_ID 0x6348
#define BCM6358_CPU_ID 0x6358
@@ -33,6 +34,19 @@ unsigned int bcm63xx_get_cpu_freq(void);
# define BCMCPU_IS_6338() (0)
#endif
+#ifdef CONFIG_BCM63XX_CPU_6345
+# ifdef bcm63xx_get_cpu_id
+# undef bcm63xx_get_cpu_id
+# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
+# define BCMCPU_RUNTIME_DETECT
+# else
+# define bcm63xx_get_cpu_id() BCM6345_CPU_ID
+# endif
+# define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
+#else
+# define BCMCPU_IS_6345() (0)
+#endif
+
#ifdef CONFIG_BCM63XX_CPU_6348
# ifdef bcm63xx_get_cpu_id
# undef bcm63xx_get_cpu_id
@@ -123,6 +137,15 @@ enum bcm63xx_regs_set {
#define BCM_6338_MEMC_BASE (0xfffe3100)
/*
+ * 6345 register sets base address
+ */
+#define BCM_6345_PERF_BASE (0xfffe0000)
+#define BCM_6345_TIMER_BASE (0xfffe0200)
+#define BCM_6345_WDT_BASE (0xfffe021c)
+#define BCM_6345_UART0_BASE (0xfffe0300)
+#define BCM_6345_GPIO_BASE (0xfffe0400)
+
+/*
* 6348 register sets base address
*/
#define BCM_6348_DSL_LMEM_BASE (0xfff00000)
@@ -204,6 +227,20 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
return BCM_6338_MEMC_BASE;
}
#endif
+#ifdef CONFIG_BCM63XX_CPU_6345
+ switch (set) {
+ case RSET_PERF:
+ return BCM_6345_PERF_BASE;
+ case RSET_TIMER:
+ return BCM_6345_TIMER_BASE;
+ case RSET_WDT:
+ return BCM_6345_WDT_BASE;
+ case RSET_UART0:
+ return BCM_6345_UART0_BASE;
+ case RSET_GPIO:
+ return BCM_6345_GPIO_BASE;
+ }
+#endif
#ifdef CONFIG_BCM63XX_CPU_6348
switch (set) {
case RSET_DSL_LMEM:
@@ -462,6 +499,17 @@ enum bcm63xx_irq {
#define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17)
/*
+ * 6345 irqs
+ */
+#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
+#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
+#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
+#define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4)
+#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5)
+#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
+#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
+
+/*
* 6348 irqs
*/
#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)