brcm2708: add kernel 4.14 support

Patch generation process:
- rebase rpi/rpi-4.14.y on v4.14.89 from linux-stable
- git format-patch v4.14.89

Patches skipped during rebase:
- lan78xx: Read MAC address from DT if present
- lan78xx: Enable LEDs and auto-negotiation
- Revert "softirq: Let ksoftirqd do its job"
- sc16is7xx: Fix for multi-channel stall
- lan78xx: Ignore DT MAC address if already valid
- lan78xx: Simple patch to prevent some crashes
- tcp_write_queue_purge clears all the SKBs in the write queue
- Revert "lan78xx: Simple patch to prevent some crashes"
- lan78xx: Connect phy early
- Arm: mm: ftrace: Only set text back to ro after kernel has been marked ro
- Revert "Revert "softirq: Let ksoftirqd do its job""
- ASoC: cs4265: SOC_SINGLE register value error fix
- Revert "ASoC: cs4265: SOC_SINGLE register value error fix"
- Revert "net: pskb_trim_rcsum() and CHECKSUM_COMPLETE are friends"
- Revert "Revert "net: pskb_trim_rcsum() and CHECKSUM_COMPLETE are friends""

Patches dropped after rebase:
- net: Add non-mainline source for rtl8192cu wlan
- net: Fix rtl8192cu build errors on other platforms
- brcm: adds support for BCM43341 wifi
- brcmfmac: Mute expected startup 'errors'
- ARM64: Fix build break for RTL8187/RTL8192CU wifi
- ARM64: Enable RTL8187/RTL8192CU wifi in build config
- This is the driver for Sony CXD2880 DVB-T2/T tuner + demodulator
- brcmfmac: add CLM download support
- brcmfmac: request_firmware_direct is quieter
- Sets the BCDC priority to constant 0
- brcmfmac: Disable ARP offloading when promiscuous
- brcmfmac: Avoid possible out-of-bounds read
- brcmfmac: Delete redundant length check
- net: rtl8192cu: Normalize indentation
- net: rtl8192cu: Fix implicit fallthrough warnings
- Revert "Sets the BCDC priority to constant 0"
- media: cxd2880: Bump to match 4.18.y version
- media: cxd2880-spi: Bump to match 4.18.y version
- Revert "mm: alloc_contig: re-allow CMA to compact FS pages"
- Revert "Revert "mm: alloc_contig: re-allow CMA to compact FS pages""
- cxd2880: CXD2880_SPI_DRV should select DVB_CXD2880 with
  MEDIA_SUBDRV_AUTOSELECT
- 950-0421-HID-hid-bigbenff-driver-for-BigBen-Interactive-PS3OF.patch
- 950-0453-Add-hid-bigbenff-to-list-of-have_special_driver-for-.patch

Make I2C built-in instead of modular as in upstream defconfig; also the
easiest way to get MFD_ARIZONA enabled, which is required by
kmod-sound-soc-rpi-cirrus.
Add missing compatible strings from
4.9/960-add-rasbperrypi-compatible.patch, using upstream names for
compute modules.
Add extra patch to enable the LEDs on lan78xx.

Compile-tested: bcm2708, bcm2709, bcm2710 (with CONFIG_ALL_KMODS=y)
Runtime-tested: bcm2708, bcm2710

Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>

1 files changed, 256 insertions, 0 deletions

diff --git a/target/linux/brcm2708/patches-4.14/950-0296-lan78xx-PHY-DSP-registers-initialization-to-address-.patch b/target/linux/brcm2708/patches-4.14/950-0296-lan78xx-PHY-DSP-registers-initialization-to-address-.patch
new file mode 100644
index 0000000000..f2e40fb010
--- /dev/null
+++ b/target/linux/brcm2708/patches-4.14/950-0296-lan78xx-PHY-DSP-registers-initialization-to-address-.patch
@@ -0,0 +1,256 @@
+From 07667014469b0e1464d1cd77d0b42d523fd3ad46 Mon Sep 17 00:00:00 2001
+From: Raghuram Chary J <raghuramchary.jallipalli@microchip.com>
+Date: Wed, 11 Apr 2018 20:36:36 +0530
+Subject: [PATCH 296/454] lan78xx: PHY DSP registers initialization to address
+ EEE link drop issues with long cables
+
+commit 1c2734b31d72316e3faaad88c0c9c46fa92a4b20 upstream.
+
+The patch is to configure DSP registers of PHY device
+to handle Gbe-EEE failures with >40m cable length.
+
+Fixes: 55d7de9de6c3 ("Microchip's LAN7800 family USB 2/3 to 10/100/1000 Ethernet device driver")
+Signed-off-by: Raghuram Chary J <raghuramchary.jallipalli@microchip.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/microchip.c  | 178 ++++++++++++++++++++++++++++++++++-
+ include/linux/microchipphy.h |   8 ++
+ 2 files changed, 185 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/phy/microchip.c
++++ b/drivers/net/phy/microchip.c
+@@ -20,6 +20,7 @@
+ #include <linux/ethtool.h>
+ #include <linux/phy.h>
+ #include <linux/microchipphy.h>
++#include <linux/delay.h>
+ 
+ #define DRIVER_AUTHOR	"WOOJUNG HUH <woojung.huh@microchip.com>"
+ #define DRIVER_DESC	"Microchip LAN88XX PHY driver"
+@@ -30,6 +31,16 @@ struct lan88xx_priv {
+ 	__u32	wolopts;
+ };
+ 
++static int lan88xx_read_page(struct phy_device *phydev)
++{
++	return __phy_read(phydev, LAN88XX_EXT_PAGE_ACCESS);
++}
++
++static int lan88xx_write_page(struct phy_device *phydev, int page)
++{
++	return __phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, page);
++}
++
+ static int lan88xx_phy_config_intr(struct phy_device *phydev)
+ {
+ 	int rc;
+@@ -66,6 +77,150 @@ static int lan88xx_suspend(struct phy_de
+ 	return 0;
+ }
+ 
++static int lan88xx_TR_reg_set(struct phy_device *phydev, u16 regaddr,
++			      u32 data)
++{
++	int val, save_page, ret = 0;
++	u16 buf;
++
++	/* Save current page */
++	save_page = phy_save_page(phydev);
++	if (save_page < 0) {
++		pr_warn("Failed to get current page\n");
++		goto err;
++	}
++
++	/* Switch to TR page */
++	lan88xx_write_page(phydev, LAN88XX_EXT_PAGE_ACCESS_TR);
++
++	ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_LOW_DATA,
++			  (data & 0xFFFF));
++	if (ret < 0) {
++		pr_warn("Failed to write TR low data\n");
++		goto err;
++	}
++
++	ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_HIGH_DATA,
++			  (data & 0x00FF0000) >> 16);
++	if (ret < 0) {
++		pr_warn("Failed to write TR high data\n");
++		goto err;
++	}
++
++	/* Config control bits [15:13] of register */
++	buf = (regaddr & ~(0x3 << 13));/* Clr [14:13] to write data in reg */
++	buf |= 0x8000; /* Set [15] to Packet transmit */
++
++	ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_CR, buf);
++	if (ret < 0) {
++		pr_warn("Failed to write data in reg\n");
++		goto err;
++	}
++
++	usleep_range(1000, 2000);/* Wait for Data to be written */
++	val = __phy_read(phydev, LAN88XX_EXT_PAGE_TR_CR);
++	if (!(val & 0x8000))
++		pr_warn("TR Register[0x%X] configuration failed\n", regaddr);
++err:
++	return phy_restore_page(phydev, save_page, ret);
++}
++
++static void lan88xx_config_TR_regs(struct phy_device *phydev)
++{
++	int err;
++
++	/* Get access to Channel 0x1, Node 0xF , Register 0x01.
++	 * Write 24-bit value 0x12B00A to register. Setting MrvlTrFix1000Kf,
++	 * MrvlTrFix1000Kp, MasterEnableTR bits.
++	 */
++	err = lan88xx_TR_reg_set(phydev, 0x0F82, 0x12B00A);
++	if (err < 0)
++		pr_warn("Failed to Set Register[0x0F82]\n");
++
++	/* Get access to Channel b'10, Node b'1101, Register 0x06.
++	 * Write 24-bit value 0xD2C46F to register. Setting SSTrKf1000Slv,
++	 * SSTrKp1000Mas bits.
++	 */
++	err = lan88xx_TR_reg_set(phydev, 0x168C, 0xD2C46F);
++	if (err < 0)
++		pr_warn("Failed to Set Register[0x168C]\n");
++
++	/* Get access to Channel b'10, Node b'1111, Register 0x11.
++	 * Write 24-bit value 0x620 to register. Setting rem_upd_done_thresh
++	 * bits
++	 */
++	err = lan88xx_TR_reg_set(phydev, 0x17A2, 0x620);
++	if (err < 0)
++		pr_warn("Failed to Set Register[0x17A2]\n");
++
++	/* Get access to Channel b'10, Node b'1101, Register 0x10.
++	 * Write 24-bit value 0xEEFFDD to register. Setting
++	 * eee_TrKp1Long_1000, eee_TrKp2Long_1000, eee_TrKp3Long_1000,
++	 * eee_TrKp1Short_1000,eee_TrKp2Short_1000, eee_TrKp3Short_1000 bits.
++	 */
++	err = lan88xx_TR_reg_set(phydev, 0x16A0, 0xEEFFDD);
++	if (err < 0)
++		pr_warn("Failed to Set Register[0x16A0]\n");
++
++	/* Get access to Channel b'10, Node b'1101, Register 0x13.
++	 * Write 24-bit value 0x071448 to register. Setting
++	 * slv_lpi_tr_tmr_val1, slv_lpi_tr_tmr_val2 bits.
++	 */
++	err = lan88xx_TR_reg_set(phydev, 0x16A6, 0x071448);
++	if (err < 0)
++		pr_warn("Failed to Set Register[0x16A6]\n");
++
++	/* Get access to Channel b'10, Node b'1101, Register 0x12.
++	 * Write 24-bit value 0x13132F to register. Setting
++	 * slv_sigdet_timer_val1, slv_sigdet_timer_val2 bits.
++	 */
++	err = lan88xx_TR_reg_set(phydev, 0x16A4, 0x13132F);
++	if (err < 0)
++		pr_warn("Failed to Set Register[0x16A4]\n");
++
++	/* Get access to Channel b'10, Node b'1101, Register 0x14.
++	 * Write 24-bit value 0x0 to register. Setting eee_3level_delay,
++	 * eee_TrKf_freeze_delay bits.
++	 */
++	err = lan88xx_TR_reg_set(phydev, 0x16A8, 0x0);
++	if (err < 0)
++		pr_warn("Failed to Set Register[0x16A8]\n");
++
++	/* Get access to Channel b'01, Node b'1111, Register 0x34.
++	 * Write 24-bit value 0x91B06C to register. Setting
++	 * FastMseSearchThreshLong1000, FastMseSearchThreshShort1000,
++	 * FastMseSearchUpdGain1000 bits.
++	 */
++	err = lan88xx_TR_reg_set(phydev, 0x0FE8, 0x91B06C);
++	if (err < 0)
++		pr_warn("Failed to Set Register[0x0FE8]\n");
++
++	/* Get access to Channel b'01, Node b'1111, Register 0x3E.
++	 * Write 24-bit value 0xC0A028 to register. Setting
++	 * FastMseKp2ThreshLong1000, FastMseKp2ThreshShort1000,
++	 * FastMseKp2UpdGain1000, FastMseKp2ExitEn1000 bits.
++	 */
++	err = lan88xx_TR_reg_set(phydev, 0x0FFC, 0xC0A028);
++	if (err < 0)
++		pr_warn("Failed to Set Register[0x0FFC]\n");
++
++	/* Get access to Channel b'01, Node b'1111, Register 0x35.
++	 * Write 24-bit value 0x041600 to register. Setting
++	 * FastMseSearchPhShNum1000, FastMseSearchClksPerPh1000,
++	 * FastMsePhChangeDelay1000 bits.
++	 */
++	err = lan88xx_TR_reg_set(phydev, 0x0FEA, 0x041600);
++	if (err < 0)
++		pr_warn("Failed to Set Register[0x0FEA]\n");
++
++	/* Get access to Channel b'10, Node b'1101, Register 0x03.
++	 * Write 24-bit value 0x000004 to register. Setting TrFreeze bits.
++	 */
++	err = lan88xx_TR_reg_set(phydev, 0x1686, 0x000004);
++	if (err < 0)
++		pr_warn("Failed to Set Register[0x1686]\n");
++}
++
+ static int lan88xx_probe(struct phy_device *phydev)
+ {
+ 	struct device *dev = &phydev->mdio.dev;
+@@ -132,6 +287,25 @@ static void lan88xx_set_mdix(struct phy_
+ 	phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0);
+ }
+ 
++static int lan88xx_config_init(struct phy_device *phydev)
++{
++	int val;
++
++	genphy_config_init(phydev);
++	/*Zerodetect delay enable */
++	val = phy_read_mmd(phydev, MDIO_MMD_PCS,
++			   PHY_ARDENNES_MMD_DEV_3_PHY_CFG);
++	val |= PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_;
++
++	phy_write_mmd(phydev, MDIO_MMD_PCS, PHY_ARDENNES_MMD_DEV_3_PHY_CFG,
++		      val);
++
++	/* Config DSP registers */
++	lan88xx_config_TR_regs(phydev);
++
++	return 0;
++}
++
+ static int lan88xx_config_aneg(struct phy_device *phydev)
+ {
+ 	lan88xx_set_mdix(phydev);
+@@ -151,7 +325,7 @@ static struct phy_driver microchip_phy_d
+ 	.probe		= lan88xx_probe,
+ 	.remove		= lan88xx_remove,
+ 
+-	.config_init	= genphy_config_init,
++	.config_init	= lan88xx_config_init,
+ 	.config_aneg	= lan88xx_config_aneg,
+ 	.read_status	= genphy_read_status,
+ 
+@@ -161,6 +335,8 @@ static struct phy_driver microchip_phy_d
+ 	.suspend	= lan88xx_suspend,
+ 	.resume		= genphy_resume,
+ 	.set_wol	= lan88xx_set_wol,
++	.read_page	= lan88xx_read_page,
++	.write_page	= lan88xx_write_page,
+ } };
+ 
+ module_phy_driver(microchip_phy_driver);
+--- a/include/linux/microchipphy.h
++++ b/include/linux/microchipphy.h
+@@ -70,4 +70,12 @@
+ #define	LAN88XX_MMD3_CHIP_ID			(32877)
+ #define	LAN88XX_MMD3_CHIP_REV			(32878)
+ 
++/* DSP registers */
++#define PHY_ARDENNES_MMD_DEV_3_PHY_CFG		(0x806A)
++#define PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_	(0x2000)
++#define LAN88XX_EXT_PAGE_ACCESS_TR		(0x52B5)
++#define LAN88XX_EXT_PAGE_TR_CR			16
++#define LAN88XX_EXT_PAGE_TR_LOW_DATA		17
++#define LAN88XX_EXT_PAGE_TR_HIGH_DATA		18
++
+ #endif /* _MICROCHIPPHY_H */