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| author | Rafał Miłecki <rafal@milecki.pl> | 2016-08-19 12:44:44 +0200 |
|---|---|---|
| committer | Rafał Miłecki <rafal@milecki.pl> | 2016-08-19 12:47:58 +0200 |
| commit | 28d641be43a5acde4dc3ff49112852cb661fd41a (patch) | |
| tree | 3b82c3e0d01ae0c227985984abaa20b095d229dd /target/linux/bcm53xx/patches-4.4/300-ARM-BCM5301X-Disable-MMU-and-Dcache-during-decompres.patch | |
| parent | 1bef5050ef62e82e061b9e6d88262dafd52fe966 (diff) | |
| download | upstream-28d641be43a5acde4dc3ff49112852cb661fd41a.tar.gz upstream-28d641be43a5acde4dc3ff49112852cb661fd41a.tar.bz2 upstream-28d641be43a5acde4dc3ff49112852cb661fd41a.zip | |
bcm53xx: update copy of ASM entry flushing whole D-cache
Previous version was based on code from kernel 2.6.22 with Broadcom two
trivial modifications. This updates the copy to the version from current
kernel and refreshes the patch.
This was tested for regressions on Netgear R6250 (BCM4708A0), D-Link
DIR-885L (BCM4709C0) and Tenda AC9 (BCM47189B0).
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Diffstat (limited to 'target/linux/bcm53xx/patches-4.4/300-ARM-BCM5301X-Disable-MMU-and-Dcache-during-decompres.patch')
| -rw-r--r-- | target/linux/bcm53xx/patches-4.4/300-ARM-BCM5301X-Disable-MMU-and-Dcache-during-decompres.patch | 31 |
1 files changed, 16 insertions, 15 deletions
diff --git a/target/linux/bcm53xx/patches-4.4/300-ARM-BCM5301X-Disable-MMU-and-Dcache-during-decompres.patch b/target/linux/bcm53xx/patches-4.4/300-ARM-BCM5301X-Disable-MMU-and-Dcache-during-decompres.patch index 5dba027725..1c73775b43 100644 --- a/target/linux/bcm53xx/patches-4.4/300-ARM-BCM5301X-Disable-MMU-and-Dcache-during-decompres.patch +++ b/target/linux/bcm53xx/patches-4.4/300-ARM-BCM5301X-Disable-MMU-and-Dcache-during-decompres.patch @@ -82,19 +82,20 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl> + mov r8, r12 --- a/arch/arm/boot/compressed/cache-v7-min.S +++ b/arch/arm/boot/compressed/cache-v7-min.S -@@ -51,7 +51,7 @@ loop2: - loop3: - orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 - orr r11, r11, r7, lsl r2 @ factor index number into r11 +@@ -12,6 +12,7 @@ + + #include <linux/linkage.h> + #include <linux/init.h> ++#include <asm/assembler.h> + + __INIT + +@@ -63,7 +64,7 @@ loop2: + ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11 + THUMB( lsl r6, r9, r2 ) + THUMB( orr r11, r11, r6 ) @ factor index number into r11 - mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way -+ mcr p15, 0, r11, c7, c6, 2 @ Invalidate line - subs r9, r9, #1 @ decrement the way - bge loop3 - subs r7, r7, #1 @ decrement the index -@@ -63,5 +63,6 @@ skip: - finished: - mov r10, #0 @ swith back to cache level 0 - mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr -+ dsb - isb - mov pc, lr ++ mcr p15, 0, r11, c7, c6, 2 @ clean & invalidate by set/way + subs r9, r9, #1 @ decrement the index + bge loop2 + subs r4, r4, #1 @ decrement the way |