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| author | Felix Fietkau <nbd@nbd.name> | 2016-05-12 17:54:14 +0200 |
|---|---|---|
| committer | Felix Fietkau <nbd@nbd.name> | 2016-05-12 17:54:14 +0200 |
| commit | 3f1705d7770d6ff42f369ff7856fb047c8b78e42 (patch) | |
| tree | 0ea8bec363bceb3d1f237afb771b9906ba98f34a /target/linux/bcm53xx/patches-4.3 | |
| parent | b9c6361d5f6f47149c99b02c2c00e91e0729aec9 (diff) | |
| download | upstream-3f1705d7770d6ff42f369ff7856fb047c8b78e42.tar.gz upstream-3f1705d7770d6ff42f369ff7856fb047c8b78e42.tar.bz2 upstream-3f1705d7770d6ff42f369ff7856fb047c8b78e42.zip | |
bcm53xx: delete old kernel versions
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Diffstat (limited to 'target/linux/bcm53xx/patches-4.3')
49 files changed, 0 insertions, 6588 deletions
diff --git a/target/linux/bcm53xx/patches-4.3/020-ARM-BCM5310X-activate-erratas-needed-for-SoC.patch b/target/linux/bcm53xx/patches-4.3/020-ARM-BCM5310X-activate-erratas-needed-for-SoC.patch deleted file mode 100644 index d1868f3f87..0000000000 --- a/target/linux/bcm53xx/patches-4.3/020-ARM-BCM5310X-activate-erratas-needed-for-SoC.patch +++ /dev/null @@ -1,31 +0,0 @@ -From f4ce7effe2253a325f8ba182903cbdf0d8698593 Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens <hauke@hauke-m.de> -Date: Sat, 21 Nov 2015 15:29:47 +0100 -Subject: [PATCH] ARM: BCM5310X: activate erratas needed for SoC - -The BCM4708 I have, which is probably the first generation which got -to the consumer market, is using a ARM Cortex-A9 rev r3p0 and a -L2C-310 rev r3p2 L2 cache controller. There are 3 workarounds for known -erratas in the Linux kernel which could be activated and will be in -this patch. There are currently no workarounds which have to be -activated for the L2C-310 rev r3p2 in Linux. - -Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> -Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> ---- - arch/arm/mach-bcm/Kconfig | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm/mach-bcm/Kconfig -+++ b/arch/arm/mach-bcm/Kconfig -@@ -38,6 +38,10 @@ config ARCH_BCM_CYGNUS - config ARCH_BCM_5301X - bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7 - select ARCH_BCM_IPROC -+ select ARM_ERRATA_754322 -+ select ARM_ERRATA_775420 -+ select ARM_ERRATA_764369 if SMP -+ - help - Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores. - diff --git a/target/linux/bcm53xx/patches-4.3/044-clk-cygnus-Convert-all-macros-to-all-caps.patch b/target/linux/bcm53xx/patches-4.3/044-clk-cygnus-Convert-all-macros-to-all-caps.patch deleted file mode 100644 index f65aa9cf0b..0000000000 --- a/target/linux/bcm53xx/patches-4.3/044-clk-cygnus-Convert-all-macros-to-all-caps.patch +++ /dev/null @@ -1,292 +0,0 @@ -From b5116083e227fa478e20d5ed945430088aa1a00b Mon Sep 17 00:00:00 2001 -From: Jon Mason <jonmason@broadcom.com> -Date: Thu, 15 Oct 2015 15:48:25 -0400 -Subject: [PATCH 44/50] clk: cygnus: Convert all macros to all caps - -The macros that are being used to initialize the values of the clk -structures should be all caps. Find and replace all of them with their -relevant counterparts. - -Signed-off-by: Jon Mason <jonmason@broadcom.com> ---- - drivers/clk/bcm/clk-cygnus.c | 146 +++++++++++++++++++++---------------------- - 1 file changed, 73 insertions(+), 73 deletions(-) - ---- a/drivers/clk/bcm/clk-cygnus.c -+++ b/drivers/clk/bcm/clk-cygnus.c -@@ -23,28 +23,28 @@ - #include <dt-bindings/clock/bcm-cygnus.h> - #include "clk-iproc.h" - --#define reg_val(o, s, w) { .offset = o, .shift = s, .width = w, } -+#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, } - --#define aon_val(o, pw, ps, is) { .offset = o, .pwr_width = pw, \ -+#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \ - .pwr_shift = ps, .iso_shift = is } - --#define sw_ctrl_val(o, s) { .offset = o, .shift = s, } -+#define SW_CTRL_VAL(o, s) { .offset = o, .shift = s, } - --#define asiu_div_val(o, es, hs, hw, ls, lw) \ -+#define ASIU_DIV_VAL(o, es, hs, hw, ls, lw) \ - { .offset = o, .en_shift = es, .high_shift = hs, \ - .high_width = hw, .low_shift = ls, .low_width = lw } - --#define reset_val(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ -+#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ - .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \ - .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ - .ka_width = kaw } - --#define vco_ctrl_val(uo, lo) { .u_offset = uo, .l_offset = lo } -+#define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo } - --#define enable_val(o, es, hs, bs) { .offset = o, .enable_shift = es, \ -+#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \ - .hold_shift = hs, .bypass_shift = bs } - --#define asiu_gate_val(o, es) { .offset = o, .en_shift = es } -+#define ASIU_GATE_VAL(o, es) { .offset = o, .en_shift = es } - - static void __init cygnus_armpll_init(struct device_node *node) - { -@@ -55,52 +55,52 @@ CLK_OF_DECLARE(cygnus_armpll, "brcm,cygn - static const struct iproc_pll_ctrl genpll = { - .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC | - IPROC_CLK_PLL_NEEDS_SW_CFG, -- .aon = aon_val(0x0, 2, 1, 0), -- .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 3), -- .sw_ctrl = sw_ctrl_val(0x10, 31), -- .ndiv_int = reg_val(0x10, 20, 10), -- .ndiv_frac = reg_val(0x10, 0, 20), -- .pdiv = reg_val(0x14, 0, 4), -- .vco_ctrl = vco_ctrl_val(0x18, 0x1c), -- .status = reg_val(0x28, 12, 1), -+ .aon = AON_VAL(0x0, 2, 1, 0), -+ .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3), -+ .sw_ctrl = SW_CTRL_VAL(0x10, 31), -+ .ndiv_int = REG_VAL(0x10, 20, 10), -+ .ndiv_frac = REG_VAL(0x10, 0, 20), -+ .pdiv = REG_VAL(0x14, 0, 4), -+ .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c), -+ .status = REG_VAL(0x28, 12, 1), - }; - - static const struct iproc_clk_ctrl genpll_clk[] = { - [BCM_CYGNUS_GENPLL_AXI21_CLK] = { - .channel = BCM_CYGNUS_GENPLL_AXI21_CLK, - .flags = IPROC_CLK_AON, -- .enable = enable_val(0x4, 6, 0, 12), -- .mdiv = reg_val(0x20, 0, 8), -+ .enable = ENABLE_VAL(0x4, 6, 0, 12), -+ .mdiv = REG_VAL(0x20, 0, 8), - }, - [BCM_CYGNUS_GENPLL_250MHZ_CLK] = { - .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK, - .flags = IPROC_CLK_AON, -- .enable = enable_val(0x4, 7, 1, 13), -- .mdiv = reg_val(0x20, 10, 8), -+ .enable = ENABLE_VAL(0x4, 7, 1, 13), -+ .mdiv = REG_VAL(0x20, 10, 8), - }, - [BCM_CYGNUS_GENPLL_IHOST_SYS_CLK] = { - .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK, - .flags = IPROC_CLK_AON, -- .enable = enable_val(0x4, 8, 2, 14), -- .mdiv = reg_val(0x20, 20, 8), -+ .enable = ENABLE_VAL(0x4, 8, 2, 14), -+ .mdiv = REG_VAL(0x20, 20, 8), - }, - [BCM_CYGNUS_GENPLL_ENET_SW_CLK] = { - .channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK, - .flags = IPROC_CLK_AON, -- .enable = enable_val(0x4, 9, 3, 15), -- .mdiv = reg_val(0x24, 0, 8), -+ .enable = ENABLE_VAL(0x4, 9, 3, 15), -+ .mdiv = REG_VAL(0x24, 0, 8), - }, - [BCM_CYGNUS_GENPLL_AUDIO_125_CLK] = { - .channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK, - .flags = IPROC_CLK_AON, -- .enable = enable_val(0x4, 10, 4, 16), -- .mdiv = reg_val(0x24, 10, 8), -+ .enable = ENABLE_VAL(0x4, 10, 4, 16), -+ .mdiv = REG_VAL(0x24, 10, 8), - }, - [BCM_CYGNUS_GENPLL_CAN_CLK] = { - .channel = BCM_CYGNUS_GENPLL_CAN_CLK, - .flags = IPROC_CLK_AON, -- .enable = enable_val(0x4, 11, 5, 17), -- .mdiv = reg_val(0x24, 20, 8), -+ .enable = ENABLE_VAL(0x4, 11, 5, 17), -+ .mdiv = REG_VAL(0x24, 20, 8), - }, - }; - -@@ -113,51 +113,51 @@ CLK_OF_DECLARE(cygnus_genpll, "brcm,cygn - - static const struct iproc_pll_ctrl lcpll0 = { - .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG, -- .aon = aon_val(0x0, 2, 5, 4), -- .reset = reset_val(0x0, 31, 30, 27, 3, 23, 4, 19, 4), -- .sw_ctrl = sw_ctrl_val(0x4, 31), -- .ndiv_int = reg_val(0x4, 16, 10), -- .pdiv = reg_val(0x4, 26, 4), -- .vco_ctrl = vco_ctrl_val(0x10, 0x14), -- .status = reg_val(0x18, 12, 1), -+ .aon = AON_VAL(0x0, 2, 5, 4), -+ .reset = RESET_VAL(0x0, 31, 30, 27, 3, 23, 4, 19, 4), -+ .sw_ctrl = SW_CTRL_VAL(0x4, 31), -+ .ndiv_int = REG_VAL(0x4, 16, 10), -+ .pdiv = REG_VAL(0x4, 26, 4), -+ .vco_ctrl = VCO_CTRL_VAL(0x10, 0x14), -+ .status = REG_VAL(0x18, 12, 1), - }; - - static const struct iproc_clk_ctrl lcpll0_clk[] = { - [BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK] = { - .channel = BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK, - .flags = IPROC_CLK_AON, -- .enable = enable_val(0x0, 7, 1, 13), -- .mdiv = reg_val(0x8, 0, 8), -+ .enable = ENABLE_VAL(0x0, 7, 1, 13), -+ .mdiv = REG_VAL(0x8, 0, 8), - }, - [BCM_CYGNUS_LCPLL0_DDR_PHY_CLK] = { - .channel = BCM_CYGNUS_LCPLL0_DDR_PHY_CLK, - .flags = IPROC_CLK_AON, -- .enable = enable_val(0x0, 8, 2, 14), -- .mdiv = reg_val(0x8, 10, 8), -+ .enable = ENABLE_VAL(0x0, 8, 2, 14), -+ .mdiv = REG_VAL(0x8, 10, 8), - }, - [BCM_CYGNUS_LCPLL0_SDIO_CLK] = { - .channel = BCM_CYGNUS_LCPLL0_SDIO_CLK, - .flags = IPROC_CLK_AON, -- .enable = enable_val(0x0, 9, 3, 15), -- .mdiv = reg_val(0x8, 20, 8), -+ .enable = ENABLE_VAL(0x0, 9, 3, 15), -+ .mdiv = REG_VAL(0x8, 20, 8), - }, - [BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK] = { - .channel = BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK, - .flags = IPROC_CLK_AON, -- .enable = enable_val(0x0, 10, 4, 16), -- .mdiv = reg_val(0xc, 0, 8), -+ .enable = ENABLE_VAL(0x0, 10, 4, 16), -+ .mdiv = REG_VAL(0xc, 0, 8), - }, - [BCM_CYGNUS_LCPLL0_SMART_CARD_CLK] = { - .channel = BCM_CYGNUS_LCPLL0_SMART_CARD_CLK, - .flags = IPROC_CLK_AON, -- .enable = enable_val(0x0, 11, 5, 17), -- .mdiv = reg_val(0xc, 10, 8), -+ .enable = ENABLE_VAL(0x0, 11, 5, 17), -+ .mdiv = REG_VAL(0xc, 10, 8), - }, - [BCM_CYGNUS_LCPLL0_CH5_UNUSED] = { - .channel = BCM_CYGNUS_LCPLL0_CH5_UNUSED, - .flags = IPROC_CLK_AON, -- .enable = enable_val(0x0, 12, 6, 18), -- .mdiv = reg_val(0xc, 20, 8), -+ .enable = ENABLE_VAL(0x0, 12, 6, 18), -+ .mdiv = REG_VAL(0xc, 20, 8), - }, - }; - -@@ -189,52 +189,52 @@ static const struct iproc_pll_vco_param - static const struct iproc_pll_ctrl mipipll = { - .flags = IPROC_CLK_PLL_ASIU | IPROC_CLK_PLL_HAS_NDIV_FRAC | - IPROC_CLK_NEEDS_READ_BACK, -- .aon = aon_val(0x0, 4, 17, 16), -- .asiu = asiu_gate_val(0x0, 3), -- .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 4), -- .ndiv_int = reg_val(0x10, 20, 10), -- .ndiv_frac = reg_val(0x10, 0, 20), -- .pdiv = reg_val(0x14, 0, 4), -- .vco_ctrl = vco_ctrl_val(0x18, 0x1c), -- .status = reg_val(0x28, 12, 1), -+ .aon = AON_VAL(0x0, 4, 17, 16), -+ .asiu = ASIU_GATE_VAL(0x0, 3), -+ .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 4), -+ .ndiv_int = REG_VAL(0x10, 20, 10), -+ .ndiv_frac = REG_VAL(0x10, 0, 20), -+ .pdiv = REG_VAL(0x14, 0, 4), -+ .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c), -+ .status = REG_VAL(0x28, 12, 1), - }; - - static const struct iproc_clk_ctrl mipipll_clk[] = { - [BCM_CYGNUS_MIPIPLL_CH0_UNUSED] = { - .channel = BCM_CYGNUS_MIPIPLL_CH0_UNUSED, - .flags = IPROC_CLK_NEEDS_READ_BACK, -- .enable = enable_val(0x4, 12, 6, 18), -- .mdiv = reg_val(0x20, 0, 8), -+ .enable = ENABLE_VAL(0x4, 12, 6, 18), -+ .mdiv = REG_VAL(0x20, 0, 8), - }, - [BCM_CYGNUS_MIPIPLL_CH1_LCD] = { - .channel = BCM_CYGNUS_MIPIPLL_CH1_LCD, - .flags = IPROC_CLK_NEEDS_READ_BACK, -- .enable = enable_val(0x4, 13, 7, 19), -- .mdiv = reg_val(0x20, 10, 8), -+ .enable = ENABLE_VAL(0x4, 13, 7, 19), -+ .mdiv = REG_VAL(0x20, 10, 8), - }, - [BCM_CYGNUS_MIPIPLL_CH2_V3D] = { - .channel = BCM_CYGNUS_MIPIPLL_CH2_V3D, - .flags = IPROC_CLK_NEEDS_READ_BACK, -- .enable = enable_val(0x4, 14, 8, 20), -- .mdiv = reg_val(0x20, 20, 8), -+ .enable = ENABLE_VAL(0x4, 14, 8, 20), -+ .mdiv = REG_VAL(0x20, 20, 8), - }, - [BCM_CYGNUS_MIPIPLL_CH3_UNUSED] = { - .channel = BCM_CYGNUS_MIPIPLL_CH3_UNUSED, - .flags = IPROC_CLK_NEEDS_READ_BACK, -- .enable = enable_val(0x4, 15, 9, 21), -- .mdiv = reg_val(0x24, 0, 8), -+ .enable = ENABLE_VAL(0x4, 15, 9, 21), -+ .mdiv = REG_VAL(0x24, 0, 8), - }, - [BCM_CYGNUS_MIPIPLL_CH4_UNUSED] = { - .channel = BCM_CYGNUS_MIPIPLL_CH4_UNUSED, - .flags = IPROC_CLK_NEEDS_READ_BACK, -- .enable = enable_val(0x4, 16, 10, 22), -- .mdiv = reg_val(0x24, 10, 8), -+ .enable = ENABLE_VAL(0x4, 16, 10, 22), -+ .mdiv = REG_VAL(0x24, 10, 8), - }, - [BCM_CYGNUS_MIPIPLL_CH5_UNUSED] = { - .channel = BCM_CYGNUS_MIPIPLL_CH5_UNUSED, - .flags = IPROC_CLK_NEEDS_READ_BACK, -- .enable = enable_val(0x4, 17, 11, 23), -- .mdiv = reg_val(0x24, 20, 8), -+ .enable = ENABLE_VAL(0x4, 17, 11, 23), -+ .mdiv = REG_VAL(0x24, 20, 8), - }, - }; - -@@ -247,15 +247,15 @@ static void __init cygnus_mipipll_clk_in - CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll", cygnus_mipipll_clk_init); - - static const struct iproc_asiu_div asiu_div[] = { -- [BCM_CYGNUS_ASIU_KEYPAD_CLK] = asiu_div_val(0x0, 31, 16, 10, 0, 10), -- [BCM_CYGNUS_ASIU_ADC_CLK] = asiu_div_val(0x4, 31, 16, 10, 0, 10), -- [BCM_CYGNUS_ASIU_PWM_CLK] = asiu_div_val(0x8, 31, 16, 10, 0, 10), -+ [BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_DIV_VAL(0x0, 31, 16, 10, 0, 10), -+ [BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_DIV_VAL(0x4, 31, 16, 10, 0, 10), -+ [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_DIV_VAL(0x8, 31, 16, 10, 0, 10), - }; - - static const struct iproc_asiu_gate asiu_gate[] = { -- [BCM_CYGNUS_ASIU_KEYPAD_CLK] = asiu_gate_val(0x0, 7), -- [BCM_CYGNUS_ASIU_ADC_CLK] = asiu_gate_val(0x0, 9), -- [BCM_CYGNUS_ASIU_PWM_CLK] = asiu_gate_val(IPROC_CLK_INVALID_OFFSET, 0), -+ [BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_GATE_VAL(0x0, 7), -+ [BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_GATE_VAL(0x0, 9), -+ [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_GATE_VAL(IPROC_CLK_INVALID_OFFSET, 0), - }; - - static void __init cygnus_asiu_init(struct device_node *node) diff --git a/target/linux/bcm53xx/patches-4.3/045-clk-iproc-Add-PWRCTRL-support.patch b/target/linux/bcm53xx/patches-4.3/045-clk-iproc-Add-PWRCTRL-support.patch deleted file mode 100644 index 318bd5ca4e..0000000000 --- a/target/linux/bcm53xx/patches-4.3/045-clk-iproc-Add-PWRCTRL-support.patch +++ /dev/null @@ -1,120 +0,0 @@ -From 7c70cb333deb6e2f88da9c94ddd6b3b00c97b93a Mon Sep 17 00:00:00 2001 -From: Jon Mason <jonmason@broadcom.com> -Date: Thu, 15 Oct 2015 15:48:26 -0400 -Subject: [PATCH 45/50] clk: iproc: Add PWRCTRL support - -Some iProc SoC clocks use a different way to control clock power, via -the PWRDWN bit in the PLL control register. Since the PLL control -register is used to access the PWRDWN bit, there is no need for the -pwr_base when this is being used. A new flag, IPROC_CLK_EMBED_PWRCTRL, -has been added to identify this usage. We can use the AON interface to -write the values to enable/disable PWRDOWN. - -Signed-off-by: Jon Mason <jonmason@broadcom.com> ---- - drivers/clk/bcm/clk-iproc-pll.c | 55 ++++++++++++++++++++++++++++------------- - drivers/clk/bcm/clk-iproc.h | 6 +++++ - 2 files changed, 44 insertions(+), 17 deletions(-) - ---- a/drivers/clk/bcm/clk-iproc-pll.c -+++ b/drivers/clk/bcm/clk-iproc-pll.c -@@ -148,14 +148,25 @@ static void __pll_disable(struct iproc_p - writel(val, pll->asiu_base + ctrl->asiu.offset); - } - -- /* latch input value so core power can be shut down */ -- val = readl(pll->pwr_base + ctrl->aon.offset); -- val |= (1 << ctrl->aon.iso_shift); -- writel(val, pll->pwr_base + ctrl->aon.offset); -- -- /* power down the core */ -- val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); -- writel(val, pll->pwr_base + ctrl->aon.offset); -+ if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { -+ val = readl(pll->pll_base + ctrl->aon.offset); -+ val |= (bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); -+ writel(val, pll->pll_base + ctrl->aon.offset); -+ -+ if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) -+ readl(pll->pll_base + ctrl->aon.offset); -+ } -+ -+ if (pll->pwr_base) { -+ /* latch input value so core power can be shut down */ -+ val = readl(pll->pwr_base + ctrl->aon.offset); -+ val |= (1 << ctrl->aon.iso_shift); -+ writel(val, pll->pwr_base + ctrl->aon.offset); -+ -+ /* power down the core */ -+ val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); -+ writel(val, pll->pwr_base + ctrl->aon.offset); -+ } - } - - static int __pll_enable(struct iproc_pll *pll) -@@ -163,11 +174,22 @@ static int __pll_enable(struct iproc_pll - const struct iproc_pll_ctrl *ctrl = pll->ctrl; - u32 val; - -- /* power up the PLL and make sure it's not latched */ -- val = readl(pll->pwr_base + ctrl->aon.offset); -- val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; -- val &= ~(1 << ctrl->aon.iso_shift); -- writel(val, pll->pwr_base + ctrl->aon.offset); -+ if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { -+ val = readl(pll->pll_base + ctrl->aon.offset); -+ val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); -+ writel(val, pll->pll_base + ctrl->aon.offset); -+ -+ if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) -+ readl(pll->pll_base + ctrl->aon.offset); -+ } -+ -+ if (pll->pwr_base) { -+ /* power up the PLL and make sure it's not latched */ -+ val = readl(pll->pwr_base + ctrl->aon.offset); -+ val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; -+ val &= ~(1 << ctrl->aon.iso_shift); -+ writel(val, pll->pwr_base + ctrl->aon.offset); -+ } - - /* certain PLLs also need to be ungated from the ASIU top level */ - if (ctrl->flags & IPROC_CLK_PLL_ASIU) { -@@ -607,9 +629,8 @@ void __init iproc_pll_clk_setup(struct d - if (WARN_ON(!pll->pll_base)) - goto err_pll_iomap; - -+ /* Some SoCs do not require the pwr_base, thus failing is not fatal */ - pll->pwr_base = of_iomap(node, 1); -- if (WARN_ON(!pll->pwr_base)) -- goto err_pwr_iomap; - - /* some PLLs require gating control at the top ASIU level */ - if (pll_ctrl->flags & IPROC_CLK_PLL_ASIU) { -@@ -692,9 +713,9 @@ err_pll_register: - iounmap(pll->asiu_base); - - err_asiu_iomap: -- iounmap(pll->pwr_base); -+ if (pll->pwr_base) -+ iounmap(pll->pwr_base); - --err_pwr_iomap: - iounmap(pll->pll_base); - - err_pll_iomap: ---- a/drivers/clk/bcm/clk-iproc.h -+++ b/drivers/clk/bcm/clk-iproc.h -@@ -49,6 +49,12 @@ - #define IPROC_CLK_PLL_NEEDS_SW_CFG BIT(4) - - /* -+ * Some PLLs use a different way to control clock power, via the PWRDWN bit in -+ * the PLL control register -+ */ -+#define IPROC_CLK_EMBED_PWRCTRL BIT(5) -+ -+/* - * Parameters for VCO frequency configuration - * - * VCO frequency = diff --git a/target/linux/bcm53xx/patches-4.3/046-clk-nsp-add-clock-support-for-Broadcom-Northstar-Plu.patch b/target/linux/bcm53xx/patches-4.3/046-clk-nsp-add-clock-support-for-Broadcom-Northstar-Plu.patch deleted file mode 100644 index c8eda8d102..0000000000 --- a/target/linux/bcm53xx/patches-4.3/046-clk-nsp-add-clock-support-for-Broadcom-Northstar-Plu.patch +++ /dev/null @@ -1,219 +0,0 @@ -From d358480591b34d081806ecb5a9474930a4d59f8a Mon Sep 17 00:00:00 2001 -From: Jon Mason <jonmason@broadcom.com> -Date: Thu, 15 Oct 2015 15:48:27 -0400 -Subject: [PATCH 46/50] clk: nsp: add clock support for Broadcom Northstar Plus - SoC - -The Broadcom Northstar Plus SoC is architected under the iProc -architecture. It has the following PLLs: ARMPLL, GENPLL, LCPLL0, all -derived from an onboard crystal. - -Signed-off-by: Jon Mason <jonmason@broadcom.com> ---- - drivers/clk/bcm/Makefile | 2 + - drivers/clk/bcm/clk-nsp.c | 135 ++++++++++++++++++++++++++++++++++++ - include/dt-bindings/clock/bcm-nsp.h | 51 ++++++++++++++ - 3 files changed, 188 insertions(+) - create mode 100644 drivers/clk/bcm/clk-nsp.c - create mode 100644 include/dt-bindings/clock/bcm-nsp.h - ---- a/drivers/clk/bcm/Makefile -+++ b/drivers/clk/bcm/Makefile -@@ -4,3 +4,5 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281 - obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o - obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o - obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o -+obj-$(CONFIG_ARCH_BCM_NSP) += clk-nsp.o -+obj-$(CONFIG_ARCH_BCM_5301X) += clk-nsp.o ---- /dev/null -+++ b/drivers/clk/bcm/clk-nsp.c -@@ -0,0 +1,135 @@ -+/* -+ * Copyright (C) 2015 Broadcom Corporation -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation version 2. -+ * -+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any -+ * kind, whether express or implied; without even the implied warranty -+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include <linux/kernel.h> -+#include <linux/err.h> -+#include <linux/clk-provider.h> -+#include <linux/io.h> -+#include <linux/of.h> -+#include <linux/of_address.h> -+ -+#include <dt-bindings/clock/bcm-nsp.h> -+#include "clk-iproc.h" -+ -+#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, } -+ -+#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \ -+ .pwr_shift = ps, .iso_shift = is } -+ -+#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ -+ .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \ -+ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ -+ .ka_width = kaw } -+ -+#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \ -+ .hold_shift = hs, .bypass_shift = bs } -+ -+static void __init nsp_armpll_init(struct device_node *node) -+{ -+ iproc_armpll_setup(node); -+} -+CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init); -+ -+static const struct iproc_pll_ctrl genpll = { -+ .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL, -+ .aon = AON_VAL(0x0, 1, 12, 0), -+ .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3), -+ .ndiv_int = REG_VAL(0x14, 20, 10), -+ .ndiv_frac = REG_VAL(0x14, 0, 20), -+ .pdiv = REG_VAL(0x18, 24, 3), -+ .status = REG_VAL(0x20, 12, 1), -+}; -+ -+static const struct iproc_clk_ctrl genpll_clk[] = { -+ [BCM_NSP_GENPLL_PHY_CLK] = { -+ .channel = BCM_NSP_GENPLL_PHY_CLK, -+ .flags = IPROC_CLK_AON, -+ .enable = ENABLE_VAL(0x4, 12, 6, 18), -+ .mdiv = REG_VAL(0x18, 16, 8), -+ }, -+ [BCM_NSP_GENPLL_ENET_SW_CLK] = { -+ .channel = BCM_NSP_GENPLL_ENET_SW_CLK, -+ .flags = IPROC_CLK_AON, -+ .enable = ENABLE_VAL(0x4, 13, 7, 19), -+ .mdiv = REG_VAL(0x18, 8, 8), -+ }, -+ [BCM_NSP_GENPLL_USB_PHY_REF_CLK] = { -+ .channel = BCM_NSP_GENPLL_USB_PHY_REF_CLK, -+ .flags = IPROC_CLK_AON, -+ .enable = ENABLE_VAL(0x4, 14, 8, 20), -+ .mdiv = REG_VAL(0x18, 0, 8), -+ }, -+ [BCM_NSP_GENPLL_IPROCFAST_CLK] = { -+ .channel = BCM_NSP_GENPLL_IPROCFAST_CLK, -+ .flags = IPROC_CLK_AON, -+ .enable = ENABLE_VAL(0x4, 15, 9, 21), -+ .mdiv = REG_VAL(0x1c, 16, 8), -+ }, -+ [BCM_NSP_GENPLL_SATA1_CLK] = { -+ .channel = BCM_NSP_GENPLL_SATA1_CLK, -+ .flags = IPROC_CLK_AON, -+ .enable = ENABLE_VAL(0x4, 16, 10, 22), -+ .mdiv = REG_VAL(0x1c, 8, 8), -+ }, -+ [BCM_NSP_GENPLL_SATA2_CLK] = { -+ .channel = BCM_NSP_GENPLL_SATA2_CLK, -+ .flags = IPROC_CLK_AON, -+ .enable = ENABLE_VAL(0x4, 17, 11, 23), -+ .mdiv = REG_VAL(0x1c, 0, 8), -+ }, -+}; -+ -+static void __init nsp_genpll_clk_init(struct device_node *node) -+{ -+ iproc_pll_clk_setup(node, &genpll, NULL, 0, genpll_clk, -+ ARRAY_SIZE(genpll_clk)); -+} -+CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp-genpll", nsp_genpll_clk_init); -+ -+static const struct iproc_pll_ctrl lcpll0 = { -+ .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL, -+ .aon = AON_VAL(0x0, 1, 24, 0), -+ .reset = RESET_VAL(0x0, 23, 22, 16, 3, 12, 4, 19, 4), -+ .ndiv_int = REG_VAL(0x4, 20, 8), -+ .ndiv_frac = REG_VAL(0x4, 0, 20), -+ .pdiv = REG_VAL(0x4, 28, 3), -+ .status = REG_VAL(0x10, 12, 1), -+}; -+ -+static const struct iproc_clk_ctrl lcpll0_clk[] = { -+ [BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK] = { -+ .channel = BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK, -+ .flags = IPROC_CLK_AON, -+ .enable = ENABLE_VAL(0x0, 6, 3, 9), -+ .mdiv = REG_VAL(0x8, 24, 8), -+ }, -+ [BCM_NSP_LCPLL0_SDIO_CLK] = { -+ .channel = BCM_NSP_LCPLL0_SDIO_CLK, -+ .flags = IPROC_CLK_AON, -+ .enable = ENABLE_VAL(0x0, 7, 4, 10), -+ .mdiv = REG_VAL(0x8, 16, 8), -+ }, -+ [BCM_NSP_LCPLL0_DDR_PHY_CLK] = { -+ .channel = BCM_NSP_LCPLL0_DDR_PHY_CLK, -+ .flags = IPROC_CLK_AON, -+ .enable = ENABLE_VAL(0x0, 8, 5, 11), -+ .mdiv = REG_VAL(0x8, 8, 8), -+ }, -+}; -+ -+static void __init nsp_lcpll0_clk_init(struct device_node *node) -+{ -+ iproc_pll_clk_setup(node, &lcpll0, NULL, 0, lcpll0_clk, -+ ARRAY_SIZE(lcpll0_clk)); -+} -+CLK_OF_DECLARE(nsp_lcpll0_clk, "brcm,nsp-lcpll0", nsp_lcpll0_clk_init); ---- /dev/null -+++ b/include/dt-bindings/clock/bcm-nsp.h -@@ -0,0 +1,51 @@ -+/* -+ * BSD LICENSE -+ * -+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Broadcom Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef _CLOCK_BCM_NSP_H -+#define _CLOCK_BCM_NSP_H -+ -+/* GENPLL clock channel ID */ -+#define BCM_NSP_GENPLL 0 -+#define BCM_NSP_GENPLL_PHY_CLK 1 -+#define BCM_NSP_GENPLL_ENET_SW_CLK 2 -+#define BCM_NSP_GENPLL_USB_PHY_REF_CLK 3 -+#define BCM_NSP_GENPLL_IPROCFAST_CLK 4 -+#define BCM_NSP_GENPLL_SATA1_CLK 5 -+#define BCM_NSP_GENPLL_SATA2_CLK 6 -+ -+/* LCPLL0 clock channel ID */ -+#define BCM_NSP_LCPLL0 0 -+#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK 1 -+#define BCM_NSP_LCPLL0_SDIO_CLK 2 -+#define BCM_NSP_LCPLL0_DDR_PHY_CLK 3 -+ -+#endif /* _CLOCK_BCM_NSP_H */ diff --git a/target/linux/bcm53xx/patches-4.3/047-clk-iproc-Add-PLL-base-write-function.patch b/target/linux/bcm53xx/patches-4.3/047-clk-iproc-Add-PLL-base-write-function.patch deleted file mode 100644 index 2f07cc6656..0000000000 --- a/target/linux/bcm53xx/patches-4.3/047-clk-iproc-Add-PLL-base-write-function.patch +++ /dev/null @@ -1,223 +0,0 @@ -From acbb7a3de7e4d83b23c0bbb3eaf77d15a041d865 Mon Sep 17 00:00:00 2001 -From: Jon Mason <jonmason@broadcom.com> -Date: Thu, 15 Oct 2015 15:48:28 -0400 -Subject: [PATCH 47/50] clk: iproc: Add PLL base write function - -All writes to the PLL base address must be flushed if the -IPROC_CLK_NEEDS_READ_BACK flag is set. If we add a function to make the -necessary write and reads, we can make sure that any future code which -makes PLL base writes will do the correct thing. - -Signed-off-by: Jon Mason <jonmason@broadcom.com> ---- - drivers/clk/bcm/clk-iproc-pll.c | 80 +++++++++++++++++------------------------ - 1 file changed, 33 insertions(+), 47 deletions(-) - ---- a/drivers/clk/bcm/clk-iproc-pll.c -+++ b/drivers/clk/bcm/clk-iproc-pll.c -@@ -137,6 +137,18 @@ static int pll_wait_for_lock(struct ipro - return -EIO; - } - -+static void iproc_pll_write(const struct iproc_pll *pll, void __iomem *base, -+ const u32 offset, u32 val) -+{ -+ const struct iproc_pll_ctrl *ctrl = pll->ctrl; -+ -+ writel(val, base + offset); -+ -+ if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK && -+ base == pll->pll_base)) -+ val = readl(base + offset); -+} -+ - static void __pll_disable(struct iproc_pll *pll) - { - const struct iproc_pll_ctrl *ctrl = pll->ctrl; -@@ -145,27 +157,24 @@ static void __pll_disable(struct iproc_p - if (ctrl->flags & IPROC_CLK_PLL_ASIU) { - val = readl(pll->asiu_base + ctrl->asiu.offset); - val &= ~(1 << ctrl->asiu.en_shift); -- writel(val, pll->asiu_base + ctrl->asiu.offset); -+ iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); - } - - if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { - val = readl(pll->pll_base + ctrl->aon.offset); - val |= (bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); -- writel(val, pll->pll_base + ctrl->aon.offset); -- -- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) -- readl(pll->pll_base + ctrl->aon.offset); -+ iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val); - } - - if (pll->pwr_base) { - /* latch input value so core power can be shut down */ - val = readl(pll->pwr_base + ctrl->aon.offset); - val |= (1 << ctrl->aon.iso_shift); -- writel(val, pll->pwr_base + ctrl->aon.offset); -+ iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); - - /* power down the core */ - val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); -- writel(val, pll->pwr_base + ctrl->aon.offset); -+ iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); - } - } - -@@ -177,10 +186,7 @@ static int __pll_enable(struct iproc_pll - if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { - val = readl(pll->pll_base + ctrl->aon.offset); - val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); -- writel(val, pll->pll_base + ctrl->aon.offset); -- -- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) -- readl(pll->pll_base + ctrl->aon.offset); -+ iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val); - } - - if (pll->pwr_base) { -@@ -188,14 +194,14 @@ static int __pll_enable(struct iproc_pll - val = readl(pll->pwr_base + ctrl->aon.offset); - val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; - val &= ~(1 << ctrl->aon.iso_shift); -- writel(val, pll->pwr_base + ctrl->aon.offset); -+ iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); - } - - /* certain PLLs also need to be ungated from the ASIU top level */ - if (ctrl->flags & IPROC_CLK_PLL_ASIU) { - val = readl(pll->asiu_base + ctrl->asiu.offset); - val |= (1 << ctrl->asiu.en_shift); -- writel(val, pll->asiu_base + ctrl->asiu.offset); -+ iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); - } - - return 0; -@@ -209,9 +215,7 @@ static void __pll_put_in_reset(struct ip - - val = readl(pll->pll_base + reset->offset); - val &= ~(1 << reset->reset_shift | 1 << reset->p_reset_shift); -- writel(val, pll->pll_base + reset->offset); -- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) -- readl(pll->pll_base + reset->offset); -+ iproc_pll_write(pll, pll->pll_base, reset->offset, val); - } - - static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp, -@@ -228,9 +232,7 @@ static void __pll_bring_out_reset(struct - val |= ki << reset->ki_shift | kp << reset->kp_shift | - ka << reset->ka_shift; - val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift; -- writel(val, pll->pll_base + reset->offset); -- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) -- readl(pll->pll_base + reset->offset); -+ iproc_pll_write(pll, pll->pll_base, reset->offset, val); - } - - static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index, -@@ -285,9 +287,8 @@ static int pll_set_rate(struct iproc_clk - /* put PLL in reset */ - __pll_put_in_reset(pll); - -- writel(0, pll->pll_base + ctrl->vco_ctrl.u_offset); -- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) -- readl(pll->pll_base + ctrl->vco_ctrl.u_offset); -+ iproc_pll_write(pll, pll->pll_base, ctrl->vco_ctrl.u_offset, 0); -+ - val = readl(pll->pll_base + ctrl->vco_ctrl.l_offset); - - if (rate >= VCO_LOW && rate < VCO_MID) -@@ -298,17 +299,13 @@ static int pll_set_rate(struct iproc_clk - else - val |= (1 << PLL_VCO_HIGH_SHIFT); - -- writel(val, pll->pll_base + ctrl->vco_ctrl.l_offset); -- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) -- readl(pll->pll_base + ctrl->vco_ctrl.l_offset); -+ iproc_pll_write(pll, pll->pll_base, ctrl->vco_ctrl.l_offset, val); - - /* program integer part of NDIV */ - val = readl(pll->pll_base + ctrl->ndiv_int.offset); - val &= ~(bit_mask(ctrl->ndiv_int.width) << ctrl->ndiv_int.shift); - val |= vco->ndiv_int << ctrl->ndiv_int.shift; -- writel(val, pll->pll_base + ctrl->ndiv_int.offset); -- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) -- readl(pll->pll_base + ctrl->ndiv_int.offset); -+ iproc_pll_write(pll, pll->pll_base, ctrl->ndiv_int.offset, val); - - /* program fractional part of NDIV */ - if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { -@@ -316,18 +313,15 @@ static int pll_set_rate(struct iproc_clk - val &= ~(bit_mask(ctrl->ndiv_frac.width) << - ctrl->ndiv_frac.shift); - val |= vco->ndiv_frac << ctrl->ndiv_frac.shift; -- writel(val, pll->pll_base + ctrl->ndiv_frac.offset); -- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) -- readl(pll->pll_base + ctrl->ndiv_frac.offset); -+ iproc_pll_write(pll, pll->pll_base, ctrl->ndiv_frac.offset, -+ val); - } - - /* program PDIV */ - val = readl(pll->pll_base + ctrl->pdiv.offset); - val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift); - val |= vco->pdiv << ctrl->pdiv.shift; -- writel(val, pll->pll_base + ctrl->pdiv.offset); -- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) -- readl(pll->pll_base + ctrl->pdiv.offset); -+ iproc_pll_write(pll, pll->pll_base, ctrl->pdiv.offset, val); - - __pll_bring_out_reset(pll, kp, ka, ki); - -@@ -464,14 +458,12 @@ static int iproc_clk_enable(struct clk_h - /* channel enable is active low */ - val = readl(pll->pll_base + ctrl->enable.offset); - val &= ~(1 << ctrl->enable.enable_shift); -- writel(val, pll->pll_base + ctrl->enable.offset); -+ iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); - - /* also make sure channel is not held */ - val = readl(pll->pll_base + ctrl->enable.offset); - val &= ~(1 << ctrl->enable.hold_shift); -- writel(val, pll->pll_base + ctrl->enable.offset); -- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) -- readl(pll->pll_base + ctrl->enable.offset); -+ iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); - - return 0; - } -@@ -488,9 +480,7 @@ static void iproc_clk_disable(struct clk - - val = readl(pll->pll_base + ctrl->enable.offset); - val |= 1 << ctrl->enable.enable_shift; -- writel(val, pll->pll_base + ctrl->enable.offset); -- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) -- readl(pll->pll_base + ctrl->enable.offset); -+ iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); - } - - static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw, -@@ -559,9 +549,7 @@ static int iproc_clk_set_rate(struct clk - val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); - val |= div << ctrl->mdiv.shift; - } -- writel(val, pll->pll_base + ctrl->mdiv.offset); -- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) -- readl(pll->pll_base + ctrl->mdiv.offset); -+ iproc_pll_write(pll, pll->pll_base, ctrl->mdiv.offset, val); - clk->rate = parent_rate / div; - - return 0; -@@ -588,9 +576,7 @@ static void iproc_pll_sw_cfg(struct ipro - - val = readl(pll->pll_base + ctrl->sw_ctrl.offset); - val |= BIT(ctrl->sw_ctrl.shift); -- writel(val, pll->pll_base + ctrl->sw_ctrl.offset); -- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) -- readl(pll->pll_base + ctrl->sw_ctrl.offset); -+ iproc_pll_write(pll, pll->pll_base, ctrl->sw_ctrl.offset, val); - } - } - diff --git a/target/linux/bcm53xx/patches-4.3/048-clk-iproc-Split-off-dig_filter.patch b/target/linux/bcm53xx/patches-4.3/048-clk-iproc-Split-off-dig_filter.patch deleted file mode 100644 index 528311f8d6..0000000000 --- a/target/linux/bcm53xx/patches-4.3/048-clk-iproc-Split-off-dig_filter.patch +++ /dev/null @@ -1,158 +0,0 @@ -From fb9e4932d17ad32786d03cb672fb62f2b337acf5 Mon Sep 17 00:00:00 2001 -From: Jon Mason <jonmason@broadcom.com> -Date: Thu, 15 Oct 2015 15:48:29 -0400 -Subject: [PATCH 48/50] clk: iproc: Split off dig_filter - -The PLL loop filter/gain can be located in a separate register on some -SoCs. Split these off into a separate variable, so that an offset can -be added if necessary. Also, make the necessary modifications to the -Cygnus and NSP drivers for this change. - -Signed-off-by: Jon Mason <jonmason@broadcom.com> ---- - drivers/clk/bcm/clk-cygnus.c | 17 +++++++++++------ - drivers/clk/bcm/clk-iproc-pll.c | 14 +++++++++----- - drivers/clk/bcm/clk-iproc.h | 10 +++++++++- - drivers/clk/bcm/clk-nsp.c | 14 +++++++++----- - 4 files changed, 38 insertions(+), 17 deletions(-) - ---- a/drivers/clk/bcm/clk-cygnus.c -+++ b/drivers/clk/bcm/clk-cygnus.c -@@ -34,9 +34,11 @@ - { .offset = o, .en_shift = es, .high_shift = hs, \ - .high_width = hw, .low_shift = ls, .low_width = lw } - --#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ -- .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \ -- .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ -+#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \ -+ .p_reset_shift = prs } -+ -+#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\ -+ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ - .ka_width = kaw } - - #define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo } -@@ -56,7 +58,8 @@ static const struct iproc_pll_ctrl genpl - .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC | - IPROC_CLK_PLL_NEEDS_SW_CFG, - .aon = AON_VAL(0x0, 2, 1, 0), -- .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3), -+ .reset = RESET_VAL(0x0, 11, 10), -+ .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3), - .sw_ctrl = SW_CTRL_VAL(0x10, 31), - .ndiv_int = REG_VAL(0x10, 20, 10), - .ndiv_frac = REG_VAL(0x10, 0, 20), -@@ -114,7 +117,8 @@ CLK_OF_DECLARE(cygnus_genpll, "brcm,cygn - static const struct iproc_pll_ctrl lcpll0 = { - .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG, - .aon = AON_VAL(0x0, 2, 5, 4), -- .reset = RESET_VAL(0x0, 31, 30, 27, 3, 23, 4, 19, 4), -+ .reset = RESET_VAL(0x0, 31, 30), -+ .dig_filter = DF_VAL(0x0, 27, 3, 23, 4, 19, 4), - .sw_ctrl = SW_CTRL_VAL(0x4, 31), - .ndiv_int = REG_VAL(0x4, 16, 10), - .pdiv = REG_VAL(0x4, 26, 4), -@@ -191,7 +195,8 @@ static const struct iproc_pll_ctrl mipip - IPROC_CLK_NEEDS_READ_BACK, - .aon = AON_VAL(0x0, 4, 17, 16), - .asiu = ASIU_GATE_VAL(0x0, 3), -- .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 4), -+ .reset = RESET_VAL(0x0, 11, 10), -+ .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 4), - .ndiv_int = REG_VAL(0x10, 20, 10), - .ndiv_frac = REG_VAL(0x10, 0, 20), - .pdiv = REG_VAL(0x14, 0, 4), ---- a/drivers/clk/bcm/clk-iproc-pll.c -+++ b/drivers/clk/bcm/clk-iproc-pll.c -@@ -224,13 +224,17 @@ static void __pll_bring_out_reset(struct - u32 val; - const struct iproc_pll_ctrl *ctrl = pll->ctrl; - const struct iproc_pll_reset_ctrl *reset = &ctrl->reset; -+ const struct iproc_pll_dig_filter_ctrl *dig_filter = &ctrl->dig_filter; -+ -+ val = readl(pll->pll_base + dig_filter->offset); -+ val &= ~(bit_mask(dig_filter->ki_width) << dig_filter->ki_shift | -+ bit_mask(dig_filter->kp_width) << dig_filter->kp_shift | -+ bit_mask(dig_filter->ka_width) << dig_filter->ka_shift); -+ val |= ki << dig_filter->ki_shift | kp << dig_filter->kp_shift | -+ ka << dig_filter->ka_shift; -+ iproc_pll_write(pll, pll->pll_base, dig_filter->offset, val); - - val = readl(pll->pll_base + reset->offset); -- val &= ~(bit_mask(reset->ki_width) << reset->ki_shift | -- bit_mask(reset->kp_width) << reset->kp_shift | -- bit_mask(reset->ka_width) << reset->ka_shift); -- val |= ki << reset->ki_shift | kp << reset->kp_shift | -- ka << reset->ka_shift; - val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift; - iproc_pll_write(pll, pll->pll_base, reset->offset, val); - } ---- a/drivers/clk/bcm/clk-iproc.h -+++ b/drivers/clk/bcm/clk-iproc.h -@@ -94,12 +94,19 @@ struct iproc_pll_aon_pwr_ctrl { - }; - - /* -- * Control of the PLL reset, with Ki, Kp, and Ka parameters -+ * Control of the PLL reset - */ - struct iproc_pll_reset_ctrl { - unsigned int offset; - unsigned int reset_shift; - unsigned int p_reset_shift; -+}; -+ -+/* -+ * Control of the Ki, Kp, and Ka parameters -+ */ -+struct iproc_pll_dig_filter_ctrl { -+ unsigned int offset; - unsigned int ki_shift; - unsigned int ki_width; - unsigned int kp_shift; -@@ -129,6 +136,7 @@ struct iproc_pll_ctrl { - struct iproc_pll_aon_pwr_ctrl aon; - struct iproc_asiu_gate asiu; - struct iproc_pll_reset_ctrl reset; -+ struct iproc_pll_dig_filter_ctrl dig_filter; - struct iproc_pll_sw_ctrl sw_ctrl; - struct iproc_clk_reg_op ndiv_int; - struct iproc_clk_reg_op ndiv_frac; ---- a/drivers/clk/bcm/clk-nsp.c -+++ b/drivers/clk/bcm/clk-nsp.c -@@ -26,9 +26,11 @@ - #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \ - .pwr_shift = ps, .iso_shift = is } - --#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ -- .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \ -- .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ -+#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \ -+ .p_reset_shift = prs } -+ -+#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\ -+ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ - .ka_width = kaw } - - #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \ -@@ -43,7 +45,8 @@ CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-arm - static const struct iproc_pll_ctrl genpll = { - .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL, - .aon = AON_VAL(0x0, 1, 12, 0), -- .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3), -+ .reset = RESET_VAL(0x0, 11, 10), -+ .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3), - .ndiv_int = REG_VAL(0x14, 20, 10), - .ndiv_frac = REG_VAL(0x14, 0, 20), - .pdiv = REG_VAL(0x18, 24, 3), -@@ -99,7 +102,8 @@ CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp - static const struct iproc_pll_ctrl lcpll0 = { - .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL, - .aon = AON_VAL(0x0, 1, 24, 0), -- .reset = RESET_VAL(0x0, 23, 22, 16, 3, 12, 4, 19, 4), -+ .reset = RESET_VAL(0x0, 23, 22), -+ .dig_filter = DF_VAL(0x0, 16, 3, 12, 4, 19, 4), - .ndiv_int = REG_VAL(0x4, 20, 8), - .ndiv_frac = REG_VAL(0x4, 0, 20), - .pdiv = REG_VAL(0x4, 28, 3), diff --git a/target/linux/bcm53xx/patches-4.3/049-clk-iproc-Separate-status-and-control-variables.patch b/target/linux/bcm53xx/patches-4.3/049-clk-iproc-Separate-status-and-control-variables.patch deleted file mode 100644 index 1e7cbc0d89..0000000000 --- a/target/linux/bcm53xx/patches-4.3/049-clk-iproc-Separate-status-and-control-variables.patch +++ /dev/null @@ -1,319 +0,0 @@ -From eeb32564795a3584dba6281f445ff2aa552be36b Mon Sep 17 00:00:00 2001 -From: Jon Mason <jonmason@broadcom.com> -Date: Thu, 15 Oct 2015 15:48:30 -0400 -Subject: [PATCH 49/50] clk: iproc: Separate status and control variables - -Some PLLs have separate registers for Status and Control. The means the -pll_base needs to be split into 2 new variables, so that those PLLs can -specify device tree registers for those independently. Also, add a new -driver flag to identify this presence of the split, and let the driver -know that additional registers need to be used. - -Signed-off-by: Jon Mason <jonmason@broadcom.com> ---- - drivers/clk/bcm/clk-iproc-pll.c | 96 ++++++++++++++++++++++++----------------- - drivers/clk/bcm/clk-iproc.h | 6 +++ - 2 files changed, 62 insertions(+), 40 deletions(-) - ---- a/drivers/clk/bcm/clk-iproc-pll.c -+++ b/drivers/clk/bcm/clk-iproc-pll.c -@@ -74,7 +74,8 @@ struct iproc_clk { - }; - - struct iproc_pll { -- void __iomem *pll_base; -+ void __iomem *status_base; -+ void __iomem *control_base; - void __iomem *pwr_base; - void __iomem *asiu_base; - -@@ -127,7 +128,7 @@ static int pll_wait_for_lock(struct ipro - const struct iproc_pll_ctrl *ctrl = pll->ctrl; - - for (i = 0; i < LOCK_DELAY; i++) { -- u32 val = readl(pll->pll_base + ctrl->status.offset); -+ u32 val = readl(pll->status_base + ctrl->status.offset); - - if (val & (1 << ctrl->status.shift)) - return 0; -@@ -145,7 +146,7 @@ static void iproc_pll_write(const struct - writel(val, base + offset); - - if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK && -- base == pll->pll_base)) -+ (base == pll->status_base || base == pll->control_base))) - val = readl(base + offset); - } - -@@ -161,9 +162,9 @@ static void __pll_disable(struct iproc_p - } - - if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { -- val = readl(pll->pll_base + ctrl->aon.offset); -+ val = readl(pll->control_base + ctrl->aon.offset); - val |= (bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); -- iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val); -+ iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val); - } - - if (pll->pwr_base) { -@@ -184,9 +185,9 @@ static int __pll_enable(struct iproc_pll - u32 val; - - if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { -- val = readl(pll->pll_base + ctrl->aon.offset); -+ val = readl(pll->control_base + ctrl->aon.offset); - val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); -- iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val); -+ iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val); - } - - if (pll->pwr_base) { -@@ -213,9 +214,9 @@ static void __pll_put_in_reset(struct ip - const struct iproc_pll_ctrl *ctrl = pll->ctrl; - const struct iproc_pll_reset_ctrl *reset = &ctrl->reset; - -- val = readl(pll->pll_base + reset->offset); -+ val = readl(pll->control_base + reset->offset); - val &= ~(1 << reset->reset_shift | 1 << reset->p_reset_shift); -- iproc_pll_write(pll, pll->pll_base, reset->offset, val); -+ iproc_pll_write(pll, pll->control_base, reset->offset, val); - } - - static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp, -@@ -226,17 +227,17 @@ static void __pll_bring_out_reset(struct - const struct iproc_pll_reset_ctrl *reset = &ctrl->reset; - const struct iproc_pll_dig_filter_ctrl *dig_filter = &ctrl->dig_filter; - -- val = readl(pll->pll_base + dig_filter->offset); -+ val = readl(pll->control_base + dig_filter->offset); - val &= ~(bit_mask(dig_filter->ki_width) << dig_filter->ki_shift | - bit_mask(dig_filter->kp_width) << dig_filter->kp_shift | - bit_mask(dig_filter->ka_width) << dig_filter->ka_shift); - val |= ki << dig_filter->ki_shift | kp << dig_filter->kp_shift | - ka << dig_filter->ka_shift; -- iproc_pll_write(pll, pll->pll_base, dig_filter->offset, val); -+ iproc_pll_write(pll, pll->control_base, dig_filter->offset, val); - -- val = readl(pll->pll_base + reset->offset); -+ val = readl(pll->control_base + reset->offset); - val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift; -- iproc_pll_write(pll, pll->pll_base, reset->offset, val); -+ iproc_pll_write(pll, pll->control_base, reset->offset, val); - } - - static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index, -@@ -291,9 +292,9 @@ static int pll_set_rate(struct iproc_clk - /* put PLL in reset */ - __pll_put_in_reset(pll); - -- iproc_pll_write(pll, pll->pll_base, ctrl->vco_ctrl.u_offset, 0); -+ iproc_pll_write(pll, pll->control_base, ctrl->vco_ctrl.u_offset, 0); - -- val = readl(pll->pll_base + ctrl->vco_ctrl.l_offset); -+ val = readl(pll->control_base + ctrl->vco_ctrl.l_offset); - - if (rate >= VCO_LOW && rate < VCO_MID) - val |= (1 << PLL_VCO_LOW_SHIFT); -@@ -303,29 +304,29 @@ static int pll_set_rate(struct iproc_clk - else - val |= (1 << PLL_VCO_HIGH_SHIFT); - -- iproc_pll_write(pll, pll->pll_base, ctrl->vco_ctrl.l_offset, val); -+ iproc_pll_write(pll, pll->control_base, ctrl->vco_ctrl.l_offset, val); - - /* program integer part of NDIV */ -- val = readl(pll->pll_base + ctrl->ndiv_int.offset); -+ val = readl(pll->control_base + ctrl->ndiv_int.offset); - val &= ~(bit_mask(ctrl->ndiv_int.width) << ctrl->ndiv_int.shift); - val |= vco->ndiv_int << ctrl->ndiv_int.shift; -- iproc_pll_write(pll, pll->pll_base, ctrl->ndiv_int.offset, val); -+ iproc_pll_write(pll, pll->control_base, ctrl->ndiv_int.offset, val); - - /* program fractional part of NDIV */ - if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { -- val = readl(pll->pll_base + ctrl->ndiv_frac.offset); -+ val = readl(pll->control_base + ctrl->ndiv_frac.offset); - val &= ~(bit_mask(ctrl->ndiv_frac.width) << - ctrl->ndiv_frac.shift); - val |= vco->ndiv_frac << ctrl->ndiv_frac.shift; -- iproc_pll_write(pll, pll->pll_base, ctrl->ndiv_frac.offset, -+ iproc_pll_write(pll, pll->control_base, ctrl->ndiv_frac.offset, - val); - } - - /* program PDIV */ -- val = readl(pll->pll_base + ctrl->pdiv.offset); -+ val = readl(pll->control_base + ctrl->pdiv.offset); - val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift); - val |= vco->pdiv << ctrl->pdiv.shift; -- iproc_pll_write(pll, pll->pll_base, ctrl->pdiv.offset, val); -+ iproc_pll_write(pll, pll->control_base, ctrl->pdiv.offset, val); - - __pll_bring_out_reset(pll, kp, ka, ki); - -@@ -372,7 +373,7 @@ static unsigned long iproc_pll_recalc_ra - return 0; - - /* PLL needs to be locked */ -- val = readl(pll->pll_base + ctrl->status.offset); -+ val = readl(pll->status_base + ctrl->status.offset); - if ((val & (1 << ctrl->status.shift)) == 0) { - clk->rate = 0; - return 0; -@@ -383,19 +384,19 @@ static unsigned long iproc_pll_recalc_ra - * - * ((ndiv_int + ndiv_frac / 2^20) * (parent clock rate / pdiv) - */ -- val = readl(pll->pll_base + ctrl->ndiv_int.offset); -+ val = readl(pll->control_base + ctrl->ndiv_int.offset); - ndiv_int = (val >> ctrl->ndiv_int.shift) & - bit_mask(ctrl->ndiv_int.width); - ndiv = ndiv_int << 20; - - if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { -- val = readl(pll->pll_base + ctrl->ndiv_frac.offset); -+ val = readl(pll->control_base + ctrl->ndiv_frac.offset); - ndiv_frac = (val >> ctrl->ndiv_frac.shift) & - bit_mask(ctrl->ndiv_frac.width); - ndiv += ndiv_frac; - } - -- val = readl(pll->pll_base + ctrl->pdiv.offset); -+ val = readl(pll->control_base + ctrl->pdiv.offset); - pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width); - - clk->rate = (ndiv * parent_rate) >> 20; -@@ -460,14 +461,14 @@ static int iproc_clk_enable(struct clk_h - u32 val; - - /* channel enable is active low */ -- val = readl(pll->pll_base + ctrl->enable.offset); -+ val = readl(pll->control_base + ctrl->enable.offset); - val &= ~(1 << ctrl->enable.enable_shift); -- iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); -+ iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val); - - /* also make sure channel is not held */ -- val = readl(pll->pll_base + ctrl->enable.offset); -+ val = readl(pll->control_base + ctrl->enable.offset); - val &= ~(1 << ctrl->enable.hold_shift); -- iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); -+ iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val); - - return 0; - } -@@ -482,9 +483,9 @@ static void iproc_clk_disable(struct clk - if (ctrl->flags & IPROC_CLK_AON) - return; - -- val = readl(pll->pll_base + ctrl->enable.offset); -+ val = readl(pll->control_base + ctrl->enable.offset); - val |= 1 << ctrl->enable.enable_shift; -- iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); -+ iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val); - } - - static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw, -@@ -499,7 +500,7 @@ static unsigned long iproc_clk_recalc_ra - if (parent_rate == 0) - return 0; - -- val = readl(pll->pll_base + ctrl->mdiv.offset); -+ val = readl(pll->control_base + ctrl->mdiv.offset); - mdiv = (val >> ctrl->mdiv.shift) & bit_mask(ctrl->mdiv.width); - if (mdiv == 0) - mdiv = 256; -@@ -546,14 +547,14 @@ static int iproc_clk_set_rate(struct clk - if (div > 256) - return -EINVAL; - -- val = readl(pll->pll_base + ctrl->mdiv.offset); -+ val = readl(pll->control_base + ctrl->mdiv.offset); - if (div == 256) { - val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); - } else { - val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); - val |= div << ctrl->mdiv.shift; - } -- iproc_pll_write(pll, pll->pll_base, ctrl->mdiv.offset, val); -+ iproc_pll_write(pll, pll->control_base, ctrl->mdiv.offset, val); - clk->rate = parent_rate / div; - - return 0; -@@ -578,9 +579,10 @@ static void iproc_pll_sw_cfg(struct ipro - if (ctrl->flags & IPROC_CLK_PLL_NEEDS_SW_CFG) { - u32 val; - -- val = readl(pll->pll_base + ctrl->sw_ctrl.offset); -+ val = readl(pll->control_base + ctrl->sw_ctrl.offset); - val |= BIT(ctrl->sw_ctrl.shift); -- iproc_pll_write(pll, pll->pll_base, ctrl->sw_ctrl.offset, val); -+ iproc_pll_write(pll, pll->control_base, ctrl->sw_ctrl.offset, -+ val); - } - } - -@@ -615,8 +617,8 @@ void __init iproc_pll_clk_setup(struct d - if (WARN_ON(!pll->clks)) - goto err_clks; - -- pll->pll_base = of_iomap(node, 0); -- if (WARN_ON(!pll->pll_base)) -+ pll->control_base = of_iomap(node, 0); -+ if (WARN_ON(!pll->control_base)) - goto err_pll_iomap; - - /* Some SoCs do not require the pwr_base, thus failing is not fatal */ -@@ -629,6 +631,16 @@ void __init iproc_pll_clk_setup(struct d - goto err_asiu_iomap; - } - -+ if (pll_ctrl->flags & IPROC_CLK_PLL_SPLIT_STAT_CTRL) { -+ /* Some SoCs have a split status/control. If this does not -+ * exist, assume they are unified. -+ */ -+ pll->status_base = of_iomap(node, 2); -+ if (!pll->status_base) -+ goto err_status_iomap; -+ } else -+ pll->status_base = pll->control_base; -+ - /* initialize and register the PLL itself */ - pll->ctrl = pll_ctrl; - -@@ -699,6 +711,10 @@ err_clk_register: - clk_unregister(pll->clk_data.clks[i]); - - err_pll_register: -+ if (pll->status_base != pll->control_base) -+ iounmap(pll->status_base); -+ -+err_status_iomap: - if (pll->asiu_base) - iounmap(pll->asiu_base); - -@@ -706,7 +722,7 @@ err_asiu_iomap: - if (pll->pwr_base) - iounmap(pll->pwr_base); - -- iounmap(pll->pll_base); -+ iounmap(pll->control_base); - - err_pll_iomap: - kfree(pll->clks); ---- a/drivers/clk/bcm/clk-iproc.h -+++ b/drivers/clk/bcm/clk-iproc.h -@@ -55,6 +55,12 @@ - #define IPROC_CLK_EMBED_PWRCTRL BIT(5) - - /* -+ * Some PLLs have separate registers for Status and Control. Identify this to -+ * let the driver know if additional registers need to be used -+ */ -+#define IPROC_CLK_PLL_SPLIT_STAT_CTRL BIT(6) -+ -+/* - * Parameters for VCO frequency configuration - * - * VCO frequency = diff --git a/target/linux/bcm53xx/patches-4.3/050-ARM-dts-enable-clock-support-for-BCM5301X.patch b/target/linux/bcm53xx/patches-4.3/050-ARM-dts-enable-clock-support-for-BCM5301X.patch deleted file mode 100644 index a9a5246c0c..0000000000 --- a/target/linux/bcm53xx/patches-4.3/050-ARM-dts-enable-clock-support-for-BCM5301X.patch +++ /dev/null @@ -1,153 +0,0 @@ -From e96ef422d0095fe9ae39b03c0805a0db8ff7e382 Mon Sep 17 00:00:00 2001 -From: Jon Mason <jonmason@broadcom.com> -Date: Tue, 13 Oct 2015 17:22:25 -0400 -Subject: [PATCH 50/50] ARM: dts: enable clock support for BCM5301X - -Replace current device tree dummy clocks with real clock support for -Broadcom Northstar SoCs. - -Signed-off-by: Jon Mason <jonmason@broadcom.com> ---- - arch/arm/boot/dts/bcm5301x.dtsi | 88 ++++++++++++++++++++++++++++++++--------- - 1 file changed, 69 insertions(+), 19 deletions(-) - ---- a/arch/arm/boot/dts/bcm5301x.dtsi -+++ b/arch/arm/boot/dts/bcm5301x.dtsi -@@ -8,6 +8,7 @@ - * Licensed under the GNU/GPL. See COPYING for details. - */ - -+#include <dt-bindings/clock/bcm-nsp.h> - #include <dt-bindings/gpio/gpio.h> - #include <dt-bindings/input/input.h> - #include <dt-bindings/interrupt-controller/irq.h> -@@ -42,41 +43,48 @@ - - mpcore { - compatible = "simple-bus"; -- ranges = <0x00000000 0x19020000 0x00003000>; -+ ranges = <0x00000000 0x19000000 0x00023000>; - #address-cells = <1>; - #size-cells = <1>; - -- scu@0000 { -+ a9pll: arm_clk@00000 { -+ #clock-cells = <0>; -+ compatible = "brcm,nsp-armpll"; -+ clocks = <&osc>; -+ reg = <0x00000 0x1000>; -+ }; -+ -+ scu@20000 { - compatible = "arm,cortex-a9-scu"; -- reg = <0x0000 0x100>; -+ reg = <0x20000 0x100>; - }; - -- timer@0200 { -+ timer@20200 { - compatible = "arm,cortex-a9-global-timer"; -- reg = <0x0200 0x100>; -+ reg = <0x20200 0x100>; - interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&clk_periph>; -+ clocks = <&periph_clk>; - }; - -- local-timer@0600 { -+ local-timer@20600 { - compatible = "arm,cortex-a9-twd-timer"; -- reg = <0x0600 0x100>; -+ reg = <0x20600 0x100>; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&clk_periph>; -+ clocks = <&periph_clk>; - }; - -- gic: interrupt-controller@1000 { -+ gic: interrupt-controller@21000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; -- reg = <0x1000 0x1000>, -- <0x0100 0x100>; -+ reg = <0x21000 0x1000>, -+ <0x20100 0x100>; - }; - -- L2: cache-controller@2000 { -+ L2: cache-controller@22000 { - compatible = "arm,pl310-cache"; -- reg = <0x2000 0x1000>; -+ reg = <0x22000 0x1000>; - cache-unified; - arm,shared-override; - prefetch-data = <1>; -@@ -94,14 +102,37 @@ - - clocks { - #address-cells = <1>; -- #size-cells = <0>; -+ #size-cells = <1>; -+ ranges; - -- /* As long as we do not have a real clock driver us this -- * fixed clock */ -- clk_periph: periph { -+ osc: oscillator { -+ #clock-cells = <0>; - compatible = "fixed-clock"; -+ clock-frequency = <25000000>; -+ }; -+ -+ iprocmed: iprocmed { - #clock-cells = <0>; -- clock-frequency = <400000000>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; -+ clock-div = <2>; -+ clock-mult = <1>; -+ }; -+ -+ iprocslow: iprocslow { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; -+ clock-div = <4>; -+ clock-mult = <1>; -+ }; -+ -+ periph_clk: periph_clk { -+ #clock-cells = <0>; -+ compatible = "fixed-factor-clock"; -+ clocks = <&a9pll>; -+ clock-div = <2>; -+ clock-mult = <1>; - }; - }; - -@@ -189,4 +220,23 @@ - - brcm,nand-has-wp; - }; -+ -+ lcpll0: lcpll0@1800c100 { -+ #clock-cells = <1>; -+ compatible = "brcm,nsp-lcpll0"; -+ reg = <0x1800c100 0x14>; -+ clocks = <&osc>; -+ clock-output-names = "lcpll0", "pcie_phy", "sdio", -+ "ddr_phy"; -+ }; -+ -+ genpll: genpll@1800c140 { -+ #clock-cells = <1>; -+ compatible = "brcm,nsp-genpll"; -+ reg = <0x1800c140 0x24>; -+ clocks = <&osc>; -+ clock-output-names = "genpll", "phy", "ethernetclk", -+ "usbclk", "iprocfast", "sata1", -+ "sata2"; -+ }; - }; diff --git a/target/linux/bcm53xx/patches-4.3/067-ARM-BCM5301X-add-NAND-flash-chip-description-for-Asu.patch b/target/linux/bcm53xx/patches-4.3/067-ARM-BCM5301X-add-NAND-flash-chip-description-for-Asu.patch deleted file mode 100644 index ccb8e2769f..0000000000 --- a/target/linux/bcm53xx/patches-4.3/067-ARM-BCM5301X-add-NAND-flash-chip-description-for-Asu.patch +++ /dev/null @@ -1,32 +0,0 @@ -From af8fe7176ec13de08b1bfb7ea2ae9cc147b2429a Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens <hauke@hauke-m.de> -Date: Sat, 12 Sep 2015 12:56:37 +0200 -Subject: [PATCH] ARM: BCM5301X: add NAND flash chip description for Asus - RT-AC87U - -The NAND flash chip description were not imported for the Asus RT-AC87U -dts file when this was done for all the other dts files, because these -patches were send in parallel. - -This adds a missing NAND flash chip description to this patch: -commit 9faa5960eef3204cae6637b530f5e23e53b5a9ef -Author: Hauke Mehrtens <hauke@hauke-m.de> -Date: Fri May 29 23:39:47 2015 +0200 - -ARM: BCM5301X: add NAND flash chip description - -Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> ---- - arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts -+++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts -@@ -10,6 +10,7 @@ - /dts-v1/; - - #include "bcm4708.dtsi" -+#include "bcm5301x-nand-cs0-bch8.dtsi" - - / { - compatible = "asus,rt-ac87u", "brcm,bcm4709", "brcm,bcm4708"; diff --git a/target/linux/bcm53xx/patches-4.3/082-ARM-BCM5301X-Add-DT-for-Netgear-R7000.patch b/target/linux/bcm53xx/patches-4.3/082-ARM-BCM5301X-Add-DT-for-Netgear-R7000.patch deleted file mode 100644 index 044fb80607..0000000000 --- a/target/linux/bcm53xx/patches-4.3/082-ARM-BCM5301X-Add-DT-for-Netgear-R7000.patch +++ /dev/null @@ -1,128 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> -Date: Wed, 26 Aug 2015 16:11:38 +0200 -Subject: [PATCH] ARM: BCM5301X: Add DT for Netgear R7000 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Rafał Miłecki <zajec5@gmail.com> ---- ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -72,6 +72,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ - bcm47081-buffalo-wzr-900dhp.dtb \ - bcm4709-asus-rt-ac87u.dtb \ - bcm4709-buffalo-wxr-1900dhp.dtb \ -+ bcm4709-netgear-r7000.dtb \ - bcm4709-netgear-r8000.dtb - dtb-$(CONFIG_ARCH_BCM_63XX) += \ - bcm963138dvt.dtb ---- /dev/null -+++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts -@@ -0,0 +1,106 @@ -+/* -+ * Broadcom BCM470X / BCM5301X ARM platform code. -+ * DTS for Netgear R7000 -+ * -+ * Copyright (C) 2015 Rafał Miłecki <zajec5@gmail.com> -+ * -+ * Licensed under the GNU/GPL. See COPYING for details. -+ */ -+ -+/dts-v1/; -+ -+#include "bcm4708.dtsi" -+#include "bcm5301x-nand-cs0-bch8.dtsi" -+ -+/ { -+ compatible = "netgear,r7000", "brcm,bcm4709", "brcm,bcm4708"; -+ model = "Netgear R7000"; -+ -+ chosen { -+ bootargs = "console=ttyS0,115200"; -+ }; -+ -+ memory { -+ reg = <0x00000000 0x08000000>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ power-white { -+ label = "bcm53xx:white:power"; -+ gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; -+ linux,default-trigger = "default-on"; -+ }; -+ -+ power-amber { -+ label = "bcm53xx:amber:power"; -+ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; -+ linux,default-trigger = "default-off"; -+ }; -+ -+ 5ghz { -+ label = "bcm53xx:white:5ghz"; -+ gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; -+ linux,default-trigger = "default-off"; -+ }; -+ -+ 2ghz { -+ label = "bcm53xx:white:2ghz"; -+ gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; -+ linux,default-trigger = "default-off"; -+ }; -+ -+ wps { -+ label = "bcm53xx:white:wps"; -+ gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "default-off"; -+ }; -+ -+ wireless { -+ label = "bcm53xx:white:wireless"; -+ gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "default-off"; -+ }; -+ -+ usb3 { -+ label = "bcm53xx:white:usb3"; -+ gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; -+ linux,default-trigger = "default-off"; -+ }; -+ -+ usb2 { -+ label = "bcm53xx:white:usb2"; -+ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; -+ linux,default-trigger = "default-off"; -+ }; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ wps { -+ label = "WPS"; -+ linux,code = <KEY_WPS_BUTTON>; -+ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; -+ }; -+ -+ rfkill { -+ label = "WiFi"; -+ linux,code = <KEY_RFKILL>; -+ gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; -+ }; -+ -+ restart { -+ label = "Reset"; -+ linux,code = <KEY_RESTART>; -+ gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; diff --git a/target/linux/bcm53xx/patches-4.3/083-ARM-dts-bcm5301x-Add-BCM-SVK-DT-files.patch b/target/linux/bcm53xx/patches-4.3/083-ARM-dts-bcm5301x-Add-BCM-SVK-DT-files.patch deleted file mode 100644 index 0dae7c9144..0000000000 --- a/target/linux/bcm53xx/patches-4.3/083-ARM-dts-bcm5301x-Add-BCM-SVK-DT-files.patch +++ /dev/null @@ -1,218 +0,0 @@ -From a0aef7fbab0d8b5a0d445c74990e5233beda246e Mon Sep 17 00:00:00 2001 -From: Jon Mason <jonmason@broadcom.com> -Date: Wed, 21 Oct 2015 18:46:04 -0400 -Subject: [PATCH] ARM: dts: bcm5301x: Add BCM SVK DT files - -Add device tree files for Broadcom Northstar based SVKs. Since the -bcm5301x.dtsi already exists, all that is necessary is the dts files to -enable the UARTs. With these files, the SVKs are able to boot to shell. - -Signed-off-by: Jon Mason <jonmason@broadcom.com> ---- - arch/arm/boot/dts/Makefile | 5 +++- - arch/arm/boot/dts/bcm94708.dts | 56 +++++++++++++++++++++++++++++++++++ - arch/arm/boot/dts/bcm94709.dts | 56 +++++++++++++++++++++++++++++++++++ - arch/arm/boot/dts/bcm953012k.dts | 63 ++++++++++++++++++++++++++++++++++++++++ - 4 files changed, 179 insertions(+), 1 deletion(-) - create mode 100644 arch/arm/boot/dts/bcm94708.dts - create mode 100644 arch/arm/boot/dts/bcm94709.dts - create mode 100644 arch/arm/boot/dts/bcm953012k.dts - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -73,7 +73,10 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ - bcm4709-asus-rt-ac87u.dtb \ - bcm4709-buffalo-wxr-1900dhp.dtb \ - bcm4709-netgear-r7000.dtb \ -- bcm4709-netgear-r8000.dtb -+ bcm4709-netgear-r8000.dtb \ -+ bcm94708.dtb \ -+ bcm94709.dtb \ -+ bcm953012k.dtb - dtb-$(CONFIG_ARCH_BCM_63XX) += \ - bcm963138dvt.dtb - dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ ---- /dev/null -+++ b/arch/arm/boot/dts/bcm94708.dts -@@ -0,0 +1,56 @@ -+/* -+ * BSD LICENSE -+ * -+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Broadcom Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/dts-v1/; -+ -+#include "bcm4708.dtsi" -+ -+/ { -+ model = "NorthStar SVK (BCM94708)"; -+ compatible = "brcm,bcm94708", "brcm,bcm4708"; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ memory { -+ reg = <0x00000000 0x08000000>; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/bcm94709.dts -@@ -0,0 +1,56 @@ -+/* -+ * BSD LICENSE -+ * -+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Broadcom Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/dts-v1/; -+ -+#include "bcm4708.dtsi" -+ -+/ { -+ model = "NorthStar SVK (BCM94709)"; -+ compatible = "brcm,bcm94709", "brcm,bcm4709", "brcm,bcm4708"; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ memory { -+ reg = <0x00000000 0x08000000>; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/bcm953012k.dts -@@ -0,0 +1,63 @@ -+/* -+ * BSD LICENSE -+ * -+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Broadcom Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/dts-v1/; -+ -+#include "bcm4708.dtsi" -+ -+/ { -+ model = "NorthStar SVK (BCM953012K)"; -+ compatible = "brcm,bcm953012k", "brcm,brcm53012", "brcm,bcm4708"; -+ -+ aliases { -+ serial0 = &uart0; -+ serial1 = &uart1; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ memory { -+ reg = <0x00000000 0x10000000>; -+ }; -+}; -+ -+&uart0 { -+ clock-frequency = <62499840>; -+ status = "okay"; -+}; -+ -+&uart1 { -+ clock-frequency = <62499840>; -+ status = "okay"; -+}; diff --git a/target/linux/bcm53xx/patches-4.3/101-use-part-parser.patch b/target/linux/bcm53xx/patches-4.3/101-use-part-parser.patch deleted file mode 100644 index 8d48673c6d..0000000000 --- a/target/linux/bcm53xx/patches-4.3/101-use-part-parser.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi -+++ b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi -@@ -19,6 +19,8 @@ - - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; -+ -+ linux,part-probe = "ofpart", "bcm47xxpart"; - }; - }; - }; diff --git a/target/linux/bcm53xx/patches-4.3/130-dt-bindings-add-SMP-enable-method-for-Broadcom-NSP.patch b/target/linux/bcm53xx/patches-4.3/130-dt-bindings-add-SMP-enable-method-for-Broadcom-NSP.patch deleted file mode 100644 index 1de37b0132..0000000000 --- a/target/linux/bcm53xx/patches-4.3/130-dt-bindings-add-SMP-enable-method-for-Broadcom-NSP.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 204b9dbd7c4bd5a223fd104b9cba56c12fe04add Mon Sep 17 00:00:00 2001 -From: Kapil Hali <kapilh@broadcom.com> -Date: Wed, 19 Aug 2015 13:42:23 -0400 -Subject: [PATCH 130/134] dt-bindings: add SMP enable-method for Broadcom NSP - -Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's -Northstar Plus CPU to the 32-bit ARM CPU device tree binding -documentation file and create a new binding documentation for -Northstar Plus CPU. - -Signed-off-by: Kapil Hali <kapilh@broadcom.com> ---- - .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 39 ++++++++++++++++++++++ - Documentation/devicetree/bindings/arm/cpus.txt | 1 + - 2 files changed, 40 insertions(+) - create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt - ---- /dev/null -+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt -@@ -0,0 +1,39 @@ -+Broadcom Northstar Plus SoC CPU Enable Method -+--------------------------------------------- -+This binding defines the enable method used for starting secondary -+CPUs in the following Broadcom SoCs: -+ BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 -+ -+The enable method is specified by defining the following required -+properties in the "cpus" device tree node: -+ - enable-method = "brcm,bcm-nsp-smp"; -+ - secondary-boot-reg = <...>; -+ -+The secondary-boot-reg property is a u32 value that specifies the -+physical address of the register which should hold the common -+entry point for a secondary CPU. This entry is cpu node specific -+and should be added per cpu. E.g., in case of NSP (BCM58625) which -+is a dual core CPU SoC, this entry should be added to cpu1 node. -+ -+ -+Example: -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ enable-method = "brcm,bcm-nsp-smp"; -+ -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a9"; -+ next-level-cache = <&L2>; -+ reg = <0>; -+ }; -+ -+ cpu1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a9"; -+ next-level-cache = <&L2>; -+ reg = <1>; -+ secondary-boot-reg = <0xffff042c>; -+ }; -+ }; ---- a/Documentation/devicetree/bindings/arm/cpus.txt -+++ b/Documentation/devicetree/bindings/arm/cpus.txt -@@ -190,6 +190,7 @@ nodes to be present and contain the prop - "allwinner,sun6i-a31" - "allwinner,sun8i-a23" - "arm,psci" -+ "brcm,bcm-nsp-smp" - "brcm,brahma-b15" - "marvell,armada-375-smp" - "marvell,armada-380-smp" diff --git a/target/linux/bcm53xx/patches-4.3/131-ARM-BCM-Clean-up-SMP-support-for-Broadcom-Kona.patch b/target/linux/bcm53xx/patches-4.3/131-ARM-BCM-Clean-up-SMP-support-for-Broadcom-Kona.patch deleted file mode 100644 index 7a48a13e64..0000000000 --- a/target/linux/bcm53xx/patches-4.3/131-ARM-BCM-Clean-up-SMP-support-for-Broadcom-Kona.patch +++ /dev/null @@ -1,206 +0,0 @@ -From 8622d6da5d95293d474c156612fd819fdaf542ec Mon Sep 17 00:00:00 2001 -From: Kapil Hali <kapilh@broadcom.com> -Date: Wed, 25 Nov 2015 08:58:53 -0500 -Subject: [PATCH 131/134] ARM: BCM: Clean up SMP support for Broadcom Kona - -These changes cleans up SMP implementaion for Broadcom's -Kona SoC which are required for handling SMP for iProc -family of SoCs at a single place for BCM NSP and BCM Kona. - -Signed-off-by: Kapil Hali <kapilh@broadcom.com> ---- - arch/arm/boot/dts/bcm11351.dtsi | 2 +- - arch/arm/boot/dts/bcm21664.dtsi | 2 +- - arch/arm/mach-bcm/kona_smp.c | 82 +++++++++++++++++++++++++++-------------- - 3 files changed, 56 insertions(+), 30 deletions(-) - ---- a/arch/arm/boot/dts/bcm11351.dtsi -+++ b/arch/arm/boot/dts/bcm11351.dtsi -@@ -31,7 +31,6 @@ - #address-cells = <1>; - #size-cells = <0>; - enable-method = "brcm,bcm11351-cpu-method"; -- secondary-boot-reg = <0x3500417c>; - - cpu0: cpu@0 { - device_type = "cpu"; -@@ -42,6 +41,7 @@ - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; -+ secondary-boot-reg = <0x3500417c>; - reg = <1>; - }; - }; ---- a/arch/arm/boot/dts/bcm21664.dtsi -+++ b/arch/arm/boot/dts/bcm21664.dtsi -@@ -31,7 +31,6 @@ - #address-cells = <1>; - #size-cells = <0>; - enable-method = "brcm,bcm11351-cpu-method"; -- secondary-boot-reg = <0x35004178>; - - cpu0: cpu@0 { - device_type = "cpu"; -@@ -42,6 +41,7 @@ - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; -+ secondary-boot-reg = <0x35004178>; - reg = <1>; - }; - }; ---- a/arch/arm/mach-bcm/kona_smp.c -+++ b/arch/arm/mach-bcm/kona_smp.c -@@ -1,5 +1,5 @@ - /* -- * Copyright (C) 2014 Broadcom Corporation -+ * Copyright (C) 2014-2015 Broadcom Corporation - * Copyright 2014 Linaro Limited - * - * This program is free software; you can redistribute it and/or -@@ -30,9 +30,10 @@ - - /* Name of device node property defining secondary boot register location */ - #define OF_SECONDARY_BOOT "secondary-boot-reg" -+#define MPIDR_CPUID_BITMASK 0x3 - - /* I/O address of register used to coordinate secondary core startup */ --static u32 secondary_boot; -+static u32 secondary_boot_addr; - - /* - * Enable the Cortex A9 Snoop Control Unit -@@ -78,44 +79,68 @@ static int __init scu_a9_enable(void) - static void __init bcm_smp_prepare_cpus(unsigned int max_cpus) - { - static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 }; -- struct device_node *node; -+ struct device_node *cpus_node = NULL; -+ struct device_node *cpu_node = NULL; - int ret; - -- BUG_ON(secondary_boot); /* We're called only once */ -- - /* - * This function is only called via smp_ops->smp_prepare_cpu(). - * That only happens if a "/cpus" device tree node exists - * and has an "enable-method" property that selects the SMP - * operations defined herein. - */ -- node = of_find_node_by_path("/cpus"); -- BUG_ON(!node); -- -- /* -- * Our secondary enable method requires a "secondary-boot-reg" -- * property to specify a register address used to request the -- * ROM code boot a secondary code. If we have any trouble -- * getting this we fall back to uniprocessor mode. -- */ -- if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) { -- pr_err("%s: missing/invalid " OF_SECONDARY_BOOT " property\n", -- node->name); -- ret = -ENOENT; /* Arrange to disable SMP */ -- goto out; -+ cpus_node = of_find_node_by_path("/cpus"); -+ if (!cpus_node) -+ return; -+ -+ for_each_child_of_node(cpus_node, cpu_node) { -+ u32 cpuid; -+ -+ if (of_node_cmp(cpu_node->type, "cpu")) -+ continue; -+ -+ if (of_property_read_u32(cpu_node, "reg", &cpuid)) { -+ pr_debug("%s: missing reg property\n", -+ cpu_node->full_name); -+ ret = -ENOENT; -+ goto out; -+ } -+ -+ /* -+ * "secondary-boot-reg" property should be defined only -+ * for secondary cpu -+ */ -+ if ((cpuid & MPIDR_CPUID_BITMASK) == 1) { -+ /* -+ * Our secondary enable method requires a -+ * "secondary-boot-reg" property to specify a register -+ * address used to request the ROM code boot a secondary -+ * core. If we have any trouble getting this we fall -+ * back to uniprocessor mode. -+ */ -+ if (of_property_read_u32(cpu_node, -+ OF_SECONDARY_BOOT, -+ &secondary_boot_addr)) { -+ pr_warn("%s: no" OF_SECONDARY_BOOT "property\n", -+ cpu_node->name); -+ ret = -ENOENT; -+ goto out; -+ } -+ } - } - - /* -- * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is -+ * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is - * returned, the SoC reported a uniprocessor configuration. - * We bail on any other error. - */ - ret = scu_a9_enable(); - out: -- of_node_put(node); -+ of_node_put(cpu_node); -+ of_node_put(cpus_node); -+ - if (ret) { - /* Update the CPU present map to reflect uniprocessor mode */ -- BUG_ON(ret != -ENOENT); - pr_warn("disabling SMP\n"); - init_cpu_present(&only_cpu_0); - } -@@ -139,7 +164,7 @@ out: - * - Wait for the secondary boot register to be re-written, which - * indicates the secondary core has started. - */ --static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle) -+static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle) - { - void __iomem *boot_reg; - phys_addr_t boot_func; -@@ -154,15 +179,16 @@ static int bcm_boot_secondary(unsigned i - return -EINVAL; - } - -- if (!secondary_boot) { -+ if (!secondary_boot_addr) { - pr_err("required secondary boot register not specified\n"); - return -EINVAL; - } - -- boot_reg = ioremap_nocache((phys_addr_t)secondary_boot, sizeof(u32)); -+ boot_reg = ioremap_nocache( -+ (phys_addr_t)secondary_boot_addr, sizeof(u32)); - if (!boot_reg) { - pr_err("unable to map boot register for cpu %u\n", cpu_id); -- return -ENOSYS; -+ return -ENOMEM; - } - - /* -@@ -191,12 +217,12 @@ static int bcm_boot_secondary(unsigned i - - pr_err("timeout waiting for cpu %u to start\n", cpu_id); - -- return -ENOSYS; -+ return -ENXIO; - } - - static struct smp_operations bcm_smp_ops __initdata = { - .smp_prepare_cpus = bcm_smp_prepare_cpus, -- .smp_boot_secondary = bcm_boot_secondary, -+ .smp_boot_secondary = kona_boot_secondary, - }; - CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method", - &bcm_smp_ops); diff --git a/target/linux/bcm53xx/patches-4.3/133-ARM-BCM-Add-SMP-support-for-Broadcom-NSP.patch b/target/linux/bcm53xx/patches-4.3/133-ARM-BCM-Add-SMP-support-for-Broadcom-NSP.patch deleted file mode 100644 index 14a1da1eb5..0000000000 --- a/target/linux/bcm53xx/patches-4.3/133-ARM-BCM-Add-SMP-support-for-Broadcom-NSP.patch +++ /dev/null @@ -1,560 +0,0 @@ -From e99fb6d01cddf38cffc11655aba4a96a981d604e Mon Sep 17 00:00:00 2001 -From: Kapil Hali <kapilh@broadcom.com> -Date: Wed, 25 Nov 2015 13:25:55 -0500 -Subject: [PATCH 133/134] ARM: BCM: Add SMP support for Broadcom NSP - -Add SMP support for Broadcom's Northstar Plus SoC -cpu enable method. This changes also consolidates -iProc family's - BCM NSP and BCM Kona, platform -SMP handling in a common file. - -Northstar Plus SoC is based on ARM Cortex-A9 -revision r3p0 which requires configuration for ARM -Errata 764369 for SMP. This change adds the needed -configuration option. - -Signed-off-by: Kapil Hali <kapilh@broadcom.com> ---- - arch/arm/mach-bcm/Kconfig | 2 + - arch/arm/mach-bcm/Makefile | 8 +- - arch/arm/mach-bcm/kona_smp.c | 228 ---------------------------------- - arch/arm/mach-bcm/platsmp.c | 290 +++++++++++++++++++++++++++++++++++++++++++ - 4 files changed, 298 insertions(+), 230 deletions(-) - delete mode 100644 arch/arm/mach-bcm/kona_smp.c - create mode 100644 arch/arm/mach-bcm/platsmp.c - ---- a/arch/arm/mach-bcm/Makefile -+++ b/arch/arm/mach-bcm/Makefile -@@ -20,7 +20,7 @@ obj-$(CONFIG_ARCH_BCM_281XX) += board_bc - obj-$(CONFIG_ARCH_BCM_21664) += board_bcm21664.o - - # BCM281XX and BCM21664 SMP support --obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += kona_smp.o -+obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += platsmp.o - - # BCM281XX and BCM21664 L2 cache control - obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o ---- a/arch/arm/mach-bcm/kona_smp.c -+++ /dev/null -@@ -1,228 +0,0 @@ --/* -- * Copyright (C) 2014-2015 Broadcom Corporation -- * Copyright 2014 Linaro Limited -- * -- * This program is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation version 2. -- * -- * This program is distributed "as is" WITHOUT ANY WARRANTY of any -- * kind, whether express or implied; without even the implied warranty -- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- */ -- --#include <linux/init.h> --#include <linux/errno.h> --#include <linux/io.h> --#include <linux/of.h> --#include <linux/sched.h> -- --#include <asm/smp.h> --#include <asm/smp_plat.h> --#include <asm/smp_scu.h> -- --/* Size of mapped Cortex A9 SCU address space */ --#define CORTEX_A9_SCU_SIZE 0x58 -- --#define SECONDARY_TIMEOUT_NS NSEC_PER_MSEC /* 1 msec (in nanoseconds) */ --#define BOOT_ADDR_CPUID_MASK 0x3 -- --/* Name of device node property defining secondary boot register location */ --#define OF_SECONDARY_BOOT "secondary-boot-reg" --#define MPIDR_CPUID_BITMASK 0x3 -- --/* I/O address of register used to coordinate secondary core startup */ --static u32 secondary_boot_addr; -- --/* -- * Enable the Cortex A9 Snoop Control Unit -- * -- * By the time this is called we already know there are multiple -- * cores present. We assume we're running on a Cortex A9 processor, -- * so any trouble getting the base address register or getting the -- * SCU base is a problem. -- * -- * Return 0 if successful or an error code otherwise. -- */ --static int __init scu_a9_enable(void) --{ -- unsigned long config_base; -- void __iomem *scu_base; -- -- if (!scu_a9_has_base()) { -- pr_err("no configuration base address register!\n"); -- return -ENXIO; -- } -- -- /* Config base address register value is zero for uniprocessor */ -- config_base = scu_a9_get_base(); -- if (!config_base) { -- pr_err("hardware reports only one core\n"); -- return -ENOENT; -- } -- -- scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); -- if (!scu_base) { -- pr_err("failed to remap config base (%lu/%u) for SCU\n", -- config_base, CORTEX_A9_SCU_SIZE); -- return -ENOMEM; -- } -- -- scu_enable(scu_base); -- -- iounmap(scu_base); /* That's the last we'll need of this */ -- -- return 0; --} -- --static void __init bcm_smp_prepare_cpus(unsigned int max_cpus) --{ -- static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 }; -- struct device_node *cpus_node = NULL; -- struct device_node *cpu_node = NULL; -- int ret; -- -- /* -- * This function is only called via smp_ops->smp_prepare_cpu(). -- * That only happens if a "/cpus" device tree node exists -- * and has an "enable-method" property that selects the SMP -- * operations defined herein. -- */ -- cpus_node = of_find_node_by_path("/cpus"); -- if (!cpus_node) -- return; -- -- for_each_child_of_node(cpus_node, cpu_node) { -- u32 cpuid; -- -- if (of_node_cmp(cpu_node->type, "cpu")) -- continue; -- -- if (of_property_read_u32(cpu_node, "reg", &cpuid)) { -- pr_debug("%s: missing reg property\n", -- cpu_node->full_name); -- ret = -ENOENT; -- goto out; -- } -- -- /* -- * "secondary-boot-reg" property should be defined only -- * for secondary cpu -- */ -- if ((cpuid & MPIDR_CPUID_BITMASK) == 1) { -- /* -- * Our secondary enable method requires a -- * "secondary-boot-reg" property to specify a register -- * address used to request the ROM code boot a secondary -- * core. If we have any trouble getting this we fall -- * back to uniprocessor mode. -- */ -- if (of_property_read_u32(cpu_node, -- OF_SECONDARY_BOOT, -- &secondary_boot_addr)) { -- pr_warn("%s: no" OF_SECONDARY_BOOT "property\n", -- cpu_node->name); -- ret = -ENOENT; -- goto out; -- } -- } -- } -- -- /* -- * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is -- * returned, the SoC reported a uniprocessor configuration. -- * We bail on any other error. -- */ -- ret = scu_a9_enable(); --out: -- of_node_put(cpu_node); -- of_node_put(cpus_node); -- -- if (ret) { -- /* Update the CPU present map to reflect uniprocessor mode */ -- pr_warn("disabling SMP\n"); -- init_cpu_present(&only_cpu_0); -- } --} -- --/* -- * The ROM code has the secondary cores looping, waiting for an event. -- * When an event occurs each core examines the bottom two bits of the -- * secondary boot register. When a core finds those bits contain its -- * own core id, it performs initialization, including computing its boot -- * address by clearing the boot register value's bottom two bits. The -- * core signals that it is beginning its execution by writing its boot -- * address back to the secondary boot register, and finally jumps to -- * that address. -- * -- * So to start a core executing we need to: -- * - Encode the (hardware) CPU id with the bottom bits of the secondary -- * start address. -- * - Write that value into the secondary boot register. -- * - Generate an event to wake up the secondary CPU(s). -- * - Wait for the secondary boot register to be re-written, which -- * indicates the secondary core has started. -- */ --static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle) --{ -- void __iomem *boot_reg; -- phys_addr_t boot_func; -- u64 start_clock; -- u32 cpu_id; -- u32 boot_val; -- bool timeout = false; -- -- cpu_id = cpu_logical_map(cpu); -- if (cpu_id & ~BOOT_ADDR_CPUID_MASK) { -- pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK); -- return -EINVAL; -- } -- -- if (!secondary_boot_addr) { -- pr_err("required secondary boot register not specified\n"); -- return -EINVAL; -- } -- -- boot_reg = ioremap_nocache( -- (phys_addr_t)secondary_boot_addr, sizeof(u32)); -- if (!boot_reg) { -- pr_err("unable to map boot register for cpu %u\n", cpu_id); -- return -ENOMEM; -- } -- -- /* -- * Secondary cores will start in secondary_startup(), -- * defined in "arch/arm/kernel/head.S" -- */ -- boot_func = virt_to_phys(secondary_startup); -- BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK); -- BUG_ON(boot_func > (phys_addr_t)U32_MAX); -- -- /* The core to start is encoded in the low bits */ -- boot_val = (u32)boot_func | cpu_id; -- writel_relaxed(boot_val, boot_reg); -- -- sev(); -- -- /* The low bits will be cleared once the core has started */ -- start_clock = local_clock(); -- while (!timeout && readl_relaxed(boot_reg) == boot_val) -- timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS; -- -- iounmap(boot_reg); -- -- if (!timeout) -- return 0; -- -- pr_err("timeout waiting for cpu %u to start\n", cpu_id); -- -- return -ENXIO; --} -- --static struct smp_operations bcm_smp_ops __initdata = { -- .smp_prepare_cpus = bcm_smp_prepare_cpus, -- .smp_boot_secondary = kona_boot_secondary, --}; --CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method", -- &bcm_smp_ops); ---- /dev/null -+++ b/arch/arm/mach-bcm/platsmp.c -@@ -0,0 +1,290 @@ -+/* -+ * Copyright (C) 2014-2015 Broadcom Corporation -+ * Copyright 2014 Linaro Limited -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation version 2. -+ * -+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any -+ * kind, whether express or implied; without even the implied warranty -+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include <linux/cpumask.h> -+#include <linux/delay.h> -+#include <linux/errno.h> -+#include <linux/init.h> -+#include <linux/io.h> -+#include <linux/jiffies.h> -+#include <linux/of.h> -+#include <linux/sched.h> -+#include <linux/smp.h> -+ -+#include <asm/cacheflush.h> -+#include <asm/smp.h> -+#include <asm/smp_plat.h> -+#include <asm/smp_scu.h> -+ -+/* Size of mapped Cortex A9 SCU address space */ -+#define CORTEX_A9_SCU_SIZE 0x58 -+ -+#define SECONDARY_TIMEOUT_NS NSEC_PER_MSEC /* 1 msec (in nanoseconds) */ -+#define BOOT_ADDR_CPUID_MASK 0x3 -+ -+/* Name of device node property defining secondary boot register location */ -+#define OF_SECONDARY_BOOT "secondary-boot-reg" -+#define MPIDR_CPUID_BITMASK 0x3 -+ -+/* I/O address of register used to coordinate secondary core startup */ -+static u32 secondary_boot_addr; -+ -+/* -+ * Enable the Cortex A9 Snoop Control Unit -+ * -+ * By the time this is called we already know there are multiple -+ * cores present. We assume we're running on a Cortex A9 processor, -+ * so any trouble getting the base address register or getting the -+ * SCU base is a problem. -+ * -+ * Return 0 if successful or an error code otherwise. -+ */ -+static int __init scu_a9_enable(void) -+{ -+ unsigned long config_base; -+ void __iomem *scu_base; -+ -+ if (!scu_a9_has_base()) { -+ pr_err("no configuration base address register!\n"); -+ return -ENXIO; -+ } -+ -+ /* Config base address register value is zero for uniprocessor */ -+ config_base = scu_a9_get_base(); -+ if (!config_base) { -+ pr_err("hardware reports only one core\n"); -+ return -ENOENT; -+ } -+ -+ scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); -+ if (!scu_base) { -+ pr_err("failed to remap config base (%lu/%u) for SCU\n", -+ config_base, CORTEX_A9_SCU_SIZE); -+ return -ENOMEM; -+ } -+ -+ scu_enable(scu_base); -+ -+ iounmap(scu_base); /* That's the last we'll need of this */ -+ -+ return 0; -+} -+ -+static int nsp_write_lut(void) -+{ -+ void __iomem *sku_rom_lut; -+ phys_addr_t secondary_startup_phy; -+ -+ if (!secondary_boot_addr) { -+ pr_warn("required secondary boot register not specified\n"); -+ return -EINVAL; -+ } -+ -+ sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot_addr, -+ sizeof(secondary_boot_addr)); -+ if (!sku_rom_lut) { -+ pr_warn("unable to ioremap SKU-ROM LUT register\n"); -+ return -ENOMEM; -+ } -+ -+ secondary_startup_phy = virt_to_phys(secondary_startup); -+ BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX); -+ -+ writel_relaxed(secondary_startup_phy, sku_rom_lut); -+ -+ /* Ensure the write is visible to the secondary core */ -+ smp_wmb(); -+ -+ iounmap(sku_rom_lut); -+ -+ return 0; -+} -+ -+static void __init bcm_smp_prepare_cpus(unsigned int max_cpus) -+{ -+ static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 }; -+ struct device_node *cpus_node = NULL; -+ struct device_node *cpu_node = NULL; -+ int ret; -+ -+ /* -+ * This function is only called via smp_ops->smp_prepare_cpu(). -+ * That only happens if a "/cpus" device tree node exists -+ * and has an "enable-method" property that selects the SMP -+ * operations defined herein. -+ */ -+ cpus_node = of_find_node_by_path("/cpus"); -+ if (!cpus_node) -+ return; -+ -+ for_each_child_of_node(cpus_node, cpu_node) { -+ u32 cpuid; -+ -+ if (of_node_cmp(cpu_node->type, "cpu")) -+ continue; -+ -+ if (of_property_read_u32(cpu_node, "reg", &cpuid)) { -+ pr_debug("%s: missing reg property\n", -+ cpu_node->full_name); -+ ret = -ENOENT; -+ goto out; -+ } -+ -+ /* -+ * "secondary-boot-reg" property should be defined only -+ * for secondary cpu -+ */ -+ if ((cpuid & MPIDR_CPUID_BITMASK) == 1) { -+ /* -+ * Our secondary enable method requires a -+ * "secondary-boot-reg" property to specify a register -+ * address used to request the ROM code boot a secondary -+ * core. If we have any trouble getting this we fall -+ * back to uniprocessor mode. -+ */ -+ if (of_property_read_u32(cpu_node, -+ OF_SECONDARY_BOOT, -+ &secondary_boot_addr)) { -+ pr_warn("%s: no" OF_SECONDARY_BOOT "property\n", -+ cpu_node->name); -+ ret = -ENOENT; -+ goto out; -+ } -+ } -+ } -+ -+ /* -+ * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is -+ * returned, the SoC reported a uniprocessor configuration. -+ * We bail on any other error. -+ */ -+ ret = scu_a9_enable(); -+out: -+ of_node_put(cpu_node); -+ of_node_put(cpus_node); -+ -+ if (ret) { -+ /* Update the CPU present map to reflect uniprocessor mode */ -+ pr_warn("disabling SMP\n"); -+ init_cpu_present(&only_cpu_0); -+ } -+} -+ -+/* -+ * The ROM code has the secondary cores looping, waiting for an event. -+ * When an event occurs each core examines the bottom two bits of the -+ * secondary boot register. When a core finds those bits contain its -+ * own core id, it performs initialization, including computing its boot -+ * address by clearing the boot register value's bottom two bits. The -+ * core signals that it is beginning its execution by writing its boot -+ * address back to the secondary boot register, and finally jumps to -+ * that address. -+ * -+ * So to start a core executing we need to: -+ * - Encode the (hardware) CPU id with the bottom bits of the secondary -+ * start address. -+ * - Write that value into the secondary boot register. -+ * - Generate an event to wake up the secondary CPU(s). -+ * - Wait for the secondary boot register to be re-written, which -+ * indicates the secondary core has started. -+ */ -+static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle) -+{ -+ void __iomem *boot_reg; -+ phys_addr_t boot_func; -+ u64 start_clock; -+ u32 cpu_id; -+ u32 boot_val; -+ bool timeout = false; -+ -+ cpu_id = cpu_logical_map(cpu); -+ if (cpu_id & ~BOOT_ADDR_CPUID_MASK) { -+ pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK); -+ return -EINVAL; -+ } -+ -+ if (!secondary_boot_addr) { -+ pr_err("required secondary boot register not specified\n"); -+ return -EINVAL; -+ } -+ -+ boot_reg = ioremap_nocache( -+ (phys_addr_t)secondary_boot_addr, sizeof(u32)); -+ if (!boot_reg) { -+ pr_err("unable to map boot register for cpu %u\n", cpu_id); -+ return -ENOMEM; -+ } -+ -+ /* -+ * Secondary cores will start in secondary_startup(), -+ * defined in "arch/arm/kernel/head.S" -+ */ -+ boot_func = virt_to_phys(secondary_startup); -+ BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK); -+ BUG_ON(boot_func > (phys_addr_t)U32_MAX); -+ -+ /* The core to start is encoded in the low bits */ -+ boot_val = (u32)boot_func | cpu_id; -+ writel_relaxed(boot_val, boot_reg); -+ -+ sev(); -+ -+ /* The low bits will be cleared once the core has started */ -+ start_clock = local_clock(); -+ while (!timeout && readl_relaxed(boot_reg) == boot_val) -+ timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS; -+ -+ iounmap(boot_reg); -+ -+ if (!timeout) -+ return 0; -+ -+ pr_err("timeout waiting for cpu %u to start\n", cpu_id); -+ -+ return -ENXIO; -+} -+ -+static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle) -+{ -+ int ret; -+ -+ /* -+ * After wake up, secondary core branches to the startup -+ * address programmed at SKU ROM LUT location. -+ */ -+ ret = nsp_write_lut(); -+ if (ret) { -+ pr_err("unable to write startup addr to SKU ROM LUT\n"); -+ goto out; -+ } -+ -+ /* Send a CPU wakeup interrupt to the secondary core */ -+ arch_send_wakeup_ipi_mask(cpumask_of(cpu)); -+ -+out: -+ return ret; -+} -+ -+static struct smp_operations bcm_smp_ops __initdata = { -+ .smp_prepare_cpus = bcm_smp_prepare_cpus, -+ .smp_boot_secondary = kona_boot_secondary, -+}; -+CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method", -+ &bcm_smp_ops); -+ -+struct smp_operations nsp_smp_ops __initdata = { -+ .smp_prepare_cpus = bcm_smp_prepare_cpus, -+ .smp_boot_secondary = nsp_boot_secondary, -+}; -+CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops); diff --git a/target/linux/bcm53xx/patches-4.3/134-ARM-BCM-Add-SMP-support-for-Broadcom-4708.patch b/target/linux/bcm53xx/patches-4.3/134-ARM-BCM-Add-SMP-support-for-Broadcom-4708.patch deleted file mode 100644 index 9260190a34..0000000000 --- a/target/linux/bcm53xx/patches-4.3/134-ARM-BCM-Add-SMP-support-for-Broadcom-4708.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 16e1bf7dde22ee22a331aabf824cc31a6794a4cb Mon Sep 17 00:00:00 2001 -From: Jon Mason <jonmason@broadcom.com> -Date: Thu, 15 Oct 2015 14:09:10 -0400 -Subject: [PATCH 134/134] ARM: BCM: Add SMP support for Broadcom 4708 - -Add SMP support for Broadcom's 4708 SoCs. - -Signed-off-by: Jon Mason <jonmason@broadcom.com> -Acked-by: Hauke Mehrtens <hauke@hauke-m.de> -Tested-by: Hauke Mehrtens <hauke@hauke-m.de> -Signed-off-by: Kapil Hali <kapilh@broadcom.com> ---- - arch/arm/boot/dts/bcm4708.dtsi | 2 ++ - arch/arm/mach-bcm/Kconfig | 1 + - arch/arm/mach-bcm/Makefile | 3 +++ - 3 files changed, 6 insertions(+) - ---- a/arch/arm/boot/dts/bcm4708.dtsi -+++ b/arch/arm/boot/dts/bcm4708.dtsi -@@ -15,6 +15,7 @@ - cpus { - #address-cells = <1>; - #size-cells = <0>; -+ enable-method = "brcm,bcm-nsp-smp"; - - cpu@0 { - device_type = "cpu"; -@@ -27,6 +28,7 @@ - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; -+ secondary-boot-reg = <0xffff0400>; - reg = <0x1>; - }; - }; ---- a/arch/arm/mach-bcm/Kconfig -+++ b/arch/arm/mach-bcm/Kconfig -@@ -41,6 +41,7 @@ config ARCH_BCM_5301X - select ARM_ERRATA_754322 - select ARM_ERRATA_775420 - select ARM_ERRATA_764369 if SMP -+ select HAVE_SMP - - help - Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores. ---- a/arch/arm/mach-bcm/Makefile -+++ b/arch/arm/mach-bcm/Makefile -@@ -36,6 +36,9 @@ obj-$(CONFIG_ARCH_BCM2835) += board_bcm2 - - # BCM5301X - obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o -+ifeq ($(CONFIG_ARCH_BCM_5301X),y) -+obj-$(CONFIG_SMP) += platsmp.o -+endif - - # BCM63XXx - ifeq ($(CONFIG_ARCH_BCM_63XX),y) diff --git a/target/linux/bcm53xx/patches-4.3/140-PCI-iproc-Fix-code-comment-to-match-code.patch b/target/linux/bcm53xx/patches-4.3/140-PCI-iproc-Fix-code-comment-to-match-code.patch deleted file mode 100644 index c018105159..0000000000 --- a/target/linux/bcm53xx/patches-4.3/140-PCI-iproc-Fix-code-comment-to-match-code.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 5d92f41c48c5e3c6fa5be87e3d6fca57e2fbb127 Mon Sep 17 00:00:00 2001 -From: Ray Jui <rjui@broadcom.com> -Date: Tue, 15 Sep 2015 17:39:15 -0700 -Subject: [PATCH 140/147] PCI: iproc: Fix code comment to match code - -Fix code comment in pcie-iproc.h so it matches the code. - -Signed-off-by: Ray Jui <rjui@broadcom.com> -Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> ---- - drivers/pci/host/pcie-iproc.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/pci/host/pcie-iproc.h -+++ b/drivers/pci/host/pcie-iproc.h -@@ -20,11 +20,11 @@ - * iProc PCIe device - * @dev: pointer to device data structure - * @base: PCIe host controller I/O register base -- * @resources: linked list of all PCI resources - * @sysdata: Per PCI controller data (ARM-specific) - * @root_bus: pointer to root bus - * @phy: optional PHY device that controls the Serdes - * @irqs: interrupt IDs -+ * @map_irq: function callback to map interrupts - */ - struct iproc_pcie { - struct device *dev; diff --git a/target/linux/bcm53xx/patches-4.3/141-PCI-iproc-Remove-unused-struct-iproc_pcie.irqs.patch b/target/linux/bcm53xx/patches-4.3/141-PCI-iproc-Remove-unused-struct-iproc_pcie.irqs.patch deleted file mode 100644 index e16822fae7..0000000000 --- a/target/linux/bcm53xx/patches-4.3/141-PCI-iproc-Remove-unused-struct-iproc_pcie.irqs.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 98aac697a83db6e1d004e5d61cf6c976a0b1c35a Mon Sep 17 00:00:00 2001 -From: Ray Jui <rjui@broadcom.com> -Date: Tue, 15 Sep 2015 17:39:16 -0700 -Subject: [PATCH 141/147] PCI: iproc: Remove unused struct iproc_pcie.irqs[] - -Remove unused struct iproc_pcie member irqs[] and unused #define -IPROC_PCIE_MAX_NUM_IRQS. - -Signed-off-by: Ray Jui <rjui@broadcom.com> -Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> ---- - drivers/pci/host/pcie-iproc.h | 3 --- - 1 file changed, 3 deletions(-) - ---- a/drivers/pci/host/pcie-iproc.h -+++ b/drivers/pci/host/pcie-iproc.h -@@ -14,8 +14,6 @@ - #ifndef _PCIE_IPROC_H - #define _PCIE_IPROC_H - --#define IPROC_PCIE_MAX_NUM_IRQS 6 -- - /** - * iProc PCIe device - * @dev: pointer to device data structure -@@ -34,7 +32,6 @@ struct iproc_pcie { - #endif - struct pci_bus *root_bus; - struct phy *phy; -- int irqs[IPROC_PCIE_MAX_NUM_IRQS]; - int (*map_irq)(const struct pci_dev *, u8, u8); - }; - diff --git a/target/linux/bcm53xx/patches-4.3/142-PCI-iproc-Call-pci_fixup_irqs-for-ARM64-as-well-as-A.patch b/target/linux/bcm53xx/patches-4.3/142-PCI-iproc-Call-pci_fixup_irqs-for-ARM64-as-well-as-A.patch deleted file mode 100644 index 2e58d060ca..0000000000 --- a/target/linux/bcm53xx/patches-4.3/142-PCI-iproc-Call-pci_fixup_irqs-for-ARM64-as-well-as-A.patch +++ /dev/null @@ -1,31 +0,0 @@ -From bdb8a1844f3113ec08915d1e8e3fd5686fb2fb78 Mon Sep 17 00:00:00 2001 -From: Ray Jui <rjui@broadcom.com> -Date: Tue, 15 Sep 2015 17:39:17 -0700 -Subject: [PATCH 142/147] PCI: iproc: Call pci_fixup_irqs() for ARM64 as well - as ARM - -After 459a07721c11 ("PCI: Build setup-irq.o for arm64"), we build -setup-irq.o for arm64, so we can use pci_fixup_irqs() on both arm and -arm64. - -Remove the "#ifdef CONFIG_ARM" around the call to pci_fixup_irqs(). - -[bhelgaas: changelog] -Signed-off-by: Ray Jui <rjui@broadcom.com> -Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> ---- - drivers/pci/host/pcie-iproc.c | 2 -- - 1 file changed, 2 deletions(-) - ---- a/drivers/pci/host/pcie-iproc.c -+++ b/drivers/pci/host/pcie-iproc.c -@@ -238,9 +238,7 @@ int iproc_pcie_setup(struct iproc_pcie * - - pci_scan_child_bus(bus); - pci_assign_unassigned_bus_resources(bus); --#ifdef CONFIG_ARM - pci_fixup_irqs(pci_common_swizzle, pcie->map_irq); --#endif - pci_bus_add_devices(bus); - - return 0; diff --git a/target/linux/bcm53xx/patches-4.3/143-PCI-iproc-Fix-PCIe-reset-logic.patch b/target/linux/bcm53xx/patches-4.3/143-PCI-iproc-Fix-PCIe-reset-logic.patch deleted file mode 100644 index b9020a5ac8..0000000000 --- a/target/linux/bcm53xx/patches-4.3/143-PCI-iproc-Fix-PCIe-reset-logic.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 199ff14100095d52cd1b232cc0f3b12f348b5b07 Mon Sep 17 00:00:00 2001 -From: Ray Jui <rjui@broadcom.com> -Date: Tue, 15 Sep 2015 17:39:18 -0700 -Subject: [PATCH 143/147] PCI: iproc: Fix PCIe reset logic - -The current reset logic does not always properly reset the device. For -example, in the case when the perst_b signal is already de-asserted in the -bootloader, the current reset logic fails to trigger a proper assert -> -de-assert reset sequence. - -Fix the issue by always triggering the proper reset sequence. - -Also explicitly select the desired reset source, i.e., perst_b, and reduce -the wait time after the device comes out of reset from 250 ms to 100 ms, -based on recommendation from the ASIC team. - -Tested-by: Vladimir Dreizin <vdreizin@broadcom.com> -Tested-by: Darren Edamura <dedamura@broadcom.com> -Signed-off-by: Ray Jui <rjui@broadcom.com> -Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> -Reviewed-by: Vladimir Dreizin <vdreizin@broadcom.com> -Reviewed-by: Trac Hoang <trhoang@broadcom.com> -Reviewed-by: Scott Branden <sbranden@broadcom.com> ---- - drivers/pci/host/pcie-iproc.c | 15 ++++++++++----- - 1 file changed, 10 insertions(+), 5 deletions(-) - ---- a/drivers/pci/host/pcie-iproc.c -+++ b/drivers/pci/host/pcie-iproc.c -@@ -31,6 +31,8 @@ - #include "pcie-iproc.h" - - #define CLK_CONTROL_OFFSET 0x000 -+#define EP_PERST_SOURCE_SELECT_SHIFT 2 -+#define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT) - #define EP_MODE_SURVIVE_PERST_SHIFT 1 - #define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT) - #define RC_PCIE_RST_OUTPUT_SHIFT 0 -@@ -119,15 +121,18 @@ static void iproc_pcie_reset(struct ipro - u32 val; - - /* -- * Configure the PCIe controller as root complex and send a downstream -- * reset -+ * Select perst_b signal as reset source. Put the device into reset, -+ * and then bring it out of reset - */ -- val = EP_MODE_SURVIVE_PERST | RC_PCIE_RST_OUTPUT; -+ val = readl(pcie->base + CLK_CONTROL_OFFSET); -+ val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST & -+ ~RC_PCIE_RST_OUTPUT; - writel(val, pcie->base + CLK_CONTROL_OFFSET); - udelay(250); -- val &= ~EP_MODE_SURVIVE_PERST; -+ -+ val |= RC_PCIE_RST_OUTPUT; - writel(val, pcie->base + CLK_CONTROL_OFFSET); -- msleep(250); -+ msleep(100); - } - - static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus *bus) diff --git a/target/linux/bcm53xx/patches-4.3/144-PCI-iproc-Improve-link-detection-logic.patch b/target/linux/bcm53xx/patches-4.3/144-PCI-iproc-Improve-link-detection-logic.patch deleted file mode 100644 index 3fecba2b26..0000000000 --- a/target/linux/bcm53xx/patches-4.3/144-PCI-iproc-Improve-link-detection-logic.patch +++ /dev/null @@ -1,84 +0,0 @@ -From aaf22ab4e916afa68a2e1aed4e913b76cbd58276 Mon Sep 17 00:00:00 2001 -From: Ray Jui <rjui@broadcom.com> -Date: Tue, 15 Sep 2015 17:39:19 -0700 -Subject: [PATCH 144/147] PCI: iproc: Improve link detection logic - -Improve the link detection logic by explicitly querying the link status -register to ensure link is active. - -Also force class to PCI_CLASS_BRIDGE_PCI (0x0604) through the host -configuration space register. - -Signed-off-by: Ray Jui <rjui@broadcom.com> -Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> -Reviewed-by: Anup Patel <anup.patel@broadcom.com> -Reviewed-by: Scott Branden <sbranden@broadcom.com> ---- - drivers/pci/host/pcie-iproc.c | 29 +++++++++++++++++++++++------ - 1 file changed, 23 insertions(+), 6 deletions(-) - ---- a/drivers/pci/host/pcie-iproc.c -+++ b/drivers/pci/host/pcie-iproc.c -@@ -60,6 +60,12 @@ - #define SYS_RC_INTX_EN 0x330 - #define SYS_RC_INTX_MASK 0xf - -+#define PCIE_LINK_STATUS_OFFSET 0xf0c -+#define PCIE_PHYLINKUP_SHIFT 3 -+#define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT) -+#define PCIE_DL_ACTIVE_SHIFT 2 -+#define PCIE_DL_ACTIVE BIT(PCIE_DL_ACTIVE_SHIFT) -+ - static inline struct iproc_pcie *iproc_data(struct pci_bus *bus) - { - struct iproc_pcie *pcie; -@@ -138,9 +144,15 @@ static void iproc_pcie_reset(struct ipro - static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus *bus) - { - u8 hdr_type; -- u32 link_ctrl; -+ u32 link_ctrl, class, val; - u16 pos, link_status; -- int link_is_active = 0; -+ bool link_is_active = false; -+ -+ val = readl(pcie->base + PCIE_LINK_STATUS_OFFSET); -+ if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) { -+ dev_err(pcie->dev, "PHY or data link is INACTIVE!\n"); -+ return -ENODEV; -+ } - - /* make sure we are not in EP mode */ - pci_bus_read_config_byte(bus, 0, PCI_HEADER_TYPE, &hdr_type); -@@ -150,14 +162,19 @@ static int iproc_pcie_check_link(struct - } - - /* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */ -- pci_bus_write_config_word(bus, 0, PCI_CLASS_DEVICE, -- PCI_CLASS_BRIDGE_PCI); -+#define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c -+#define PCI_CLASS_BRIDGE_MASK 0xffff00 -+#define PCI_CLASS_BRIDGE_SHIFT 8 -+ pci_bus_read_config_dword(bus, 0, PCI_BRIDGE_CTRL_REG_OFFSET, &class); -+ class &= ~PCI_CLASS_BRIDGE_MASK; -+ class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT); -+ pci_bus_write_config_dword(bus, 0, PCI_BRIDGE_CTRL_REG_OFFSET, class); - - /* check link status to see if link is active */ - pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP); - pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA, &link_status); - if (link_status & PCI_EXP_LNKSTA_NLW) -- link_is_active = 1; -+ link_is_active = true; - - if (!link_is_active) { - /* try GEN 1 link speed */ -@@ -181,7 +198,7 @@ static int iproc_pcie_check_link(struct - pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA, - &link_status); - if (link_status & PCI_EXP_LNKSTA_NLW) -- link_is_active = 1; -+ link_is_active = true; - } - } - diff --git a/target/linux/bcm53xx/patches-4.3/145-PCI-iproc-Update-PCIe-device-tree-bindings.patch b/target/linux/bcm53xx/patches-4.3/145-PCI-iproc-Update-PCIe-device-tree-bindings.patch deleted file mode 100644 index eb5bb64bba..0000000000 --- a/target/linux/bcm53xx/patches-4.3/145-PCI-iproc-Update-PCIe-device-tree-bindings.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 8d0afa1a93be2da954c85392bbc7b2264c9d241c Mon Sep 17 00:00:00 2001 -From: Ray Jui <rjui@broadcom.com> -Date: Tue, 15 Sep 2015 17:39:20 -0700 -Subject: [PATCH 145/147] PCI: iproc: Update PCIe device tree bindings - -Update the device tree bindings with added support for outbound mapping -configurations. - -Signed-off-by: Ray Jui <rjui@broadcom.com> -Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> ---- - .../devicetree/bindings/pci/brcm,iproc-pcie.txt | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - ---- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt -+++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt -@@ -17,6 +17,21 @@ Optional properties: - - phys: phandle of the PCIe PHY device - - phy-names: must be "pcie-phy" - -+- brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done -+by the ASIC after power on reset. In this case, SW needs to configure it -+ -+If the brcm,pcie-ob property is present, the following properties become -+effective: -+ -+Required: -+- brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal -+address used by the iProc PCIe core (not the PCIe address) -+- brcm,pcie-ob-window-size: The outbound address mapping window size (in MB) -+ -+Optional: -+- brcm,pcie-ob-oarr-size: Some iProc SoCs need the OARR size bit to be set to -+increase the outbound window size -+ - Example: - pcie0: pcie@18012000 { - compatible = "brcm,iproc-pcie"; -@@ -38,6 +53,11 @@ Example: - - phys = <&phy 0 5>; - phy-names = "pcie-phy"; -+ -+ brcm,pcie-ob; -+ brcm,pcie-ob-oarr-size; -+ brcm,pcie-ob-axi-offset = <0x00000000>; -+ brcm,pcie-ob-window-size = <256>; - }; - - pcie1: pcie@18013000 { diff --git a/target/linux/bcm53xx/patches-4.3/146-PCI-iproc-Add-outbound-mapping-support.patch b/target/linux/bcm53xx/patches-4.3/146-PCI-iproc-Add-outbound-mapping-support.patch deleted file mode 100644 index b65d3057bc..0000000000 --- a/target/linux/bcm53xx/patches-4.3/146-PCI-iproc-Add-outbound-mapping-support.patch +++ /dev/null @@ -1,236 +0,0 @@ -From e99a187b5c5f60fe55ca586f82ac1a3557fb166a Mon Sep 17 00:00:00 2001 -From: Ray Jui <rjui@broadcom.com> -Date: Fri, 16 Oct 2015 08:18:24 -0500 -Subject: [PATCH 146/147] PCI: iproc: Add outbound mapping support - -Certain SoCs require the PCIe outbound mapping to be configured in -software. Add support for those chips. - -[jonmason: Use %pap format when printing size_t to avoid warnings in 32-bit -build.] -[arnd: Use div64_u64() instead of "%" to avoid __aeabi_uldivmod link error -in 32-bit build.] -Signed-off-by: Ray Jui <rjui@broadcom.com> -Signed-off-by: Jon Mason <jonmason@broadcom.com> -Signed-off-by: Arnd Bergmann <arnd@arndb.de> -Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> ---- - drivers/pci/host/pcie-iproc-platform.c | 27 ++++++++ - drivers/pci/host/pcie-iproc.c | 115 +++++++++++++++++++++++++++++++++ - drivers/pci/host/pcie-iproc.h | 17 +++++ - 3 files changed, 159 insertions(+) - ---- a/drivers/pci/host/pcie-iproc-platform.c -+++ b/drivers/pci/host/pcie-iproc-platform.c -@@ -54,6 +54,33 @@ static int iproc_pcie_pltfm_probe(struct - return -ENOMEM; - } - -+ if (of_property_read_bool(np, "brcm,pcie-ob")) { -+ u32 val; -+ -+ ret = of_property_read_u32(np, "brcm,pcie-ob-axi-offset", -+ &val); -+ if (ret) { -+ dev_err(pcie->dev, -+ "missing brcm,pcie-ob-axi-offset property\n"); -+ return ret; -+ } -+ pcie->ob.axi_offset = val; -+ -+ ret = of_property_read_u32(np, "brcm,pcie-ob-window-size", -+ &val); -+ if (ret) { -+ dev_err(pcie->dev, -+ "missing brcm,pcie-ob-window-size property\n"); -+ return ret; -+ } -+ pcie->ob.window_size = (resource_size_t)val * SZ_1M; -+ -+ if (of_property_read_bool(np, "brcm,pcie-ob-oarr-size")) -+ pcie->ob.set_oarr_size = true; -+ -+ pcie->need_ob_cfg = true; -+ } -+ - /* PHY use is optional */ - pcie->phy = devm_phy_get(&pdev->dev, "pcie-phy"); - if (IS_ERR(pcie->phy)) { ---- a/drivers/pci/host/pcie-iproc.c -+++ b/drivers/pci/host/pcie-iproc.c -@@ -66,6 +66,18 @@ - #define PCIE_DL_ACTIVE_SHIFT 2 - #define PCIE_DL_ACTIVE BIT(PCIE_DL_ACTIVE_SHIFT) - -+#define OARR_VALID_SHIFT 0 -+#define OARR_VALID BIT(OARR_VALID_SHIFT) -+#define OARR_SIZE_CFG_SHIFT 1 -+#define OARR_SIZE_CFG BIT(OARR_SIZE_CFG_SHIFT) -+ -+#define OARR_LO(window) (0xd20 + (window) * 8) -+#define OARR_HI(window) (0xd24 + (window) * 8) -+#define OMAP_LO(window) (0xd40 + (window) * 8) -+#define OMAP_HI(window) (0xd44 + (window) * 8) -+ -+#define MAX_NUM_OB_WINDOWS 2 -+ - static inline struct iproc_pcie *iproc_data(struct pci_bus *bus) - { - struct iproc_pcie *pcie; -@@ -212,6 +224,101 @@ static void iproc_pcie_enable(struct ipr - writel(SYS_RC_INTX_MASK, pcie->base + SYS_RC_INTX_EN); - } - -+/** -+ * Some iProc SoCs require the SW to configure the outbound address mapping -+ * -+ * Outbound address translation: -+ * -+ * iproc_pcie_address = axi_address - axi_offset -+ * OARR = iproc_pcie_address -+ * OMAP = pci_addr -+ * -+ * axi_addr -> iproc_pcie_address -> OARR -> OMAP -> pci_address -+ */ -+static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr, -+ u64 pci_addr, resource_size_t size) -+{ -+ struct iproc_pcie_ob *ob = &pcie->ob; -+ unsigned i; -+ u64 max_size = (u64)ob->window_size * MAX_NUM_OB_WINDOWS; -+ u64 remainder; -+ -+ if (size > max_size) { -+ dev_err(pcie->dev, -+ "res size 0x%pap exceeds max supported size 0x%llx\n", -+ &size, max_size); -+ return -EINVAL; -+ } -+ -+ div64_u64_rem(size, ob->window_size, &remainder); -+ if (remainder) { -+ dev_err(pcie->dev, -+ "res size %pap needs to be multiple of window size %pap\n", -+ &size, &ob->window_size); -+ return -EINVAL; -+ } -+ -+ if (axi_addr < ob->axi_offset) { -+ dev_err(pcie->dev, -+ "axi address %pap less than offset %pap\n", -+ &axi_addr, &ob->axi_offset); -+ return -EINVAL; -+ } -+ -+ /* -+ * Translate the AXI address to the internal address used by the iProc -+ * PCIe core before programming the OARR -+ */ -+ axi_addr -= ob->axi_offset; -+ -+ for (i = 0; i < MAX_NUM_OB_WINDOWS; i++) { -+ writel(lower_32_bits(axi_addr) | OARR_VALID | -+ (ob->set_oarr_size ? 1 : 0), pcie->base + OARR_LO(i)); -+ writel(upper_32_bits(axi_addr), pcie->base + OARR_HI(i)); -+ writel(lower_32_bits(pci_addr), pcie->base + OMAP_LO(i)); -+ writel(upper_32_bits(pci_addr), pcie->base + OMAP_HI(i)); -+ -+ size -= ob->window_size; -+ if (size == 0) -+ break; -+ -+ axi_addr += ob->window_size; -+ pci_addr += ob->window_size; -+ } -+ -+ return 0; -+} -+ -+static int iproc_pcie_map_ranges(struct iproc_pcie *pcie, -+ struct list_head *resources) -+{ -+ struct resource_entry *window; -+ int ret; -+ -+ resource_list_for_each_entry(window, resources) { -+ struct resource *res = window->res; -+ u64 res_type = resource_type(res); -+ -+ switch (res_type) { -+ case IORESOURCE_IO: -+ case IORESOURCE_BUS: -+ break; -+ case IORESOURCE_MEM: -+ ret = iproc_pcie_setup_ob(pcie, res->start, -+ res->start - window->offset, -+ resource_size(res)); -+ if (ret) -+ return ret; -+ break; -+ default: -+ dev_err(pcie->dev, "invalid resource %pR\n", res); -+ return -EINVAL; -+ } -+ } -+ -+ return 0; -+} -+ - int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res) - { - int ret; -@@ -235,6 +342,14 @@ int iproc_pcie_setup(struct iproc_pcie * - - iproc_pcie_reset(pcie); - -+ if (pcie->need_ob_cfg) { -+ ret = iproc_pcie_map_ranges(pcie, res); -+ if (ret) { -+ dev_err(pcie->dev, "map failed\n"); -+ goto err_power_off_phy; -+ } -+ } -+ - #ifdef CONFIG_ARM - pcie->sysdata.private_data = pcie; - sysdata = &pcie->sysdata; ---- a/drivers/pci/host/pcie-iproc.h -+++ b/drivers/pci/host/pcie-iproc.h -@@ -15,6 +15,19 @@ - #define _PCIE_IPROC_H - - /** -+ * iProc PCIe outbound mapping -+ * @set_oarr_size: indicates the OARR size bit needs to be set -+ * @axi_offset: offset from the AXI address to the internal address used by -+ * the iProc PCIe core -+ * @window_size: outbound window size -+ */ -+struct iproc_pcie_ob { -+ bool set_oarr_size; -+ resource_size_t axi_offset; -+ resource_size_t window_size; -+}; -+ -+/** - * iProc PCIe device - * @dev: pointer to device data structure - * @base: PCIe host controller I/O register base -@@ -23,6 +36,8 @@ - * @phy: optional PHY device that controls the Serdes - * @irqs: interrupt IDs - * @map_irq: function callback to map interrupts -+ * @need_ob_cfg: indidates SW needs to configure the outbound mapping window -+ * @ob: outbound mapping parameters - */ - struct iproc_pcie { - struct device *dev; -@@ -33,6 +48,8 @@ struct iproc_pcie { - struct pci_bus *root_bus; - struct phy *phy; - int (*map_irq)(const struct pci_dev *, u8, u8); -+ bool need_ob_cfg; -+ struct iproc_pcie_ob ob; - }; - - int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res); diff --git a/target/linux/bcm53xx/patches-4.3/147-PCI-iproc-Fix-header-comment-Corporation-misspelling.patch b/target/linux/bcm53xx/patches-4.3/147-PCI-iproc-Fix-header-comment-Corporation-misspelling.patch deleted file mode 100644 index 9ad5f00c04..0000000000 --- a/target/linux/bcm53xx/patches-4.3/147-PCI-iproc-Fix-header-comment-Corporation-misspelling.patch +++ /dev/null @@ -1,25 +0,0 @@ -From be908d21b2e9c2cab1ef568dfca4f9777611b3dd Mon Sep 17 00:00:00 2001 -From: Florian Fainelli <f.fainelli@gmail.com> -Date: Fri, 16 Oct 2015 12:04:04 -0700 -Subject: [PATCH 147/147] PCI: iproc: Fix header comment "Corporation" - misspelling - -Fix an obvious "Broadcom Corporation" typo in a header comment. - -Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> -Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> -Acked-by: Ray Jui <rjui@broadcom.com> ---- - drivers/pci/host/pcie-iproc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/pci/host/pcie-iproc.c -+++ b/drivers/pci/host/pcie-iproc.c -@@ -1,6 +1,6 @@ - /* - * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de> -- * Copyright (C) 2015 Broadcom Corporatcommon ion -+ * Copyright (C) 2015 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as diff --git a/target/linux/bcm53xx/patches-4.3/150-PCI-iproc-Update-iProc-PCIe-device-tree-binding.patch b/target/linux/bcm53xx/patches-4.3/150-PCI-iproc-Update-iProc-PCIe-device-tree-binding.patch deleted file mode 100644 index 7d6949f234..0000000000 --- a/target/linux/bcm53xx/patches-4.3/150-PCI-iproc-Update-iProc-PCIe-device-tree-binding.patch +++ /dev/null @@ -1,29 +0,0 @@ -From d85a955118c8d8679d4f746fe2189c172d7c365f Mon Sep 17 00:00:00 2001 -From: Ray Jui <rjui@broadcom.com> -Date: Mon, 16 Nov 2015 17:18:05 -0800 -Subject: [PATCH 150/154] PCI: iproc: Update iProc PCIe device tree binding - -Add a new compatible string "brcm,iproc-pcie-paxc", for PAXC based iProc -PCIe root complex. A PAXC based PCIe root complex is connected to -emulated endpoint devices internal to the ASIC - -Signed-off-by: Ray Jui <rjui@broadcom.com> -Reviewed-by: Scott Branden <sbranden@broadcom.com> ---- - Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - ---- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt -+++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt -@@ -1,7 +1,10 @@ - * Broadcom iProc PCIe controller with the platform bus interface - - Required properties: --- compatible: Must be "brcm,iproc-pcie" -+- compatible: Must be "brcm,iproc-pcie" for PAXB, or "brcm,iproc-pcie-paxc" -+ for PAXC. PAXB based root complex is used for external endpoint devices. -+ PAXC based root complex is connected to emulated endpoint devices -+ internal to the ASIC - - reg: base address and length of the PCIe controller I/O register space - - #interrupt-cells: set to <1> - - interrupt-map-mask and interrupt-map, standard PCI properties to define the diff --git a/target/linux/bcm53xx/patches-4.3/151-PCI-iproc-Add-PAXC-interface-support.patch b/target/linux/bcm53xx/patches-4.3/151-PCI-iproc-Add-PAXC-interface-support.patch deleted file mode 100644 index 9b7b762241..0000000000 --- a/target/linux/bcm53xx/patches-4.3/151-PCI-iproc-Add-PAXC-interface-support.patch +++ /dev/null @@ -1,428 +0,0 @@ -From a13fc4733b25d6dad6ec1826f09225c69ee21e3a Mon Sep 17 00:00:00 2001 -From: Ray Jui <rjui@broadcom.com> -Date: Mon, 16 Nov 2015 17:41:43 -0800 -Subject: [PATCH 151/154] PCI: iproc: Add PAXC interface support - -Traditionally, all iProc PCIe root complexes use PAXB based wrapper, -with an integrated on-chip Serdes to support external endpoint devices. -On newer iProc platforms, a PAXC based wrapper is introduced, for -connection with internally emulated PCIe endpoint devices in the ASIC - -This patch adds support for PAXC based iProc PCIe root complex in the -iProc PCIe core driver. This change fators out common logic between -PAXB and PAXC, and use tables to store register offsets that are -different between PAXB and PAXC. This allows the driver to be scaled to -support subsequent PAXC revisions in the future - -Signed-off-by: Ray Jui <rjui@broadcom.com> -Reviewed-by: Scott Branden <sbranden@broadcom.com> ---- - drivers/pci/host/pcie-iproc-platform.c | 24 +++- - drivers/pci/host/pcie-iproc.c | 202 +++++++++++++++++++++++++++------ - drivers/pci/host/pcie-iproc.h | 19 ++++ - 3 files changed, 205 insertions(+), 40 deletions(-) - ---- a/drivers/pci/host/pcie-iproc-platform.c -+++ b/drivers/pci/host/pcie-iproc-platform.c -@@ -26,8 +26,21 @@ - - #include "pcie-iproc.h" - -+static const struct of_device_id iproc_pcie_of_match_table[] = { -+ { -+ .compatible = "brcm,iproc-pcie", -+ .data = (int *)IPROC_PCIE_PAXB, -+ }, { -+ .compatible = "brcm,iproc-pcie-paxc", -+ .data = (int *)IPROC_PCIE_PAXC, -+ }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, iproc_pcie_of_match_table); -+ - static int iproc_pcie_pltfm_probe(struct platform_device *pdev) - { -+ const struct of_device_id *of_id; - struct iproc_pcie *pcie; - struct device_node *np = pdev->dev.of_node; - struct resource reg; -@@ -35,11 +48,16 @@ static int iproc_pcie_pltfm_probe(struct - LIST_HEAD(res); - int ret; - -+ of_id = of_match_device(iproc_pcie_of_match_table, &pdev->dev); -+ if (!of_id) -+ return -EINVAL; -+ - pcie = devm_kzalloc(&pdev->dev, sizeof(struct iproc_pcie), GFP_KERNEL); - if (!pcie) - return -ENOMEM; - - pcie->dev = &pdev->dev; -+ pcie->type = (enum iproc_pcie_type)of_id->data; - platform_set_drvdata(pdev, pcie); - - ret = of_address_to_resource(np, 0, ®); -@@ -114,12 +132,6 @@ static int iproc_pcie_pltfm_remove(struc - return iproc_pcie_remove(pcie); - } - --static const struct of_device_id iproc_pcie_of_match_table[] = { -- { .compatible = "brcm,iproc-pcie", }, -- { /* sentinel */ } --}; --MODULE_DEVICE_TABLE(of, iproc_pcie_of_match_table); -- - static struct platform_driver iproc_pcie_pltfm_driver = { - .driver = { - .name = "iproc-pcie", ---- a/drivers/pci/host/pcie-iproc.c -+++ b/drivers/pci/host/pcie-iproc.c -@@ -30,20 +30,16 @@ - - #include "pcie-iproc.h" - --#define CLK_CONTROL_OFFSET 0x000 - #define EP_PERST_SOURCE_SELECT_SHIFT 2 - #define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT) - #define EP_MODE_SURVIVE_PERST_SHIFT 1 - #define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT) - #define RC_PCIE_RST_OUTPUT_SHIFT 0 - #define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT) -+#define PAXC_RESET_MASK 0x7f - --#define CFG_IND_ADDR_OFFSET 0x120 - #define CFG_IND_ADDR_MASK 0x00001ffc - --#define CFG_IND_DATA_OFFSET 0x124 -- --#define CFG_ADDR_OFFSET 0x1f8 - #define CFG_ADDR_BUS_NUM_SHIFT 20 - #define CFG_ADDR_BUS_NUM_MASK 0x0ff00000 - #define CFG_ADDR_DEV_NUM_SHIFT 15 -@@ -55,12 +51,8 @@ - #define CFG_ADDR_CFG_TYPE_SHIFT 0 - #define CFG_ADDR_CFG_TYPE_MASK 0x00000003 - --#define CFG_DATA_OFFSET 0x1fc -- --#define SYS_RC_INTX_EN 0x330 - #define SYS_RC_INTX_MASK 0xf - --#define PCIE_LINK_STATUS_OFFSET 0xf0c - #define PCIE_PHYLINKUP_SHIFT 3 - #define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT) - #define PCIE_DL_ACTIVE_SHIFT 2 -@@ -71,12 +63,54 @@ - #define OARR_SIZE_CFG_SHIFT 1 - #define OARR_SIZE_CFG BIT(OARR_SIZE_CFG_SHIFT) - --#define OARR_LO(window) (0xd20 + (window) * 8) --#define OARR_HI(window) (0xd24 + (window) * 8) --#define OMAP_LO(window) (0xd40 + (window) * 8) --#define OMAP_HI(window) (0xd44 + (window) * 8) -- - #define MAX_NUM_OB_WINDOWS 2 -+#define MAX_NUM_PAXC_PF 4 -+ -+#define IPROC_PCIE_REG_INVALID 0xffff -+ -+enum iproc_pcie_reg { -+ IPROC_PCIE_CLK_CTRL = 0, -+ IPROC_PCIE_CFG_IND_ADDR, -+ IPROC_PCIE_CFG_IND_DATA, -+ IPROC_PCIE_CFG_ADDR, -+ IPROC_PCIE_CFG_DATA, -+ IPROC_PCIE_INTX_EN, -+ IPROC_PCIE_OARR_LO, -+ IPROC_PCIE_OARR_HI, -+ IPROC_PCIE_OMAP_LO, -+ IPROC_PCIE_OMAP_HI, -+ IPROC_PCIE_LINK_STATUS, -+}; -+ -+/* iProc PCIe PAXB registers */ -+static const u16 iproc_pcie_reg_paxb[] = { -+ [IPROC_PCIE_CLK_CTRL] = 0x000, -+ [IPROC_PCIE_CFG_IND_ADDR] = 0x120, -+ [IPROC_PCIE_CFG_IND_DATA] = 0x124, -+ [IPROC_PCIE_CFG_ADDR] = 0x1f8, -+ [IPROC_PCIE_CFG_DATA] = 0x1fc, -+ [IPROC_PCIE_INTX_EN] = 0x330, -+ [IPROC_PCIE_OARR_LO] = 0xd20, -+ [IPROC_PCIE_OARR_HI] = 0xd24, -+ [IPROC_PCIE_OMAP_LO] = 0xd40, -+ [IPROC_PCIE_OMAP_HI] = 0xd44, -+ [IPROC_PCIE_LINK_STATUS] = 0xf0c, -+}; -+ -+/* iProc PCIe PAXC v1 registers */ -+static const u16 iproc_pcie_reg_paxc[] = { -+ [IPROC_PCIE_CLK_CTRL] = 0x000, -+ [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0, -+ [IPROC_PCIE_CFG_IND_DATA] = 0x1f4, -+ [IPROC_PCIE_CFG_ADDR] = 0x1f8, -+ [IPROC_PCIE_CFG_DATA] = 0x1fc, -+ [IPROC_PCIE_INTX_EN] = IPROC_PCIE_REG_INVALID, -+ [IPROC_PCIE_OARR_LO] = IPROC_PCIE_REG_INVALID, -+ [IPROC_PCIE_OARR_HI] = IPROC_PCIE_REG_INVALID, -+ [IPROC_PCIE_OMAP_LO] = IPROC_PCIE_REG_INVALID, -+ [IPROC_PCIE_OMAP_HI] = IPROC_PCIE_REG_INVALID, -+ [IPROC_PCIE_LINK_STATUS] = IPROC_PCIE_REG_INVALID, -+}; - - static inline struct iproc_pcie *iproc_data(struct pci_bus *bus) - { -@@ -91,6 +125,65 @@ static inline struct iproc_pcie *iproc_d - return pcie; - } - -+static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset) -+{ -+ return !!(reg_offset == IPROC_PCIE_REG_INVALID); -+} -+ -+static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie, -+ enum iproc_pcie_reg reg) -+{ -+ return pcie->reg_offsets[reg]; -+} -+ -+static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie, -+ enum iproc_pcie_reg reg) -+{ -+ u16 offset = iproc_pcie_reg_offset(pcie, reg); -+ -+ if (iproc_pcie_reg_is_invalid(offset)) -+ return 0; -+ -+ return readl(pcie->base + offset); -+} -+ -+static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie, -+ enum iproc_pcie_reg reg, u32 val) -+{ -+ u16 offset = iproc_pcie_reg_offset(pcie, reg); -+ -+ if (iproc_pcie_reg_is_invalid(offset)) -+ return; -+ -+ writel(val, pcie->base + offset); -+} -+ -+static inline void iproc_pcie_ob_write(struct iproc_pcie *pcie, -+ enum iproc_pcie_reg reg, -+ unsigned window, u32 val) -+{ -+ u16 offset = iproc_pcie_reg_offset(pcie, reg); -+ -+ if (iproc_pcie_reg_is_invalid(offset)) -+ return; -+ -+ writel(val, pcie->base + offset + (window * 8)); -+} -+ -+static inline bool iproc_pcie_device_is_valid(struct iproc_pcie *pcie, -+ unsigned int slot, -+ unsigned int fn) -+{ -+ if (slot > 0) -+ return false; -+ -+ /* PAXC can only support limited number of functions */ -+ if (pcie->type == IPROC_PCIE_PAXC && fn >= MAX_NUM_PAXC_PF) -+ return false; -+ -+ return true; -+} -+ - /** - * Note access to the configuration registers are protected at the higher layer - * by 'pci_lock' in drivers/pci/access.c -@@ -104,28 +197,34 @@ static void __iomem *iproc_pcie_map_cfg_ - unsigned fn = PCI_FUNC(devfn); - unsigned busno = bus->number; - u32 val; -+ u16 offset; -+ -+ if (!iproc_pcie_device_is_valid(pcie, slot, fn)) -+ return NULL; - - /* root complex access */ - if (busno == 0) { -- if (slot >= 1) -+ iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR, -+ where & CFG_IND_ADDR_MASK); -+ offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA); -+ if (iproc_pcie_reg_is_invalid(offset)) - return NULL; -- writel(where & CFG_IND_ADDR_MASK, -- pcie->base + CFG_IND_ADDR_OFFSET); -- return (pcie->base + CFG_IND_DATA_OFFSET); -+ else -+ return (pcie->base + offset); - } - -- if (fn > 1) -- return NULL; -- - /* EP device access */ - val = (busno << CFG_ADDR_BUS_NUM_SHIFT) | - (slot << CFG_ADDR_DEV_NUM_SHIFT) | - (fn << CFG_ADDR_FUNC_NUM_SHIFT) | - (where & CFG_ADDR_REG_NUM_MASK) | - (1 & CFG_ADDR_CFG_TYPE_MASK); -- writel(val, pcie->base + CFG_ADDR_OFFSET); -- -- return (pcie->base + CFG_DATA_OFFSET); -+ iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val); -+ offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA); -+ if (iproc_pcie_reg_is_invalid(offset)) -+ return NULL; -+ else -+ return (pcie->base + offset); - } - - static struct pci_ops iproc_pcie_ops = { -@@ -138,18 +237,29 @@ static void iproc_pcie_reset(struct ipro - { - u32 val; - -+ if (pcie->type == IPROC_PCIE_PAXC) { -+ val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL); -+ val &= ~PAXC_RESET_MASK; -+ iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); -+ udelay(100); -+ val |= PAXC_RESET_MASK; -+ iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); -+ udelay(100); -+ return; -+ } -+ - /* - * Select perst_b signal as reset source. Put the device into reset, - * and then bring it out of reset - */ -- val = readl(pcie->base + CLK_CONTROL_OFFSET); -+ val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL); - val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST & - ~RC_PCIE_RST_OUTPUT; -- writel(val, pcie->base + CLK_CONTROL_OFFSET); -+ iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); - udelay(250); - - val |= RC_PCIE_RST_OUTPUT; -- writel(val, pcie->base + CLK_CONTROL_OFFSET); -+ iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); - msleep(100); - } - -@@ -160,7 +270,14 @@ static int iproc_pcie_check_link(struct - u16 pos, link_status; - bool link_is_active = false; - -- val = readl(pcie->base + PCIE_LINK_STATUS_OFFSET); -+ /* -+ * PAXC connects to emulated endpoint devices directly and does not -+ * have a Serdes. Therefore skip the link detection logic here -+ */ -+ if (pcie->type == IPROC_PCIE_PAXC) -+ return 0; -+ -+ val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS); - if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) { - dev_err(pcie->dev, "PHY or data link is INACTIVE!\n"); - return -ENODEV; -@@ -221,7 +338,7 @@ static int iproc_pcie_check_link(struct - - static void iproc_pcie_enable(struct iproc_pcie *pcie) - { -- writel(SYS_RC_INTX_MASK, pcie->base + SYS_RC_INTX_EN); -+ iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK); - } - - /** -@@ -272,11 +389,15 @@ static int iproc_pcie_setup_ob(struct ip - axi_addr -= ob->axi_offset; - - for (i = 0; i < MAX_NUM_OB_WINDOWS; i++) { -- writel(lower_32_bits(axi_addr) | OARR_VALID | -- (ob->set_oarr_size ? 1 : 0), pcie->base + OARR_LO(i)); -- writel(upper_32_bits(axi_addr), pcie->base + OARR_HI(i)); -- writel(lower_32_bits(pci_addr), pcie->base + OMAP_LO(i)); -- writel(upper_32_bits(pci_addr), pcie->base + OMAP_HI(i)); -+ iproc_pcie_ob_write(pcie, IPROC_PCIE_OARR_LO, i, -+ lower_32_bits(axi_addr) | OARR_VALID | -+ (ob->set_oarr_size ? 1 : 0)); -+ iproc_pcie_ob_write(pcie, IPROC_PCIE_OARR_HI, i, -+ upper_32_bits(axi_addr)); -+ iproc_pcie_ob_write(pcie, IPROC_PCIE_OMAP_LO, i, -+ lower_32_bits(pci_addr)); -+ iproc_pcie_ob_write(pcie, IPROC_PCIE_OMAP_HI, i, -+ upper_32_bits(pci_addr)); - - size -= ob->window_size; - if (size == 0) -@@ -340,6 +461,19 @@ int iproc_pcie_setup(struct iproc_pcie * - goto err_exit_phy; - } - -+ switch (pcie->type) { -+ case IPROC_PCIE_PAXB: -+ pcie->reg_offsets = iproc_pcie_reg_paxb; -+ break; -+ case IPROC_PCIE_PAXC: -+ pcie->reg_offsets = iproc_pcie_reg_paxc; -+ break; -+ default: -+ dev_err(pcie->dev, "incompatible iProc PCIe interface\n"); -+ ret = -EINVAL; -+ goto err_power_off_phy; -+ } -+ - iproc_pcie_reset(pcie); - - if (pcie->need_ob_cfg) { ---- a/drivers/pci/host/pcie-iproc.h -+++ b/drivers/pci/host/pcie-iproc.h -@@ -15,6 +15,20 @@ - #define _PCIE_IPROC_H - - /** -+ * iProc PCIe interface type -+ * -+ * PAXB is the wrapper used in root complex that can be connected to an -+ * external endpoint device -+ * -+ * PAXC is the wrapper used in root complex dedicated for internal emulated -+ * endpoint devices -+ */ -+enum iproc_pcie_type { -+ IPROC_PCIE_PAXB = 0, -+ IPROC_PCIE_PAXC, -+}; -+ -+/** - * iProc PCIe outbound mapping - * @set_oarr_size: indicates the OARR size bit needs to be set - * @axi_offset: offset from the AXI address to the internal address used by -@@ -29,7 +43,10 @@ struct iproc_pcie_ob { - - /** - * iProc PCIe device -+ * - * @dev: pointer to device data structure -+ * @type: iProc PCIe interface type -+ * @reg_offsets: register offsets - * @base: PCIe host controller I/O register base - * @sysdata: Per PCI controller data (ARM-specific) - * @root_bus: pointer to root bus -@@ -41,6 +58,8 @@ struct iproc_pcie_ob { - */ - struct iproc_pcie { - struct device *dev; -+ enum iproc_pcie_type type; -+ const u16 *reg_offsets; - void __iomem *base; - #ifdef CONFIG_ARM - struct pci_sys_data sysdata; diff --git a/target/linux/bcm53xx/patches-4.3/152-PCI-iproc-Add-iProc-PCIe-MSI-device-tree-binding.patch b/target/linux/bcm53xx/patches-4.3/152-PCI-iproc-Add-iProc-PCIe-MSI-device-tree-binding.patch deleted file mode 100644 index f0b0031237..0000000000 --- a/target/linux/bcm53xx/patches-4.3/152-PCI-iproc-Add-iProc-PCIe-MSI-device-tree-binding.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 96b40de5e36ec479dabb88500f1830a87818a809 Mon Sep 17 00:00:00 2001 -From: Ray Jui <rjui@broadcom.com> -Date: Mon, 16 Nov 2015 17:57:33 -0800 -Subject: [PATCH 152/154] PCI: iproc: Add iProc PCIe MSI device tree binding - -This patch updates the iProc PCIe device tree bindings with added -binding information for MSI - -Signed-off-by: Ray Jui <rjui@broadcom.com> -Reviewed-by: Anup Patel <anup.patel@broadcom.com> -Reviewed-by: Vikram Prakash <vikramp@broadcom.com> -Reviewed-by: Scott Branden <sbranden@broadcom.com> ---- - .../devicetree/bindings/pci/brcm,iproc-pcie.txt | 35 ++++++++++++++++++++++ - 1 file changed, 35 insertions(+) - ---- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt -+++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt -@@ -35,6 +35,28 @@ Optional: - - brcm,pcie-ob-oarr-size: Some iProc SoCs need the OARR size bit to be set to - increase the outbound window size - -+MSI support (optional): -+ -+For older platforms without MSI integrated in the GIC, iProc PCIe core provides -+an event queue based MSI support. The iProc MSI uses host memories to store -+MSI posted writes in the event queues -+ -+- msi-parent: Link to the device node of the MSI controller. On newer iProc -+platforms, the MSI controller may be gicv2m or gicv3-its. On older iProc -+platforms without MSI support in its interrupt controller, one may use the -+event queue based MSI support integrated within the iProc PCIe core -+ -+When the iProc event queue based MSI is used, one needs to define the -+following properties in the MSI device node: -+- compatible: Must be "brcm,iproc-msi" -+- msi-controller: claims itself as an MSI controller -+- interrupt-parent: Link to its parent interrupt device -+- interrupts: List of interrupt IDs from its parent interrupt device -+ -+Optional properties: -+- brcm,pcie-msi-inten: Needs to be present for some older iProc platforms that -+require the interrupt enable registers to be set explicitly to enable MSI -+ - Example: - pcie0: pcie@18012000 { - compatible = "brcm,iproc-pcie"; -@@ -61,6 +83,19 @@ Example: - brcm,pcie-ob-oarr-size; - brcm,pcie-ob-axi-offset = <0x00000000>; - brcm,pcie-ob-window-size = <256>; -+ -+ msi-parent = <&msi0>; -+ -+ /* iProc event queue based MSI */ -+ msi0: msi@18012000 { -+ compatible = "brcm,iproc-msi"; -+ msi-controller; -+ interrupt-parent = <&gic>; -+ interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>, -+ <GIC_SPI 97 IRQ_TYPE_NONE>, -+ <GIC_SPI 98 IRQ_TYPE_NONE>, -+ <GIC_SPI 99 IRQ_TYPE_NONE>, -+ }; - }; - - pcie1: pcie@18013000 { diff --git a/target/linux/bcm53xx/patches-4.3/153-PCI-iproc-Add-iProc-PCIe-MSI-support.patch b/target/linux/bcm53xx/patches-4.3/153-PCI-iproc-Add-iProc-PCIe-MSI-support.patch deleted file mode 100644 index ecf2804abd..0000000000 --- a/target/linux/bcm53xx/patches-4.3/153-PCI-iproc-Add-iProc-PCIe-MSI-support.patch +++ /dev/null @@ -1,886 +0,0 @@ -From c81922174d61127ff5baad6059ae148794c72276 Mon Sep 17 00:00:00 2001 -From: Ray Jui <rjui@broadcom.com> -Date: Tue, 17 Nov 2015 13:14:37 -0800 -Subject: [PATCH 153/154] PCI: iproc: Add iProc PCIe MSI support - -This patch adds PCIe MSI support for both PAXB and PAXC interfaces on -all iProc based platforms - -The iProc PCIe MSI support deploys an event queue based implementation. -Each event queue is serviced by a GIC interrupt and can support up to 64 -MSI vectors. Host memory is allocated for the event queues, and each event -queue consists of 64 word-sized entries. MSI data is written to the -lower 16-bit of each entry, whereas the upper 16-bit of the entry is -reserved for the controller for internal processing - -Each event queue is tracked by a head pointer and tail pointer. Head -pointer indicates the next entry in the event queue to be processed by -the driver and is updated by the driver after processing is done. -The controller uses the tail pointer as the next MSI data insertion -point. The controller ensures MSI data is flushed to host memory before -updating the tail pointer and then triggering the interrupt - -MSI IRQ affinity is supported by evenly distributing the interrupts to -each CPU core. MSI vector is moved from one GIC interrupt to another in -order to steer to the target CPU - -Therefore, the actual number of supported MSI vectors is: - -M * 64 / N - -where M denotes the number of GIC interrupts (event queues), and N -denotes the number of CPU cores - -This iProc event queue based MSI support should not be used with newer -platforms with integrated MSI support in the GIC (e.g., giv2m or -gicv3-its) - -Signed-off-by: Ray Jui <rjui@broadcom.com> -Reviewed-by: Anup Patel <anup.patel@broadcom.com> -Reviewed-by: Vikram Prakash <vikramp@broadcom.com> -Reviewed-by: Scott Branden <sbranden@broadcom.com> ---- - drivers/pci/host/Kconfig | 9 + - drivers/pci/host/Makefile | 1 + - drivers/pci/host/pcie-iproc-bcma.c | 1 + - drivers/pci/host/pcie-iproc-msi.c | 675 +++++++++++++++++++++++++++++++++ - drivers/pci/host/pcie-iproc-platform.c | 1 + - drivers/pci/host/pcie-iproc.c | 26 ++ - drivers/pci/host/pcie-iproc.h | 23 +- - 7 files changed, 734 insertions(+), 2 deletions(-) - create mode 100644 drivers/pci/host/pcie-iproc-msi.c - ---- a/drivers/pci/host/Kconfig -+++ b/drivers/pci/host/Kconfig -@@ -124,6 +124,15 @@ config PCIE_IPROC - iProc family of SoCs. An appropriate bus interface driver also needs - to be enabled - -+config PCIE_IPROC_MSI -+ bool "Broadcom iProc PCIe MSI support" -+ depends on ARCH_BCM_IPROC && PCI_MSI -+ select PCI_MSI_IRQ_DOMAIN -+ default ARCH_BCM_IPROC -+ help -+ Say Y here if you want to enable MSI support for Broadcom's iProc -+ PCIe controller -+ - config PCIE_IPROC_PLATFORM - tristate "Broadcom iProc PCIe platform bus driver" - depends on ARCH_BCM_IPROC || (ARM && COMPILE_TEST) ---- a/drivers/pci/host/Makefile -+++ b/drivers/pci/host/Makefile -@@ -15,5 +15,6 @@ obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene - obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o - obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o - obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o -+obj-$(CONFIG_PCIE_IPROC_MSI) += pcie-iproc-msi.o - obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o - obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o ---- a/drivers/pci/host/pcie-iproc-bcma.c -+++ b/drivers/pci/host/pcie-iproc-bcma.c -@@ -55,6 +55,7 @@ static int iproc_pcie_bcma_probe(struct - bcma_set_drvdata(bdev, pcie); - - pcie->base = bdev->io_addr; -+ pcie->base_addr = bdev->addr; - - res_mem.start = bdev->addr_s[0]; - res_mem.end = bdev->addr_s[0] + SZ_128M - 1; ---- /dev/null -+++ b/drivers/pci/host/pcie-iproc-msi.c -@@ -0,0 +1,675 @@ -+/* -+ * Copyright (C) 2015 Broadcom Corporation -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation version 2. -+ * -+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any -+ * kind, whether express or implied; without even the implied warranty -+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include <linux/interrupt.h> -+#include <linux/irqchip/chained_irq.h> -+#include <linux/irqdomain.h> -+#include <linux/msi.h> -+#include <linux/of_irq.h> -+#include <linux/of_pci.h> -+#include <linux/pci.h> -+ -+#include "pcie-iproc.h" -+ -+#define IPROC_MSI_INTR_EN_SHIFT 11 -+#define IPROC_MSI_INTR_EN BIT(IPROC_MSI_INTR_EN_SHIFT) -+#define IPROC_MSI_INT_N_EVENT_SHIFT 1 -+#define IPROC_MSI_INT_N_EVENT BIT(IPROC_MSI_INT_N_EVENT_SHIFT) -+#define IPROC_MSI_EQ_EN_SHIFT 0 -+#define IPROC_MSI_EQ_EN BIT(IPROC_MSI_EQ_EN_SHIFT) -+ -+#define IPROC_MSI_EQ_MASK 0x3f -+ -+/* max number of GIC interrupts */ -+#define NR_HW_IRQS 6 -+ -+/* number of entries in each event queue */ -+#define EQ_LEN 64 -+ -+/* size of each event queue memory region */ -+#define EQ_MEM_REGION_SIZE SZ_4K -+ -+/* size of each MSI address region */ -+#define MSI_MEM_REGION_SIZE SZ_4K -+ -+enum iproc_msi_reg { -+ IPROC_MSI_EQ_PAGE = 0, -+ IPROC_MSI_EQ_PAGE_UPPER, -+ IPROC_MSI_PAGE, -+ IPROC_MSI_PAGE_UPPER, -+ IPROC_MSI_CTRL, -+ IPROC_MSI_EQ_HEAD, -+ IPROC_MSI_EQ_TAIL, -+ IPROC_MSI_INTS_EN, -+ IPROC_MSI_REG_SIZE, -+}; -+ -+struct iproc_msi; -+ -+/** -+ * iProc MSI group -+ * -+ * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI -+ * event queue -+ * -+ * @msi: pointer to iProc MSI data -+ * @gic_irq: GIC interrupt -+ * @eq: Event queue number -+ */ -+struct iproc_msi_grp { -+ struct iproc_msi *msi; -+ int gic_irq; -+ unsigned int eq; -+}; -+ -+/** -+ * iProc event queue based MSI -+ * -+ * Only meant to be used on platforms without MSI support integrated into the -+ * GIC -+ * -+ * @pcie: pointer to iProc PCIe data -+ * @reg_offsets: MSI register offsets -+ * @grps: MSI groups -+ * @nr_irqs: number of total interrupts connected to GIC -+ * @nr_cpus: number of toal CPUs -+ * @has_inten_reg: indicates the MSI interrupt enable register needs to be -+ * set explicitly (required for some legacy platforms) -+ * @bitmap: MSI vector bitmap -+ * @bitmap_lock: lock to protect access to the MSI bitmap -+ * @nr_msi_vecs: total number of MSI vectors -+ * @inner_domain: inner IRQ domain -+ * @msi_domain: MSI IRQ domain -+ * @nr_eq_region: required number of 4K aligned memory region for MSI event -+ * queues -+ * @nr_msi_region: required number of 4K aligned address region for MSI posted -+ * writes -+ * @eq_cpu: pointer to allocated memory region for MSI event queues -+ * @eq_dma: DMA address of MSI event queues -+ * @msi_addr: MSI address -+ */ -+struct iproc_msi { -+ struct iproc_pcie *pcie; -+ const u16 (*reg_offsets)[IPROC_MSI_REG_SIZE]; -+ struct iproc_msi_grp *grps; -+ int nr_irqs; -+ int nr_cpus; -+ bool has_inten_reg; -+ unsigned long *bitmap; -+ struct mutex bitmap_lock; -+ unsigned int nr_msi_vecs; -+ struct irq_domain *inner_domain; -+ struct irq_domain *msi_domain; -+ unsigned int nr_eq_region; -+ unsigned int nr_msi_region; -+ void *eq_cpu; -+ dma_addr_t eq_dma; -+ phys_addr_t msi_addr; -+}; -+ -+static const u16 iproc_msi_reg_paxb[NR_HW_IRQS][IPROC_MSI_REG_SIZE] = { -+ { 0x200, 0x2c0, 0x204, 0x2c4, 0x210, 0x250, 0x254, 0x208 }, -+ { 0x200, 0x2c0, 0x204, 0x2c4, 0x214, 0x258, 0x25c, 0x208 }, -+ { 0x200, 0x2c0, 0x204, 0x2c4, 0x218, 0x260, 0x264, 0x208 }, -+ { 0x200, 0x2c0, 0x204, 0x2c4, 0x21c, 0x268, 0x26c, 0x208 }, -+ { 0x200, 0x2c0, 0x204, 0x2c4, 0x220, 0x270, 0x274, 0x208 }, -+ { 0x200, 0x2c0, 0x204, 0x2c4, 0x224, 0x278, 0x27c, 0x208 }, -+}; -+ -+static const u16 iproc_msi_reg_paxc[NR_HW_IRQS][IPROC_MSI_REG_SIZE] = { -+ { 0xc00, 0xc04, 0xc08, 0xc0c, 0xc40, 0xc50, 0xc60 }, -+ { 0xc10, 0xc14, 0xc18, 0xc1c, 0xc44, 0xc54, 0xc64 }, -+ { 0xc20, 0xc24, 0xc28, 0xc2c, 0xc48, 0xc58, 0xc68 }, -+ { 0xc30, 0xc34, 0xc38, 0xc3c, 0xc4c, 0xc5c, 0xc6c }, -+}; -+ -+static inline u32 iproc_msi_read_reg(struct iproc_msi *msi, -+ enum iproc_msi_reg reg, -+ unsigned int eq) -+{ -+ struct iproc_pcie *pcie = msi->pcie; -+ -+ return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]); -+} -+ -+static inline void iproc_msi_write_reg(struct iproc_msi *msi, -+ enum iproc_msi_reg reg, -+ int eq, u32 val) -+{ -+ struct iproc_pcie *pcie = msi->pcie; -+ -+ writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]); -+} -+ -+static inline u32 hwirq_to_group(struct iproc_msi *msi, unsigned long hwirq) -+{ -+ return (hwirq % msi->nr_irqs); -+} -+ -+static inline unsigned int iproc_msi_addr_offset(struct iproc_msi *msi, -+ unsigned long hwirq) -+{ -+ if (msi->nr_msi_region > 1) -+ return hwirq_to_group(msi, hwirq) * MSI_MEM_REGION_SIZE; -+ else -+ return hwirq_to_group(msi, hwirq) * sizeof(u32); -+} -+ -+static inline unsigned int iproc_msi_eq_offset(struct iproc_msi *msi, u32 eq) -+{ -+ if (msi->nr_eq_region > 1) -+ return eq * EQ_MEM_REGION_SIZE; -+ else -+ return eq * EQ_LEN * sizeof(u32); -+} -+ -+static struct irq_chip iproc_msi_irq_chip = { -+ .name = "iProc-MSI", -+}; -+ -+static struct msi_domain_info iproc_msi_domain_info = { -+ .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | -+ MSI_FLAG_PCI_MSIX, -+ .chip = &iproc_msi_irq_chip, -+}; -+ -+/* -+ * In iProc PCIe core, each MSI group is serviced by a GIC interrupt and a -+ * dedicated event queue. Each MSI group can support up to 64 MSI vectors -+ * -+ * The number of MSI groups varies between different iProc SoCs. The total -+ * number of CPU cores also varies. To support MSI IRQ affinity, we -+ * distribute GIC interrupts across all available CPUs. MSI vector is moved -+ * from one GIC interrupt to another to steer to the target CPU -+ * -+ * Assuming: -+ * - the number of MSI groups is M -+ * - the number of CPU cores is N -+ * - M is always a multiple of N -+ * -+ * Total number of raw MSI vectors = M * 64 -+ * Total number of supported MSI vectors = (M * 64) / N -+ */ -+static inline int hwirq_to_cpu(struct iproc_msi *msi, unsigned long hwirq) -+{ -+ return (hwirq % msi->nr_cpus); -+} -+ -+static inline unsigned long hwirq_to_canonical_hwirq(struct iproc_msi *msi, -+ unsigned long hwirq) -+{ -+ return (hwirq - hwirq_to_cpu(msi, hwirq)); -+} -+ -+static int iproc_msi_irq_set_affinity(struct irq_data *data, -+ const struct cpumask *mask, bool force) -+{ -+ struct iproc_msi *msi = irq_data_get_irq_chip_data(data); -+ int target_cpu = cpumask_first(mask); -+ int curr_cpu; -+ -+ curr_cpu = hwirq_to_cpu(msi, data->hwirq); -+ if (curr_cpu == target_cpu) -+ return IRQ_SET_MASK_OK_DONE; -+ -+ /* steer MSI to the target CPU */ -+ data->hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq) + target_cpu; -+ -+ return IRQ_SET_MASK_OK; -+} -+ -+static void iproc_msi_irq_compose_msi_msg(struct irq_data *data, -+ struct msi_msg *msg) -+{ -+ struct iproc_msi *msi = irq_data_get_irq_chip_data(data); -+ dma_addr_t addr; -+ -+ addr = msi->msi_addr + iproc_msi_addr_offset(msi, data->hwirq); -+ msg->address_lo = lower_32_bits(addr); -+ msg->address_hi = upper_32_bits(addr); -+ msg->data = data->hwirq; -+} -+ -+static struct irq_chip iproc_msi_bottom_irq_chip = { -+ .name = "MSI", -+ .irq_set_affinity = iproc_msi_irq_set_affinity, -+ .irq_compose_msi_msg = iproc_msi_irq_compose_msi_msg, -+}; -+ -+static int iproc_msi_irq_domain_alloc(struct irq_domain *domain, -+ unsigned int virq, unsigned int nr_irqs, -+ void *args) -+{ -+ struct iproc_msi *msi = domain->host_data; -+ int hwirq; -+ -+ mutex_lock(&msi->bitmap_lock); -+ -+ /* allocate 'nr_cpus' number of MSI vectors each time */ -+ hwirq = bitmap_find_next_zero_area(msi->bitmap, msi->nr_msi_vecs, 0, -+ msi->nr_cpus, 0); -+ if (hwirq < msi->nr_msi_vecs) { -+ bitmap_set(msi->bitmap, hwirq, msi->nr_cpus); -+ } else { -+ mutex_unlock(&msi->bitmap_lock); -+ return -ENOSPC; -+ } -+ -+ mutex_unlock(&msi->bitmap_lock); -+ -+ irq_domain_set_info(domain, virq, hwirq, &iproc_msi_bottom_irq_chip, -+ domain->host_data, handle_simple_irq, NULL, NULL); -+ -+ return 0; -+} -+ -+static void iproc_msi_irq_domain_free(struct irq_domain *domain, -+ unsigned int virq, unsigned int nr_irqs) -+{ -+ struct irq_data *data = irq_domain_get_irq_data(domain, virq); -+ struct iproc_msi *msi = irq_data_get_irq_chip_data(data); -+ unsigned int hwirq; -+ -+ mutex_lock(&msi->bitmap_lock); -+ -+ hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq); -+ bitmap_clear(msi->bitmap, hwirq, msi->nr_cpus); -+ -+ mutex_unlock(&msi->bitmap_lock); -+ -+ irq_domain_free_irqs_parent(domain, virq, nr_irqs); -+} -+ -+static const struct irq_domain_ops msi_domain_ops = { -+ .alloc = iproc_msi_irq_domain_alloc, -+ .free = iproc_msi_irq_domain_free, -+}; -+ -+static inline u32 decode_msi_hwirq(struct iproc_msi *msi, u32 eq, u32 head) -+{ -+ u32 *msg, hwirq; -+ unsigned int offs; -+ -+ offs = iproc_msi_eq_offset(msi, eq) + head * sizeof(u32); -+ msg = (u32 *)(msi->eq_cpu + offs); -+ hwirq = *msg & IPROC_MSI_EQ_MASK; -+ -+ /* -+ * Since we have multiple hwirq mapped to a single MSI vector, -+ * now we need to derive the hwirq at CPU0. It can then be used to -+ * mapped back to virq -+ */ -+ return hwirq_to_canonical_hwirq(msi, hwirq); -+} -+ -+static void iproc_msi_handler(struct irq_desc *desc) -+{ -+ struct irq_chip *chip = irq_desc_get_chip(desc); -+ struct iproc_msi_grp *grp; -+ struct iproc_msi *msi; -+ struct iproc_pcie *pcie; -+ u32 eq, head, tail, nr_events; -+ unsigned long hwirq; -+ int virq; -+ -+ chained_irq_enter(chip, desc); -+ -+ grp = irq_desc_get_handler_data(desc); -+ msi = grp->msi; -+ pcie = msi->pcie; -+ eq = grp->eq; -+ -+ /* -+ * iProc MSI event queue is tracked by head and tail pointers. Head -+ * pointer indicates the next entry (MSI data) to be consumed by SW in -+ * the queue and needs to be updated by SW. iProc MSI core uses the -+ * tail pointer as the next data insertion point -+ * -+ * Entries between head and tail pointers contain valid MSI data. MSI -+ * data is guaranteed to be in the event queue memory before the tail -+ * pointer is updated by the iProc MSI core -+ */ -+ head = iproc_msi_read_reg(msi, IPROC_MSI_EQ_HEAD, -+ eq) & IPROC_MSI_EQ_MASK; -+ do { -+ tail = iproc_msi_read_reg(msi, IPROC_MSI_EQ_TAIL, -+ eq) & IPROC_MSI_EQ_MASK; -+ -+ /* -+ * Figure out total number of events (MSI data) to be -+ * processed -+ */ -+ nr_events = (tail < head) ? -+ (EQ_LEN - (head - tail)) : (tail - head); -+ if (!nr_events) -+ break; -+ -+ /* process all outstanding events */ -+ while (nr_events--) { -+ hwirq = decode_msi_hwirq(msi, eq, head); -+ virq = irq_find_mapping(msi->inner_domain, hwirq); -+ generic_handle_irq(virq); -+ -+ head++; -+ head %= EQ_LEN; -+ } -+ -+ /* -+ * Now all outstanding events have been processed. Update the -+ * head pointer -+ */ -+ iproc_msi_write_reg(msi, IPROC_MSI_EQ_HEAD, eq, head); -+ -+ /* -+ * Now go read the tail pointer again to see if there are new -+ * oustanding events that came in during the above window -+ */ -+ } while (true); -+ -+ chained_irq_exit(chip, desc); -+} -+ -+static void iproc_msi_enable(struct iproc_msi *msi) -+{ -+ int i, eq; -+ u32 val; -+ -+ /* program memory region for each event queue */ -+ for (i = 0; i < msi->nr_eq_region; i++) { -+ dma_addr_t addr = msi->eq_dma + (i * EQ_MEM_REGION_SIZE); -+ -+ iproc_msi_write_reg(msi, IPROC_MSI_EQ_PAGE, i, -+ lower_32_bits(addr)); -+ iproc_msi_write_reg(msi, IPROC_MSI_EQ_PAGE_UPPER, i, -+ upper_32_bits(addr)); -+ } -+ -+ /* program address region for MSI posted writes */ -+ for (i = 0; i < msi->nr_msi_region; i++) { -+ phys_addr_t addr = msi->msi_addr + (i * MSI_MEM_REGION_SIZE); -+ -+ iproc_msi_write_reg(msi, IPROC_MSI_PAGE, i, -+ lower_32_bits(addr)); -+ iproc_msi_write_reg(msi, IPROC_MSI_PAGE_UPPER, i, -+ upper_32_bits(addr)); -+ } -+ -+ for (eq = 0; eq < msi->nr_irqs; eq++) { -+ /* enable MSI event queue */ -+ val = IPROC_MSI_INTR_EN | IPROC_MSI_INT_N_EVENT | -+ IPROC_MSI_EQ_EN; -+ iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val); -+ -+ /* -+ * Some legacy platforms require the MSI interrupt enable -+ * register to be set explicitly -+ */ -+ if (msi->has_inten_reg) { -+ val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq); -+ val |= BIT(eq); -+ iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val); -+ } -+ } -+} -+ -+static void iproc_msi_disable(struct iproc_msi *msi) -+{ -+ u32 eq, val; -+ -+ for (eq = 0; eq < msi->nr_irqs; eq++) { -+ if (msi->has_inten_reg) { -+ val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq); -+ val &= ~BIT(eq); -+ iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val); -+ } -+ -+ val = iproc_msi_read_reg(msi, IPROC_MSI_CTRL, eq); -+ val &= ~(IPROC_MSI_INTR_EN | IPROC_MSI_INT_N_EVENT | -+ IPROC_MSI_EQ_EN); -+ iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val); -+ } -+} -+ -+static int iproc_msi_alloc_domains(struct device_node *node, -+ struct iproc_msi *msi) -+{ -+ msi->inner_domain = irq_domain_add_linear(NULL, msi->nr_msi_vecs, -+ &msi_domain_ops, msi); -+ if (!msi->inner_domain) -+ return -ENOMEM; -+ -+ msi->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node), -+ &iproc_msi_domain_info, -+ msi->inner_domain); -+ if (!msi->msi_domain) { -+ irq_domain_remove(msi->inner_domain); -+ return -ENOMEM; -+ } -+ -+ return 0; -+} -+ -+static void iproc_msi_free_domains(struct iproc_msi *msi) -+{ -+ if (msi->msi_domain) -+ irq_domain_remove(msi->msi_domain); -+ -+ if (msi->inner_domain) -+ irq_domain_remove(msi->inner_domain); -+} -+ -+static void iproc_msi_irq_free(struct iproc_msi *msi, unsigned int cpu) -+{ -+ int i; -+ -+ for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) { -+ irq_set_chained_handler_and_data(msi->grps[i].gic_irq, -+ NULL, NULL); -+ } -+} -+ -+static int iproc_msi_irq_setup(struct iproc_msi *msi, unsigned int cpu) -+{ -+ int i, ret; -+ cpumask_var_t mask; -+ struct iproc_pcie *pcie = msi->pcie; -+ -+ for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) { -+ irq_set_chained_handler_and_data(msi->grps[i].gic_irq, -+ iproc_msi_handler, -+ &msi->grps[i]); -+ /* dedicate GIC interrupt to each CPU core */ -+ if (alloc_cpumask_var(&mask, GFP_KERNEL)) { -+ cpumask_clear(mask); -+ cpumask_set_cpu(cpu, mask); -+ ret = irq_set_affinity(msi->grps[i].gic_irq, mask); -+ if (ret) -+ dev_err(pcie->dev, -+ "failed to set affinity for IRQ%d\n", -+ msi->grps[i].gic_irq); -+ free_cpumask_var(mask); -+ } else { -+ dev_err(pcie->dev, "failed to alloc CPU mask\n"); -+ ret = -EINVAL; -+ } -+ -+ if (ret) { -+ /* free all configured/unconfigured irqs */ -+ iproc_msi_irq_free(msi, cpu); -+ return ret; -+ } -+ } -+ -+ return 0; -+} -+ -+int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node) -+{ -+ struct iproc_msi *msi; -+ int i, ret; -+ unsigned int cpu; -+ -+ if (!of_device_is_compatible(node, "brcm,iproc-msi")) -+ return -ENODEV; -+ -+ if (!of_find_property(node, "msi-controller", NULL)) -+ return -ENODEV; -+ -+ if (pcie->msi) -+ return -EBUSY; -+ -+ msi = devm_kzalloc(pcie->dev, sizeof(*msi), GFP_KERNEL); -+ if (!msi) -+ return -ENOMEM; -+ -+ msi->pcie = pcie; -+ pcie->msi = msi; -+ msi->msi_addr = pcie->base_addr; -+ mutex_init(&msi->bitmap_lock); -+ msi->nr_cpus = num_possible_cpus(); -+ -+ msi->nr_irqs = of_irq_count(node); -+ if (!msi->nr_irqs) { -+ dev_err(pcie->dev, "found no MSI GIC interrupt\n"); -+ return -ENODEV; -+ } -+ -+ if (msi->nr_irqs > NR_HW_IRQS) { -+ dev_warn(pcie->dev, "too many MSI GIC interrupts defined %d\n", -+ msi->nr_irqs); -+ msi->nr_irqs = NR_HW_IRQS; -+ } -+ -+ if (msi->nr_irqs < msi->nr_cpus) { -+ dev_err(pcie->dev, -+ "not enough GIC interrupts for MSI affinity\n"); -+ return -EINVAL; -+ } -+ -+ if (msi->nr_irqs % msi->nr_cpus != 0) { -+ msi->nr_irqs -= msi->nr_irqs % msi->nr_cpus; -+ dev_warn(pcie->dev, "Reducing number of interrupts to %d\n", -+ msi->nr_irqs); -+ } -+ -+ switch (pcie->type) { -+ case IPROC_PCIE_PAXB: -+ msi->reg_offsets = iproc_msi_reg_paxb; -+ msi->nr_eq_region = 1; -+ msi->nr_msi_region = 1; -+ break; -+ case IPROC_PCIE_PAXC: -+ msi->reg_offsets = iproc_msi_reg_paxc; -+ msi->nr_eq_region = msi->nr_irqs; -+ msi->nr_msi_region = msi->nr_irqs; -+ break; -+ default: -+ dev_err(pcie->dev, "incompatible iProc PCIe interface\n"); -+ return -EINVAL; -+ } -+ -+ if (of_find_property(node, "brcm,pcie-msi-inten", NULL)) -+ msi->has_inten_reg = true; -+ -+ msi->nr_msi_vecs = msi->nr_irqs * EQ_LEN; -+ msi->bitmap = devm_kcalloc(pcie->dev, BITS_TO_LONGS(msi->nr_msi_vecs), -+ sizeof(*msi->bitmap), GFP_KERNEL); -+ if (!msi->bitmap) -+ return -ENOMEM; -+ -+ msi->grps = devm_kcalloc(pcie->dev, msi->nr_irqs, sizeof(*msi->grps), -+ GFP_KERNEL); -+ if (!msi->grps) -+ return -ENOMEM; -+ -+ for (i = 0; i < msi->nr_irqs; i++) { -+ unsigned int irq = irq_of_parse_and_map(node, i); -+ -+ if (!irq) { -+ dev_err(pcie->dev, "unable to parse/map interrupt\n"); -+ ret = -ENODEV; -+ goto free_irqs; -+ } -+ msi->grps[i].gic_irq = irq; -+ msi->grps[i].msi = msi; -+ msi->grps[i].eq = i; -+ } -+ -+ /* reserve memory for event queue and make sure memories are zeroed */ -+ msi->eq_cpu = dma_zalloc_coherent(pcie->dev, -+ msi->nr_eq_region * EQ_MEM_REGION_SIZE, -+ &msi->eq_dma, GFP_KERNEL); -+ if (!msi->eq_cpu) { -+ ret = -ENOMEM; -+ goto free_irqs; -+ } -+ -+ ret = iproc_msi_alloc_domains(node, msi); -+ if (ret) { -+ dev_err(pcie->dev, "failed to create MSI domains\n"); -+ goto free_eq_dma; -+ } -+ -+ for_each_online_cpu(cpu) { -+ ret = iproc_msi_irq_setup(msi, cpu); -+ if (ret) -+ goto free_msi_irq; -+ } -+ -+ iproc_msi_enable(msi); -+ -+ return 0; -+ -+free_msi_irq: -+ for_each_online_cpu(cpu) -+ iproc_msi_irq_free(msi, cpu); -+ iproc_msi_free_domains(msi); -+ -+free_eq_dma: -+ dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE, -+ msi->eq_cpu, msi->eq_dma); -+ -+free_irqs: -+ for (i = 0; i < msi->nr_irqs; i++) { -+ if (msi->grps[i].gic_irq) -+ irq_dispose_mapping(msi->grps[i].gic_irq); -+ } -+ pcie->msi = NULL; -+ return ret; -+} -+EXPORT_SYMBOL(iproc_msi_init); -+ -+void iproc_msi_exit(struct iproc_pcie *pcie) -+{ -+ struct iproc_msi *msi = pcie->msi; -+ unsigned int i, cpu; -+ -+ if (!msi) -+ return; -+ -+ iproc_msi_disable(msi); -+ -+ for_each_online_cpu(cpu) -+ iproc_msi_irq_free(msi, cpu); -+ -+ iproc_msi_free_domains(msi); -+ -+ dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE, -+ msi->eq_cpu, msi->eq_dma); -+ -+ for (i = 0; i < msi->nr_irqs; i++) { -+ if (msi->grps[i].gic_irq) -+ irq_dispose_mapping(msi->grps[i].gic_irq); -+ } -+} -+EXPORT_SYMBOL(iproc_msi_exit); ---- a/drivers/pci/host/pcie-iproc-platform.c -+++ b/drivers/pci/host/pcie-iproc-platform.c -@@ -71,6 +71,7 @@ static int iproc_pcie_pltfm_probe(struct - dev_err(pcie->dev, "unable to map controller registers\n"); - return -ENOMEM; - } -+ pcie->base_addr = reg.start; - - if (of_property_read_bool(np, "brcm,pcie-ob")) { - u32 val; ---- a/drivers/pci/host/pcie-iproc.c -+++ b/drivers/pci/host/pcie-iproc.c -@@ -440,6 +440,26 @@ static int iproc_pcie_map_ranges(struct - return 0; - } - -+static int iproc_pcie_msi_enable(struct iproc_pcie *pcie) -+{ -+ struct device_node *msi_node; -+ -+ msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0); -+ if (!msi_node) -+ return -ENODEV; -+ -+ /* -+ * If another MSI controller is being used, the call below should fail -+ * but that is okay -+ */ -+ return iproc_msi_init(pcie, msi_node); -+} -+ -+static void iproc_pcie_msi_disable(struct iproc_pcie *pcie) -+{ -+ iproc_msi_exit(pcie); -+} -+ - int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res) - { - int ret; -@@ -507,6 +527,10 @@ int iproc_pcie_setup(struct iproc_pcie * - - iproc_pcie_enable(pcie); - -+ if (IS_ENABLED(CONFIG_PCI_MSI)) -+ if (iproc_pcie_msi_enable(pcie)) -+ dev_info(pcie->dev, "not using iProc MSI\n"); -+ - pci_scan_child_bus(bus); - pci_assign_unassigned_bus_resources(bus); - pci_fixup_irqs(pci_common_swizzle, pcie->map_irq); -@@ -531,6 +555,8 @@ int iproc_pcie_remove(struct iproc_pcie - pci_stop_root_bus(pcie->root_bus); - pci_remove_root_bus(pcie->root_bus); - -+ iproc_pcie_msi_disable(pcie); -+ - phy_power_off(pcie->phy); - phy_exit(pcie->phy); - ---- a/drivers/pci/host/pcie-iproc.h -+++ b/drivers/pci/host/pcie-iproc.h -@@ -41,6 +41,8 @@ struct iproc_pcie_ob { - resource_size_t window_size; - }; - -+struct iproc_msi; -+ - /** - * iProc PCIe device - * -@@ -48,19 +50,21 @@ struct iproc_pcie_ob { - * @type: iProc PCIe interface type - * @reg_offsets: register offsets - * @base: PCIe host controller I/O register base -+ * @base_addr: PCIe host controller register base physical address - * @sysdata: Per PCI controller data (ARM-specific) - * @root_bus: pointer to root bus - * @phy: optional PHY device that controls the Serdes -- * @irqs: interrupt IDs - * @map_irq: function callback to map interrupts -- * @need_ob_cfg: indidates SW needs to configure the outbound mapping window -+ * @need_ob_cfg: indicates SW needs to configure the outbound mapping window - * @ob: outbound mapping parameters -+ * @msi: MSI data - */ - struct iproc_pcie { - struct device *dev; - enum iproc_pcie_type type; - const u16 *reg_offsets; - void __iomem *base; -+ phys_addr_t base_addr; - #ifdef CONFIG_ARM - struct pci_sys_data sysdata; - #endif -@@ -69,9 +73,24 @@ struct iproc_pcie { - int (*map_irq)(const struct pci_dev *, u8, u8); - bool need_ob_cfg; - struct iproc_pcie_ob ob; -+ struct iproc_msi *msi; - }; - - int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res); - int iproc_pcie_remove(struct iproc_pcie *pcie); - -+#ifdef CONFIG_PCI_MSI -+int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node); -+void iproc_msi_exit(struct iproc_pcie *pcie); -+#else -+static inline int iproc_msi_init(struct iproc_pcie *pcie, -+ struct device_node *node) -+{ -+ return -ENODEV; -+} -+static void iproc_msi_exit(struct iproc_pcie *pcie) -+{ -+} -+#endif -+ - #endif /* _PCIE_IPROC_H */ diff --git a/target/linux/bcm53xx/patches-4.3/154-PCI-iproc-Allow-multiple-devices-except-on-PAXC.patch b/target/linux/bcm53xx/patches-4.3/154-PCI-iproc-Allow-multiple-devices-except-on-PAXC.patch deleted file mode 100644 index 1955c01806..0000000000 --- a/target/linux/bcm53xx/patches-4.3/154-PCI-iproc-Allow-multiple-devices-except-on-PAXC.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 46560388c476c8471fde7712c10f9fad8d0d1875 Mon Sep 17 00:00:00 2001 -From: Ray Jui <rjui@broadcom.com> -Date: Wed, 27 Jan 2016 16:52:24 -0600 -Subject: [PATCH] PCI: iproc: Allow multiple devices except on PAXC - -Commit 943ebae781f5 ("PCI: iproc: Add PAXC interface support") only allowed -device 0, which is a regression on BCMA-based platforms. - -All systems support only one device, a Root Port at 00:00.0, on the root -bus. PAXC-based systems support only the Root Port (00:00.0) and a single -device (with multiple functions) below it, e.g., 01:00.0, 01:00.1, etc. -Non-PAXC systems support arbitrary devices below the Root Port. - -[bhelgaas: changelog, fold in removal of MAX_NUM_PAXC_PF check] -Fixes: 943ebae781f5 ("PCI: iproc: Add PAXC interface support") -Reported-by: Rafal Milecki <zajec5@gmail.com> -Signed-off-by: Ray Jui <rjui@broadcom.com> -Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> ---- - drivers/pci/host/pcie-iproc.c | 29 +++++++++++------------------ - 1 file changed, 11 insertions(+), 18 deletions(-) - ---- a/drivers/pci/host/pcie-iproc.c -+++ b/drivers/pci/host/pcie-iproc.c -@@ -64,7 +64,6 @@ - #define OARR_SIZE_CFG BIT(OARR_SIZE_CFG_SHIFT) - - #define MAX_NUM_OB_WINDOWS 2 --#define MAX_NUM_PAXC_PF 4 - - #define IPROC_PCIE_REG_INVALID 0xffff - -@@ -170,20 +169,6 @@ static inline void iproc_pcie_ob_write(struct iproc_pcie *pcie, - writel(val, pcie->base + offset + (window * 8)); - } - --static inline bool iproc_pcie_device_is_valid(struct iproc_pcie *pcie, -- unsigned int slot, -- unsigned int fn) --{ -- if (slot > 0) -- return false; -- -- /* PAXC can only support limited number of functions */ -- if (pcie->type == IPROC_PCIE_PAXC && fn >= MAX_NUM_PAXC_PF) -- return false; -- -- return true; --} -- - /** - * Note access to the configuration registers are protected at the higher layer - * by 'pci_lock' in drivers/pci/access.c -@@ -199,11 +184,11 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus, - u32 val; - u16 offset; - -- if (!iproc_pcie_device_is_valid(pcie, slot, fn)) -- return NULL; -- - /* root complex access */ - if (busno == 0) { -+ if (slot > 0 || fn > 0) -+ return NULL; -+ - iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR, - where & CFG_IND_ADDR_MASK); - offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA); -@@ -213,6 +198,14 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus, - return (pcie->base + offset); - } - -+ /* -+ * PAXC is connected to an internally emulated EP within the SoC. It -+ * allows only one device. -+ */ -+ if (pcie->type == IPROC_PCIE_PAXC) -+ if (slot > 0) -+ return NULL; -+ - /* EP device access */ - val = (busno << CFG_ADDR_BUS_NUM_SHIFT) | - (slot << CFG_ADDR_DEV_NUM_SHIFT) | diff --git a/target/linux/bcm53xx/patches-4.3/170-ARM-BCM5301X-Add-missing-Netgear-R8000-LEDs.patch b/target/linux/bcm53xx/patches-4.3/170-ARM-BCM5301X-Add-missing-Netgear-R8000-LEDs.patch deleted file mode 100644 index 60fba1315a..0000000000 --- a/target/linux/bcm53xx/patches-4.3/170-ARM-BCM5301X-Add-missing-Netgear-R8000-LEDs.patch +++ /dev/null @@ -1,52 +0,0 @@ -From b58682598541262f967ecd6db04bacac38026d3c Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> -Date: Fri, 30 Oct 2015 15:29:52 +0100 -Subject: [PATCH] ARM: BCM5301X: Add missing Netgear R8000 LEDs -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Rafał Miłecki <zajec5@gmail.com> ---- - arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 30 +++++++++++++++++++++++++++++ - 1 file changed, 30 insertions(+) - ---- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts -+++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts -@@ -50,6 +50,36 @@ - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; - }; -+ -+ wireless { -+ label = "bcm53xx:white:wireless"; -+ gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "default-off"; -+ }; -+ -+ wps { -+ label = "bcm53xx:white:wps"; -+ gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "default-off"; -+ }; -+ -+ 5ghz-2 { -+ label = "bcm53xx:white:5ghz-2"; -+ gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; -+ linux,default-trigger = "default-off"; -+ }; -+ -+ usb3 { -+ label = "bcm53xx:white:usb3"; -+ gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; -+ linux,default-trigger = "default-off"; -+ }; -+ -+ usb2 { -+ label = "bcm53xx:white:usb2"; -+ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; -+ linux,default-trigger = "default-off"; -+ }; - }; - - gpio-keys { diff --git a/target/linux/bcm53xx/patches-4.3/186-USB-bcma-switch-to-GPIO-descriptor-for-power-control.patch b/target/linux/bcm53xx/patches-4.3/186-USB-bcma-switch-to-GPIO-descriptor-for-power-control.patch deleted file mode 100644 index f1995d1e6d..0000000000 --- a/target/linux/bcm53xx/patches-4.3/186-USB-bcma-switch-to-GPIO-descriptor-for-power-control.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 0cb136f9882e4649ad6160bb7b48955ff728888c Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> -Date: Sun, 1 Nov 2015 08:17:21 +0100 -Subject: [PATCH V2] USB: bcma: switch to GPIO descriptor for power control -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -So far we were using simple (legacy) GPIO functions & some poor logic to -control power. It got many drawbacks: we were ignoring OF flags -(GPIO_ACTIVE_LOW), we were not setting direction to output and we were -assuming gpio_request success all the time. -Fix it by switching to gpiod functions and adding appropriate checks. - -Signed-off-by: Rafał Miłecki <zajec5@gmail.com> ---- - drivers/usb/host/bcma-hcd.c | 21 ++++++++++----------- - 1 file changed, 10 insertions(+), 11 deletions(-) - ---- a/drivers/usb/host/bcma-hcd.c -+++ b/drivers/usb/host/bcma-hcd.c -@@ -21,6 +21,7 @@ - */ - #include <linux/bcma/bcma.h> - #include <linux/delay.h> -+#include <linux/gpio/consumer.h> - #include <linux/platform_device.h> - #include <linux/module.h> - #include <linux/slab.h> -@@ -36,6 +37,7 @@ MODULE_LICENSE("GPL"); - struct bcma_hcd_device { - struct platform_device *ehci_dev; - struct platform_device *ohci_dev; -+ struct gpio_desc *gpio_desc; - }; - - /* Wait for bitmask in a register to get set or cleared. -@@ -228,19 +230,12 @@ static void bcma_hcd_init_chip_arm(struc - - static void bcma_hci_platform_power_gpio(struct bcma_device *dev, bool val) - { -- int gpio; -+ struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev); - -- gpio = of_get_named_gpio(dev->dev.of_node, "vcc-gpio", 0); -- if (!gpio_is_valid(gpio)) -+ if (IS_ERR_OR_NULL(usb_dev->gpio_desc)) - return; - -- if (val) { -- gpio_request(gpio, "bcma-hcd-gpio"); -- gpio_set_value(gpio, 1); -- } else { -- gpio_set_value(gpio, 0); -- gpio_free(gpio); -- } -+ gpiod_set_value(usb_dev->gpio_desc, val); - } - - static const struct usb_ehci_pdata ehci_pdata = { -@@ -314,7 +309,11 @@ static int bcma_hcd_probe(struct bcma_de - if (!usb_dev) - return -ENOMEM; - -- bcma_hci_platform_power_gpio(dev, true); -+ if (dev->dev.of_node) -+ usb_dev->gpio_desc = devm_get_gpiod_from_child(&dev->dev, "vcc", -+ &dev->dev.of_node->fwnode); -+ if (!IS_ERR_OR_NULL(usb_dev->gpio_desc)) -+ gpiod_direction_output(usb_dev->gpio_desc, 1); - - switch (dev->id.id) { - case BCMA_CORE_NS_USB20: diff --git a/target/linux/bcm53xx/patches-4.3/190-usb-xhci-plat-fix-adding-usb3-lpm-capable-quirk.patch b/target/linux/bcm53xx/patches-4.3/190-usb-xhci-plat-fix-adding-usb3-lpm-capable-quirk.patch deleted file mode 100644 index a769650e3f..0000000000 --- a/target/linux/bcm53xx/patches-4.3/190-usb-xhci-plat-fix-adding-usb3-lpm-capable-quirk.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 1420e53fc88673683f8990aa5342e7b2640ce165 Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens <hauke@hauke-m.de> -Date: Sun, 18 Oct 2015 19:13:27 +0200 -Subject: [PATCH v3 1/6] usb: xhci: plat: fix adding usb3-lpm-capable quirk - -The xhci->quirks member is overwritten in xhci_gen_setup() with the -quirks given through the module load parameter. Without this patch the -usb3-lpm-capable quirk will be over written before it gets used. This -patch moves the quirks code to the xhci_plat_quirks() callback function -which gets called directly after the quirks member variable is -overwritten with the module load parameter. - -I do not have any hardware which is using usb3-lpm-capabls so I can not -test this on real hardware. - -Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> ---- - drivers/usb/host/xhci-plat.c | 14 ++++++++------ - 1 file changed, 8 insertions(+), 6 deletions(-) - ---- a/drivers/usb/host/xhci-plat.c -+++ b/drivers/usb/host/xhci-plat.c -@@ -37,12 +37,20 @@ static const struct xhci_driver_override - - static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci) - { -+ struct platform_device *pdev = to_platform_device(dev); -+ struct device_node *node = pdev->dev.of_node; -+ struct usb_xhci_pdata *pdata = dev_get_platdata(&pdev->dev); -+ - /* - * As of now platform drivers don't provide MSI support so we ensure - * here that the generic code does not try to make a pci_dev from our - * dev struct in order to setup MSI - */ - xhci->quirks |= XHCI_PLAT; -+ -+ if ((node && of_property_read_bool(node, "usb3-lpm-capable")) || -+ (pdata && pdata->usb3_lpm_capable)) -+ xhci->quirks |= XHCI_LPM_SUPPORT; - } - - /* called during probe() after chip reset completes */ -@@ -74,8 +82,6 @@ static int xhci_plat_start(struct usb_hc - - static int xhci_plat_probe(struct platform_device *pdev) - { -- struct device_node *node = pdev->dev.of_node; -- struct usb_xhci_pdata *pdata = dev_get_platdata(&pdev->dev); - const struct hc_driver *driver; - struct xhci_hcd *xhci; - struct resource *res; -@@ -148,10 +154,6 @@ static int xhci_plat_probe(struct platfo - goto disable_clk; - } - -- if ((node && of_property_read_bool(node, "usb3-lpm-capable")) || -- (pdata && pdata->usb3_lpm_capable)) -- xhci->quirks |= XHCI_LPM_SUPPORT; -- - if (HCC_MAX_PSA(xhci->hcc_params) >= 4) - xhci->shared_hcd->can_do_streams = 1; - diff --git a/target/linux/bcm53xx/patches-4.3/191-usb-xhci-add-Broadcom-specific-fake-doorbell.patch b/target/linux/bcm53xx/patches-4.3/191-usb-xhci-add-Broadcom-specific-fake-doorbell.patch deleted file mode 100644 index a0cc267422..0000000000 --- a/target/linux/bcm53xx/patches-4.3/191-usb-xhci-add-Broadcom-specific-fake-doorbell.patch +++ /dev/null @@ -1,135 +0,0 @@ -From dd0e5f9a6a4aed849bdb80641c2a2350476cede7 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> -Date: Sun, 21 Jun 2015 11:10:49 +0200 -Subject: [PATCH v3 2/6] usb: xhci: add Broadcom specific fake doorbell -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This fixes problem with controller seeing devices only in some small -percentage of cold boots. -This quirk is also added to the platform data so we can activate it -when we register our platform driver. - -Signed-off-by: Rafał Miłecki <zajec5@gmail.com> -Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> ---- - drivers/usb/host/xhci-plat.c | 3 +++ - drivers/usb/host/xhci.c | 57 +++++++++++++++++++++++++++++++++++++--- - drivers/usb/host/xhci.h | 1 + - include/linux/usb/xhci_pdriver.h | 1 + - 4 files changed, 59 insertions(+), 3 deletions(-) - ---- a/drivers/usb/host/xhci-plat.c -+++ b/drivers/usb/host/xhci-plat.c -@@ -51,6 +51,9 @@ static void xhci_plat_quirks(struct devi - if ((node && of_property_read_bool(node, "usb3-lpm-capable")) || - (pdata && pdata->usb3_lpm_capable)) - xhci->quirks |= XHCI_LPM_SUPPORT; -+ -+ if (pdata && pdata->usb3_fake_doorbell) -+ xhci->quirks |= XHCI_FAKE_DOORBELL; - } - - /* called during probe() after chip reset completes */ ---- a/drivers/usb/host/xhci.c -+++ b/drivers/usb/host/xhci.c -@@ -121,6 +121,39 @@ int xhci_halt(struct xhci_hcd *xhci) - return ret; - } - -+static int xhci_fake_doorbell(struct xhci_hcd *xhci, int slot_id) -+{ -+ u32 temp; -+ -+ /* alloc a virt device for slot */ -+ if (!xhci_alloc_virt_device(xhci, slot_id, NULL, GFP_NOIO)) { -+ xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n"); -+ return -ENOMEM; -+ } -+ -+ /* ring fake doorbell for slot_id ep 0 */ -+ xhci_ring_ep_doorbell(xhci, slot_id, 0, 0); -+ usleep_range(1000, 1500); -+ -+ /* read the status register to check if HSE is set or not? */ -+ temp = readl(&xhci->op_regs->status); -+ -+ /* clear HSE if set */ -+ if (temp & STS_FATAL) { -+ xhci_dbg(xhci, "HSE problem detected, status: 0x%x\n", temp); -+ temp &= ~(0x1fff); -+ temp |= STS_FATAL; -+ writel(temp, &xhci->op_regs->status); -+ usleep_range(1000, 1500); -+ readl(&xhci->op_regs->status); -+ } -+ -+ /* Free virt device */ -+ xhci_free_virt_device(xhci, slot_id); -+ -+ return 0; -+} -+ - /* - * Set the run bit and wait for the host to be running. - */ -@@ -567,10 +600,25 @@ int xhci_init(struct usb_hcd *hcd) - - static int xhci_run_finished(struct xhci_hcd *xhci) - { -- if (xhci_start(xhci)) { -- xhci_halt(xhci); -- return -ENODEV; -+ int err; -+ -+ err = xhci_start(xhci); -+ if (err) { -+ err = -ENODEV; -+ goto out_err; -+ } -+ if (xhci->quirks & XHCI_FAKE_DOORBELL) { -+ err = xhci_fake_doorbell(xhci, 1); -+ if (err) -+ goto out_err; -+ -+ err = xhci_start(xhci); -+ if (err) { -+ err = -ENODEV; -+ goto out_err; -+ } - } -+ - xhci->shared_hcd->state = HC_STATE_RUNNING; - xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; - -@@ -580,6 +628,9 @@ static int xhci_run_finished(struct xhci - xhci_dbg_trace(xhci, trace_xhci_dbg_init, - "Finished xhci_run for USB3 roothub"); - return 0; -+out_err: -+ xhci_halt(xhci); -+ return err; - } - - /* ---- a/drivers/usb/host/xhci.h -+++ b/drivers/usb/host/xhci.h -@@ -1575,6 +1575,7 @@ struct xhci_hcd { - /* For controllers with a broken beyond repair streams implementation */ - #define XHCI_BROKEN_STREAMS (1 << 19) - #define XHCI_PME_STUCK_QUIRK (1 << 20) -+#define XHCI_FAKE_DOORBELL (1 << 21) - unsigned int num_active_eps; - unsigned int limit_active_eps; - /* There are two roothubs to keep track of bus suspend info for */ ---- a/include/linux/usb/xhci_pdriver.h -+++ b/include/linux/usb/xhci_pdriver.h -@@ -22,6 +22,7 @@ - */ - struct usb_xhci_pdata { - unsigned usb3_lpm_capable:1; -+ unsigned usb3_fake_doorbell:1; - }; - - #endif /* __USB_CORE_XHCI_PDRIVER_H */ diff --git a/target/linux/bcm53xx/patches-4.3/195-USB-bcma-make-helper-creating-platform-dev-more-gene.patch b/target/linux/bcm53xx/patches-4.3/195-USB-bcma-make-helper-creating-platform-dev-more-gene.patch deleted file mode 100644 index 17a9260d80..0000000000 --- a/target/linux/bcm53xx/patches-4.3/195-USB-bcma-make-helper-creating-platform-dev-more-gene.patch +++ /dev/null @@ -1,75 +0,0 @@ -From c7c7bf7fcbacadac7781783de25fe1e13e2a2c35 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> -Date: Tue, 16 Jun 2015 12:33:46 +0200 -Subject: [PATCH v3 3/6] usb: bcma: make helper creating platform dev more - generic -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Having "bool ohci" argument bounded us to two cases only and didn't -allow re-using this code for XHCI. - -Signed-off-by: Rafał Miłecki <zajec5@gmail.com> -Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> ---- - drivers/usb/host/bcma-hcd.c | 24 +++++++++++++----------- - 1 file changed, 13 insertions(+), 11 deletions(-) - ---- a/drivers/usb/host/bcma-hcd.c -+++ b/drivers/usb/host/bcma-hcd.c -@@ -244,7 +244,10 @@ static const struct usb_ehci_pdata ehci_ - static const struct usb_ohci_pdata ohci_pdata = { - }; - --static struct platform_device *bcma_hcd_create_pdev(struct bcma_device *dev, bool ohci, u32 addr) -+static struct platform_device *bcma_hcd_create_pdev(struct bcma_device *dev, -+ const char *name, u32 addr, -+ const void *data, -+ size_t size) - { - struct platform_device *hci_dev; - struct resource hci_res[2]; -@@ -259,8 +262,7 @@ static struct platform_device *bcma_hcd_ - hci_res[1].start = dev->irq; - hci_res[1].flags = IORESOURCE_IRQ; - -- hci_dev = platform_device_alloc(ohci ? "ohci-platform" : -- "ehci-platform" , 0); -+ hci_dev = platform_device_alloc(name, 0); - if (!hci_dev) - return ERR_PTR(-ENOMEM); - -@@ -271,12 +273,8 @@ static struct platform_device *bcma_hcd_ - ARRAY_SIZE(hci_res)); - if (ret) - goto err_alloc; -- if (ohci) -- ret = platform_device_add_data(hci_dev, &ohci_pdata, -- sizeof(ohci_pdata)); -- else -- ret = platform_device_add_data(hci_dev, &ehci_pdata, -- sizeof(ehci_pdata)); -+ if (data) -+ ret = platform_device_add_data(hci_dev, data, size); - if (ret) - goto err_alloc; - ret = platform_device_add(hci_dev); -@@ -333,11 +331,15 @@ static int bcma_hcd_probe(struct bcma_de - && chipinfo->rev == 0) - ohci_addr = 0x18009000; - -- usb_dev->ohci_dev = bcma_hcd_create_pdev(dev, true, ohci_addr); -+ usb_dev->ohci_dev = bcma_hcd_create_pdev(dev, "ohci-platform", -+ ohci_addr, &ohci_pdata, -+ sizeof(ohci_pdata)); - if (IS_ERR(usb_dev->ohci_dev)) - return PTR_ERR(usb_dev->ohci_dev); - -- usb_dev->ehci_dev = bcma_hcd_create_pdev(dev, false, dev->addr); -+ usb_dev->ehci_dev = bcma_hcd_create_pdev(dev, "ehci-platform", -+ dev->addr, &ehci_pdata, -+ sizeof(ehci_pdata)); - if (IS_ERR(usb_dev->ehci_dev)) { - err = PTR_ERR(usb_dev->ehci_dev); - goto err_unregister_ohci_dev; diff --git a/target/linux/bcm53xx/patches-4.3/196-USB-bcma-use-separated-function-for-USB-2.0-initiali.patch b/target/linux/bcm53xx/patches-4.3/196-USB-bcma-use-separated-function-for-USB-2.0-initiali.patch deleted file mode 100644 index 262192b7bf..0000000000 --- a/target/linux/bcm53xx/patches-4.3/196-USB-bcma-use-separated-function-for-USB-2.0-initiali.patch +++ /dev/null @@ -1,112 +0,0 @@ -From fa5622c2fadae573dd6b0f5bffe436b230b411f6 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> -Date: Tue, 16 Jun 2015 12:52:07 +0200 -Subject: [PATCH v3 4/6] usb: bcma: use separated function for USB 2.0 - initialization -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This will allow adding USB 3.0 (XHCI) support cleanly. - -Signed-off-by: Rafał Miłecki <zajec5@gmail.com> -Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> ---- - drivers/usb/host/bcma-hcd.c | 51 +++++++++++++++++++++++++++++++-------------- - 1 file changed, 35 insertions(+), 16 deletions(-) - ---- a/drivers/usb/host/bcma-hcd.c -+++ b/drivers/usb/host/bcma-hcd.c -@@ -35,6 +35,7 @@ MODULE_DESCRIPTION("Common USB driver fo - MODULE_LICENSE("GPL"); - - struct bcma_hcd_device { -+ struct bcma_device *core; - struct platform_device *ehci_dev; - struct platform_device *ohci_dev; - struct gpio_desc *gpio_desc; -@@ -288,31 +289,16 @@ err_alloc: - return ERR_PTR(ret); - } - --static int bcma_hcd_probe(struct bcma_device *dev) -+static int bcma_hcd_usb20_init(struct bcma_hcd_device *usb_dev) - { -- int err; -+ struct bcma_device *dev = usb_dev->core; -+ struct bcma_chipinfo *chipinfo = &dev->bus->chipinfo; - u32 ohci_addr; -- struct bcma_hcd_device *usb_dev; -- struct bcma_chipinfo *chipinfo; -- -- chipinfo = &dev->bus->chipinfo; -- -- /* TODO: Probably need checks here; is the core connected? */ -+ int err; - - if (dma_set_mask_and_coherent(dev->dma_dev, DMA_BIT_MASK(32))) - return -EOPNOTSUPP; - -- usb_dev = devm_kzalloc(&dev->dev, sizeof(struct bcma_hcd_device), -- GFP_KERNEL); -- if (!usb_dev) -- return -ENOMEM; -- -- if (dev->dev.of_node) -- usb_dev->gpio_desc = devm_get_gpiod_from_child(&dev->dev, "vcc", -- &dev->dev.of_node->fwnode); -- if (!IS_ERR_OR_NULL(usb_dev->gpio_desc)) -- gpiod_direction_output(usb_dev->gpio_desc, 1); -- - switch (dev->id.id) { - case BCMA_CORE_NS_USB20: - bcma_hcd_init_chip_arm(dev); -@@ -345,7 +331,6 @@ static int bcma_hcd_probe(struct bcma_de - goto err_unregister_ohci_dev; - } - -- bcma_set_drvdata(dev, usb_dev); - return 0; - - err_unregister_ohci_dev: -@@ -353,6 +338,40 @@ err_unregister_ohci_dev: - return err; - } - -+static int bcma_hcd_probe(struct bcma_device *dev) -+{ -+ int err; -+ struct bcma_hcd_device *usb_dev; -+ -+ /* TODO: Probably need checks here; is the core connected? */ -+ -+ usb_dev = devm_kzalloc(&dev->dev, sizeof(struct bcma_hcd_device), -+ GFP_KERNEL); -+ if (!usb_dev) -+ return -ENOMEM; -+ usb_dev->core = dev; -+ -+ if (dev->dev.of_node) -+ usb_dev->gpio_desc = devm_get_gpiod_from_child(&dev->dev, "vcc", -+ &dev->dev.of_node->fwnode); -+ if (!IS_ERR_OR_NULL(usb_dev->gpio_desc)) -+ gpiod_direction_output(usb_dev->gpio_desc, 1); -+ -+ switch (dev->id.id) { -+ case BCMA_CORE_USB20_HOST: -+ case BCMA_CORE_NS_USB20: -+ err = bcma_hcd_usb20_init(usb_dev); -+ if (err) -+ return err; -+ break; -+ default: -+ return -ENODEV; -+ } -+ -+ bcma_set_drvdata(dev, usb_dev); -+ return 0; -+} -+ - static void bcma_hcd_remove(struct bcma_device *dev) - { - struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev); diff --git a/target/linux/bcm53xx/patches-4.3/197-USB-bcma-add-USB-3.0-support.patch b/target/linux/bcm53xx/patches-4.3/197-USB-bcma-add-USB-3.0-support.patch deleted file mode 100644 index 34ab858b4d..0000000000 --- a/target/linux/bcm53xx/patches-4.3/197-USB-bcma-add-USB-3.0-support.patch +++ /dev/null @@ -1,295 +0,0 @@ -From 121ec6539abedbc0e975cf35f48ee044b323e4c3 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> -Date: Tue, 16 Jun 2015 17:14:26 +0200 -Subject: [PATCH v3 5/6] usb: bcma: add USB 3.0 support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Rafał Miłecki <zajec5@gmail.com> -Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> ---- - drivers/usb/host/bcma-hcd.c | 225 ++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 225 insertions(+) - ---- a/drivers/usb/host/bcma-hcd.c -+++ b/drivers/usb/host/bcma-hcd.c -@@ -29,6 +29,7 @@ - #include <linux/of_gpio.h> - #include <linux/usb/ehci_pdriver.h> - #include <linux/usb/ohci_pdriver.h> -+#include <linux/usb/xhci_pdriver.h> - - MODULE_AUTHOR("Hauke Mehrtens"); - MODULE_DESCRIPTION("Common USB driver for BCMA Bus"); -@@ -38,6 +39,7 @@ struct bcma_hcd_device { - struct bcma_device *core; - struct platform_device *ehci_dev; - struct platform_device *ohci_dev; -+ struct platform_device *xhci_dev; - struct gpio_desc *gpio_desc; - }; - -@@ -245,6 +247,10 @@ static const struct usb_ehci_pdata ehci_ - static const struct usb_ohci_pdata ohci_pdata = { - }; - -+static const struct usb_xhci_pdata xhci_pdata = { -+ .usb3_fake_doorbell = 1 -+}; -+ - static struct platform_device *bcma_hcd_create_pdev(struct bcma_device *dev, - const char *name, u32 addr, - const void *data, -@@ -338,6 +344,216 @@ err_unregister_ohci_dev: - return err; - } - -+static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask, -+ u32 value, int timeout) -+{ -+ unsigned long deadline = jiffies + timeout; -+ u32 val; -+ -+ do { -+ val = readl(addr); -+ if ((val & mask) == value) -+ return true; -+ cpu_relax(); -+ udelay(10); -+ } while (!time_after_eq(jiffies, deadline)); -+ -+ pr_err("Timeout waiting for register %p\n", addr); -+ -+ return false; -+} -+ -+static void bcma_hcd_usb30_phy_init(struct bcma_hcd_device *bcma_hcd) -+{ -+ struct bcma_device *core = bcma_hcd->core; -+ struct bcma_bus *bus = core->bus; -+ struct bcma_chipinfo *chipinfo = &bus->chipinfo; -+ struct bcma_drv_cc_b *ccb = &bus->drv_cc_b; -+ struct bcma_device *arm_core; -+ void __iomem *dmu = NULL; -+ u32 cru_straps_ctrl; -+ -+ if (chipinfo->id != BCMA_CHIP_ID_BCM4707 && -+ chipinfo->id != BCMA_CHIP_ID_BCM53018) -+ return; -+ -+ arm_core = bcma_find_core(bus, BCMA_CORE_ARMCA9); -+ if (!arm_core) -+ return; -+ -+ dmu = ioremap_nocache(arm_core->addr_s[0], 0x1000); -+ if (!dmu) -+ goto out; -+ -+ /* Check strapping of PCIE/USB3 SEL */ -+ cru_straps_ctrl = ioread32(dmu + 0x2a0); -+ if ((cru_straps_ctrl & 0x10) == 0) -+ goto out; -+ -+ /* Perform USB3 system soft reset */ -+ bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET); -+ -+ /* Enable MDIO. Setting MDCDIV as 26 */ -+ iowrite32(0x0000009a, ccb->mii + 0x000); -+ udelay(2); -+ -+ switch (chipinfo->id) { -+ case BCMA_CHIP_ID_BCM4707: -+ if (chipinfo->rev == 4) { -+ /* For NS-B0, USB3 PLL Block */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x587e8000, ccb->mii + 0x004); -+ -+ /* Clear ana_pllSeqStart */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x58061000, ccb->mii + 0x004); -+ -+ /* CMOS Divider ratio to 25 */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x582a6400, ccb->mii + 0x004); -+ -+ /* Asserting PLL Reset */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x582ec000, ccb->mii + 0x004); -+ -+ /* Deaaserting PLL Reset */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x582e8000, ccb->mii + 0x004); -+ -+ /* Deasserting USB3 system reset */ -+ bcma_awrite32(core, BCMA_RESET_CTL, 0); -+ -+ /* Set ana_pllSeqStart */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x58069000, ccb->mii + 0x004); -+ -+ /* RXPMD block */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x587e8020, ccb->mii + 0x004); -+ -+ /* CDR int loop locking BW to 1 */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x58120049, ccb->mii + 0x004); -+ -+ /* CDR int loop acquisition BW to 1 */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x580e0049, ccb->mii + 0x004); -+ -+ /* CDR prop loop BW to 1 */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x580a005c, ccb->mii + 0x004); -+ -+ /* Waiting MII Mgt interface idle */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ } else { -+ /* PLL30 block */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x587e8000, ccb->mii + 0x004); -+ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x582a6400, ccb->mii + 0x004); -+ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x587e80e0, ccb->mii + 0x004); -+ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x580a009c, ccb->mii + 0x004); -+ -+ /* Enable SSC */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x587e8040, ccb->mii + 0x004); -+ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x580a21d3, ccb->mii + 0x004); -+ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x58061003, ccb->mii + 0x004); -+ -+ /* Waiting MII Mgt interface idle */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ -+ /* Deasserting USB3 system reset */ -+ bcma_awrite32(core, BCMA_RESET_CTL, 0); -+ } -+ break; -+ case BCMA_CHIP_ID_BCM53018: -+ /* USB3 PLL Block */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x587e8000, ccb->mii + 0x004); -+ -+ /* Assert Ana_Pllseq start */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x58061000, ccb->mii + 0x004); -+ -+ /* Assert CML Divider ratio to 26 */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x582a6400, ccb->mii + 0x004); -+ -+ /* Asserting PLL Reset */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x582ec000, ccb->mii + 0x004); -+ -+ /* Deaaserting PLL Reset */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x582e8000, ccb->mii + 0x004); -+ -+ /* Waiting MII Mgt interface idle */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ -+ /* Deasserting USB3 system reset */ -+ bcma_awrite32(core, BCMA_RESET_CTL, 0); -+ -+ /* PLL frequency monitor enable */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x58069000, ccb->mii + 0x004); -+ -+ /* PIPE Block */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x587e8060, ccb->mii + 0x004); -+ -+ /* CMPMAX & CMPMINTH setting */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x580af30d, ccb->mii + 0x004); -+ -+ /* DEGLITCH MIN & MAX setting */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x580e6302, ccb->mii + 0x004); -+ -+ /* TXPMD block */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x587e8040, ccb->mii + 0x004); -+ -+ /* Enabling SSC */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ iowrite32(0x58061003, ccb->mii + 0x004); -+ -+ /* Waiting MII Mgt interface idle */ -+ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); -+ -+ break; -+ } -+out: -+ if (dmu) -+ iounmap(dmu); -+} -+ -+static int bcma_hcd_usb30_init(struct bcma_hcd_device *bcma_hcd) -+{ -+ struct bcma_device *core = bcma_hcd->core; -+ -+ bcma_core_enable(core, 0); -+ -+ bcma_hcd_usb30_phy_init(bcma_hcd); -+ -+ bcma_hcd->xhci_dev = bcma_hcd_create_pdev(core, "xhci-hcd", core->addr, -+ &xhci_pdata, -+ sizeof(xhci_pdata)); -+ if (IS_ERR(bcma_hcd->ohci_dev)) -+ return PTR_ERR(bcma_hcd->ohci_dev); -+ -+ return 0; -+} -+ - static int bcma_hcd_probe(struct bcma_device *dev) - { - int err; -@@ -364,6 +580,11 @@ static int bcma_hcd_probe(struct bcma_de - if (err) - return err; - break; -+ case BCMA_CORE_NS_USB30: -+ err = bcma_hcd_usb30_init(usb_dev); -+ if (err) -+ return err; -+ break; - default: - return -ENODEV; - } -@@ -377,11 +598,14 @@ static void bcma_hcd_remove(struct bcma_ - struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev); - struct platform_device *ohci_dev = usb_dev->ohci_dev; - struct platform_device *ehci_dev = usb_dev->ehci_dev; -+ struct platform_device *xhci_dev = usb_dev->xhci_dev; - - if (ohci_dev) - platform_device_unregister(ohci_dev); - if (ehci_dev) - platform_device_unregister(ehci_dev); -+ if (xhci_dev) -+ platform_device_unregister(xhci_dev); - - bcma_core_disable(dev, 0); - } -@@ -418,6 +642,7 @@ static int bcma_hcd_resume(struct bcma_d - static const struct bcma_device_id bcma_hcd_table[] = { - BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_USB20_HOST, BCMA_ANY_REV, BCMA_ANY_CLASS), - BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_USB20, BCMA_ANY_REV, BCMA_ANY_CLASS), -+ BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_USB30, BCMA_ANY_REV, BCMA_ANY_CLASS), - {}, - }; - MODULE_DEVICE_TABLE(bcma, bcma_hcd_table); diff --git a/target/linux/bcm53xx/patches-4.3/300-ARM-BCM5301X-Disable-MMU-and-Dcache-for-decompression.patch b/target/linux/bcm53xx/patches-4.3/300-ARM-BCM5301X-Disable-MMU-and-Dcache-for-decompression.patch deleted file mode 100644 index 62bda2e830..0000000000 --- a/target/linux/bcm53xx/patches-4.3/300-ARM-BCM5301X-Disable-MMU-and-Dcache-for-decompression.patch +++ /dev/null @@ -1,86 +0,0 @@ -From: Florian Fainelli <f.fainelli@gmail.com> -Subject: [PATCH] ARM: BCM5301x: Disable MMU and Dcache during decompression -Date: Tue, 14 Jul 2015 16:12:08 -0700 - -Use the existing __armv7_mmu_cache_flush() to perform the cache flush -since this does what we are after. - -Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> ---- - arch/arm/boot/compressed/Makefile | 4 +++ - arch/arm/boot/compressed/head-bcm_5301x-mpcore.S | 37 ++++++++++++++++++++++++ - arch/arm/boot/compressed/head.S | 2 ++ - 3 files changed, 43 insertions(+) - create mode 100644 arch/arm/boot/compressed/head-bcm_5301x-mpcore.S - ---- a/arch/arm/boot/compressed/Makefile -+++ b/arch/arm/boot/compressed/Makefile -@@ -31,6 +31,10 @@ ifeq ($(CONFIG_ARCH_ACORN),y) - OBJS += ll_char_wr.o font.o - endif - -+ifeq ($(CONFIG_ARCH_BCM_5301X),y) -+OBJS += head-bcm_5301x-mpcore.o -+endif -+ - ifeq ($(CONFIG_ARCH_SA1100),y) - OBJS += head-sa1100.o - endif ---- /dev/null -+++ b/arch/arm/boot/compressed/head-bcm_5301x-mpcore.S -@@ -0,0 +1,37 @@ -+/* -+ * -+ * Platform specific tweaks. This is merged into head.S by the linker. -+ * -+ */ -+ -+#include <linux/linkage.h> -+#include <asm/assembler.h> -+#include <asm/cp15.h> -+ -+ .section ".start", "ax" -+ -+/* -+ * This code section is spliced into the head code by the linker -+ */ -+ -+__plat_uncompress_start: -+ -+ @ Preserve r8/r7 i.e. kernel entry values -+ mov r12, r8 -+ -+ @ Clear MMU enable and Dcache enable bits -+ mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR -+ bic r0, #CR_C|CR_M -+ mcr p15, 0, r0, c1, c0, 0 @ Write SCTLR -+ nop -+ -+ @ Call the cache invalidation routine -+ bl __armv7_mmu_cache_flush_fn -+ nop -+ mov r0,#0 -+ ldr r3, =0x19022000 @ L2 cache controller, control reg -+ str r0, [r3, #0x100] @ Disable L2 cache -+ nop -+ -+ @ Restore -+ mov r8, r12 ---- a/arch/arm/boot/compressed/head.S -+++ b/arch/arm/boot/compressed/head.S -@@ -1152,6 +1152,7 @@ __armv7_mmu_cache_flush: - hierarchical: - mcr p15, 0, r10, c7, c10, 5 @ DMB - stmfd sp!, {r0-r7, r9-r11} -+ENTRY(__armv7_mmu_cache_flush_fn) - mrc p15, 1, r0, c0, c0, 1 @ read clidr - ands r3, r0, #0x7000000 @ extract loc from clidr - mov r3, r3, lsr #23 @ left align loc bit field -@@ -1201,6 +1202,7 @@ iflush: - mcr p15, 0, r10, c7, c10, 4 @ DSB - mcr p15, 0, r10, c7, c5, 4 @ ISB - mov pc, lr -+ENDPROC(__armv7_mmu_cache_flush_fn) - - __armv5tej_mmu_cache_flush: - tst r4, #1 diff --git a/target/linux/bcm53xx/patches-4.3/301-ARM-BCM5301X-Add-SPROM.patch b/target/linux/bcm53xx/patches-4.3/301-ARM-BCM5301X-Add-SPROM.patch deleted file mode 100644 index ed6cc73bcc..0000000000 --- a/target/linux/bcm53xx/patches-4.3/301-ARM-BCM5301X-Add-SPROM.patch +++ /dev/null @@ -1,26 +0,0 @@ -From d404e0b22356078a51719fa911f6e09cb1a72d80 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> -Date: Sun, 7 Jun 2015 16:18:18 +0200 -Subject: [PATCH] ARM: BCM5301X: Add SPROM -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Rafał Miłecki <zajec5@gmail.com> ---- - arch/arm/boot/dts/bcm5301x.dtsi | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm/boot/dts/bcm5301x.dtsi -+++ b/arch/arm/boot/dts/bcm5301x.dtsi -@@ -136,6 +136,10 @@ - }; - }; - -+ sprom0: sprom@0 { -+ compatible = "brcm,bcm47xx-sprom"; -+ }; -+ - axi@18000000 { - compatible = "brcm,bus-axi"; - reg = <0x18000000 0x1000>; diff --git a/target/linux/bcm53xx/patches-4.3/305-ARM-BCM5301X-Add-DT-for-Linksys-EA6300-V1.patch b/target/linux/bcm53xx/patches-4.3/305-ARM-BCM5301X-Add-DT-for-Linksys-EA6300-V1.patch deleted file mode 100644 index 82ac24e3fd..0000000000 --- a/target/linux/bcm53xx/patches-4.3/305-ARM-BCM5301X-Add-DT-for-Linksys-EA6300-V1.patch +++ /dev/null @@ -1,69 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> -Subject: [PATCH] ARM: BCM5301X: Add DT for Linksys EA6300 V1 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Rafał Miłecki <zajec5@gmail.com> ---- ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ - bcm4708-asus-rt-ac56u.dtb \ - bcm4708-asus-rt-ac68u.dtb \ - bcm4708-buffalo-wzr-1750dhp.dtb \ -+ bcm4708-linksys-ea6300-v1.dtb \ - bcm4708-luxul-xwc-1000.dtb \ - bcm4708-netgear-r6250.dtb \ - bcm4708-netgear-r6300-v2.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts -@@ -0,0 +1,48 @@ -+/* -+ * Broadcom BCM470X / BCM5301X ARM platform code. -+ * DTS for Linksys EA6300 V1 -+ * -+ * Copyright (C) 2015 Rafał Miłecki <zajec5@gmail.com> -+ * -+ * Licensed under the GNU/GPL. See COPYING for details. -+ */ -+ -+/dts-v1/; -+ -+#include "bcm4708.dtsi" -+#include "bcm5301x-nand-cs0-bch8.dtsi" -+ -+/ { -+ compatible = "linksys,ea6300v1", "brcm,bcm4708"; -+ model = "Linksys EA6300 V1"; -+ -+ chosen { -+ bootargs = "console=ttyS0,115200"; -+ }; -+ -+ memory { -+ reg = <0x00000000 0x08000000>; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ wps { -+ label = "WPS"; -+ linux,code = <KEY_WPS_BUTTON>; -+ gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; -+ }; -+ -+ restart { -+ label = "Reset"; -+ linux,code = <KEY_RESTART>; -+ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; diff --git a/target/linux/bcm53xx/patches-4.3/320-ARM-BCM5301X-Add-Buffalo-WXR-1900DHP-clock-and-USB-p.patch b/target/linux/bcm53xx/patches-4.3/320-ARM-BCM5301X-Add-Buffalo-WXR-1900DHP-clock-and-USB-p.patch deleted file mode 100644 index 802188db17..0000000000 --- a/target/linux/bcm53xx/patches-4.3/320-ARM-BCM5301X-Add-Buffalo-WXR-1900DHP-clock-and-USB-p.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 504dba5b073a9009ae1e3f2fc53ea9c3aa10c38a Mon Sep 17 00:00:00 2001 -From: Felix Fietkau <nbd@openwrt.org> -Date: Wed, 13 May 2015 20:56:38 +0200 -Subject: [PATCH] ARM: BCM5301X: Add Buffalo WXR-1900DHP clock and USB power - control -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Felix Fietkau <nbd@openwrt.org> -Signed-off-by: Rafał Miłecki <zajec5@gmail.com> ---- - arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - ---- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts -+++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts -@@ -24,6 +24,23 @@ - reg = <0x00000000 0x08000000>; - }; - -+ clocks { -+ clk_periph: periph { -+ clock-frequency = <500000000>; -+ }; -+ }; -+ -+ axi@18000000 { -+ usb2@21000 { -+ reg = <0x00021000 0x1000>; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ - leds { - compatible = "gpio-leds"; - diff --git a/target/linux/bcm53xx/patches-4.3/321-ARM-BCM5301X-Set-vcc-gpio-for-USB-controllers.patch b/target/linux/bcm53xx/patches-4.3/321-ARM-BCM5301X-Set-vcc-gpio-for-USB-controllers.patch deleted file mode 100644 index ed4d1bcb03..0000000000 --- a/target/linux/bcm53xx/patches-4.3/321-ARM-BCM5301X-Set-vcc-gpio-for-USB-controllers.patch +++ /dev/null @@ -1,86 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> -Subject: [PATCH] ARM: BCM5301X: Set vcc-gpio for USB controllers -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Rafał Miłecki <zajec5@gmail.com> ---- ---- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts -+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts -@@ -24,6 +24,26 @@ - reg = <0x00000000 0x08000000>; - }; - -+ axi@18000000 { -+ usb2@21000 { -+ reg = <0x00021000 0x1000>; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ usb3@23000 { -+ reg = <0x00023000 0x1000>; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ - spi { - compatible = "spi-gpio"; - num-chipselects = <1>; ---- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts -+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts -@@ -24,6 +24,17 @@ - reg = <0x00000000 0x08000000>; - }; - -+ axi@18000000 { -+ usb3@23000 { -+ reg = <0x00023000 0x1000>; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ - leds { - compatible = "gpio-leds"; - ---- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts -+++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts -@@ -24,6 +24,26 @@ - reg = <0x00000000 0x08000000>; - }; - -+ axi@18000000 { -+ usb2@21000 { -+ reg = <0x00021000 0x1000>; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ usb3@23000 { -+ reg = <0x00023000 0x1000>; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ - leds { - compatible = "gpio-leds"; - diff --git a/target/linux/bcm53xx/patches-4.3/330-ARM-BCM5310X-Enable-earlyprintk-on-tested-devices.patch b/target/linux/bcm53xx/patches-4.3/330-ARM-BCM5310X-Enable-earlyprintk-on-tested-devices.patch deleted file mode 100644 index 4e25647dbb..0000000000 --- a/target/linux/bcm53xx/patches-4.3/330-ARM-BCM5310X-Enable-earlyprintk-on-tested-devices.patch +++ /dev/null @@ -1,170 +0,0 @@ -From eb1075cc48d3c315c7403822c33da9588ab76492 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> -Date: Wed, 14 Jan 2015 08:33:25 +0100 -Subject: [PATCH] ARM: BCM5310X: Enable earlyprintk on tested devices -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Rafał Miłecki <zajec5@gmail.com> ---- - arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 2 +- - arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 2 +- - arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts | 2 +- - arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 2 +- - 4 files changed, 4 insertions(+), 4 deletions(-) - ---- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts -+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts -@@ -17,7 +17,7 @@ - model = "Buffalo WZR-1750DHP (BCM4708)"; - - chosen { -- bootargs = "console=ttyS0,115200"; -+ bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { ---- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts -+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts -@@ -17,7 +17,7 @@ - model = "Netgear R6250 V1 (BCM4708)"; - - chosen { -- bootargs = "console=ttyS0,115200"; -+ bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { ---- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts -+++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts -@@ -17,7 +17,7 @@ - model = "Asus RT-N18U (BCM47081)"; - - chosen { -- bootargs = "console=ttyS0,115200"; -+ bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { ---- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts -+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts -@@ -17,7 +17,7 @@ - model = "Buffalo WZR-600DHP2 (BCM47081)"; - - chosen { -- bootargs = "console=ttyS0,115200"; -+ bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { ---- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts -+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts -@@ -17,7 +17,7 @@ - model = "Buffalo WZR-900DHP (BCM47081)"; - - chosen { -- bootargs = "console=ttyS0,115200"; -+ bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { ---- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts -+++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts -@@ -17,7 +17,7 @@ - model = "Netgear R8000 (BCM4709)"; - - chosen { -- bootargs = "console=ttyS0,115200"; -+ bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { ---- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts -+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts -@@ -17,7 +17,7 @@ - model = "Asus RT-AC56U (BCM4708)"; - - chosen { -- bootargs = "console=ttyS0,115200"; -+ bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { ---- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts -+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts -@@ -17,7 +17,7 @@ - model = "Asus RT-AC68U (BCM4708)"; - - chosen { -- bootargs = "console=ttyS0,115200"; -+ bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { ---- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts -+++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts -@@ -17,7 +17,7 @@ - model = "Luxul XWC-1000 (BCM4708)"; - - chosen { -- bootargs = "console=ttyS0,115200"; -+ bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { ---- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts -+++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts -@@ -17,7 +17,7 @@ - model = "Buffalo WXR-1900DHP"; - - chosen { -- bootargs = "console=ttyS0,115200"; -+ bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { ---- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts -+++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts -@@ -17,7 +17,7 @@ - model = "SmartRG SR400ac"; - - chosen { -- bootargs = "console=ttyS0,115200"; -+ bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { ---- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts -+++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts -@@ -17,7 +17,7 @@ - model = "Asus RT-AC87U"; - - chosen { -- bootargs = "console=ttyS0,115200"; -+ bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { ---- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts -+++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts -@@ -17,7 +17,7 @@ - model = "Netgear R7000"; - - chosen { -- bootargs = "console=ttyS0,115200"; -+ bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { ---- a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts -+++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts -@@ -17,7 +17,7 @@ - model = "Linksys EA6300 V1"; - - chosen { -- bootargs = "console=ttyS0,115200"; -+ bootargs = "console=ttyS0,115200 earlyprintk"; - }; - - memory { diff --git a/target/linux/bcm53xx/patches-4.3/331-ARM-BCM5301X-Specify-RAM-on-devices-by-including-HIG.patch b/target/linux/bcm53xx/patches-4.3/331-ARM-BCM5301X-Specify-RAM-on-devices-by-including-HIG.patch deleted file mode 100644 index b53c57f7d5..0000000000 --- a/target/linux/bcm53xx/patches-4.3/331-ARM-BCM5301X-Specify-RAM-on-devices-by-including-HIG.patch +++ /dev/null @@ -1,173 +0,0 @@ -From 36b2fbb3badf0e32b371e1f7579a95d4fe25c0e1 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> -Date: Wed, 14 Jan 2015 09:13:58 +0100 -Subject: [PATCH] ARM: BCM5301X: Specify RAM on devices by including HIGHMEM -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Rafał Miłecki <zajec5@gmail.com> ---- - arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 3 ++- - arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 3 ++- - arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts | 3 ++- - arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts | 3 ++- - arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 3 ++- - 5 files changed, 10 insertions(+), 5 deletions(-) - ---- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts -+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts -@@ -21,7 +21,8 @@ - }; - - memory { -- reg = <0x00000000 0x08000000>; -+ reg = <0x00000000 0x08000000 -+ 0x88000000 0x18000000>; - }; - - axi@18000000 { ---- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts -+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts -@@ -21,7 +21,8 @@ - }; - - memory { -- reg = <0x00000000 0x08000000>; -+ reg = <0x00000000 0x08000000 -+ 0x88000000 0x08000000>; - }; - - axi@18000000 { ---- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts -+++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts -@@ -21,7 +21,8 @@ - }; - - memory { -- reg = <0x00000000 0x08000000>; -+ reg = <0x00000000 0x08000000 -+ 0x88000000 0x08000000>; - }; - - leds { ---- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts -+++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts -@@ -21,7 +21,8 @@ - }; - - memory { -- reg = <0x00000000 0x08000000>; -+ reg = <0x00000000 0x08000000 -+ 0x88000000 0x08000000>; - }; - - leds { ---- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts -+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts -@@ -21,7 +21,8 @@ - }; - - memory { -- reg = <0x00000000 0x08000000>; -+ reg = <0x00000000 0x08000000 -+ 0x88000000 0x08000000>; - }; - - spi { ---- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts -+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts -@@ -21,7 +21,8 @@ - }; - - memory { -- reg = <0x00000000 0x08000000>; -+ reg = <0x00000000 0x08000000 -+ 0x88000000 0x08000000>; - }; - - gpio-keys { ---- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts -+++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts -@@ -21,7 +21,8 @@ - }; - - memory { -- reg = <0x00000000 0x08000000>; -+ reg = <0x00000000 0x08000000 -+ 0x88000000 0x08000000>; - }; - - axi@18000000 { ---- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts -+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts -@@ -21,7 +21,8 @@ - }; - - memory { -- reg = <0x00000000 0x08000000>; -+ reg = <0x00000000 0x08000000 -+ 0x88000000 0x08000000>; - }; - - leds { ---- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts -+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts -@@ -21,7 +21,8 @@ - }; - - memory { -- reg = <0x00000000 0x08000000>; -+ reg = <0x00000000 0x08000000 -+ 0x88000000 0x08000000>; - }; - - leds { ---- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts -+++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts -@@ -21,7 +21,8 @@ - }; - - memory { -- reg = <0x00000000 0x08000000>; -+ reg = <0x00000000 0x08000000 -+ 0x88000000 0x18000000>; - }; - - clocks { ---- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts -+++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts -@@ -21,7 +21,8 @@ - }; - - memory { -- reg = <0x00000000 0x08000000>; -+ reg = <0x00000000 0x08000000 -+ 0x88000000 0x08000000>; - }; - - leds { ---- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts -+++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts -@@ -21,7 +21,8 @@ - }; - - memory { -- reg = <0x00000000 0x08000000>; -+ reg = <0x00000000 0x08000000 -+ 0x88000000 0x08000000>; - }; - - leds { ---- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts -+++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts -@@ -21,7 +21,8 @@ - }; - - memory { -- reg = <0x00000000 0x08000000>; -+ reg = <0x00000000 0x08000000 -+ 0x88000000 0x08000000>; - }; - - leds { diff --git a/target/linux/bcm53xx/patches-4.3/332-ARM-BCM5301X-Add-power-button-for-Buffalo-WZR-1750DHP.patch b/target/linux/bcm53xx/patches-4.3/332-ARM-BCM5301X-Add-power-button-for-Buffalo-WZR-1750DHP.patch deleted file mode 100644 index f9ca7eb7c1..0000000000 --- a/target/linux/bcm53xx/patches-4.3/332-ARM-BCM5301X-Add-power-button-for-Buffalo-WZR-1750DHP.patch +++ /dev/null @@ -1,20 +0,0 @@ -From: Felix Fietkau <nbd@openwrt.org> -Subject: [PATCH] ARM: BCM5301X: Add power button for Buffalo WZR-1750DHP - -Signed-off-by: Felix Fietkau <nbd@openwrt.org> ---- ---- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts -+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts -@@ -123,6 +123,12 @@ - #address-cells = <1>; - #size-cells = <0>; - -+ power { -+ label = "Power"; -+ linux,code = <KEY_POWER>; -+ gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; -+ }; -+ - restart { - label = "Reset"; - linux,code = <KEY_RESTART>; diff --git a/target/linux/bcm53xx/patches-4.3/351-ARM-BCM5301X-Enable-ChipCommon-UART-on-untested-devi.patch b/target/linux/bcm53xx/patches-4.3/351-ARM-BCM5301X-Enable-ChipCommon-UART-on-untested-devi.patch deleted file mode 100644 index dad4f8a824..0000000000 --- a/target/linux/bcm53xx/patches-4.3/351-ARM-BCM5301X-Enable-ChipCommon-UART-on-untested-devi.patch +++ /dev/null @@ -1,111 +0,0 @@ -From b49d7bb4825654f81bcee8e219028712811515a5 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> -Date: Mon, 29 Jun 2015 08:11:36 +0200 -Subject: [PATCH] ARM: BCM5301X: Enable ChipCommon UART on untested devices -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Rafał Miłecki <zajec5@gmail.com> ---- - arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts | 4 ++++ - arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts | 4 ++++ - arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts | 4 ++++ - arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts | 4 ++++ - arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts | 4 ++++ - arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts | 5 +++++ - arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 5 +++++ - arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 5 +++++ - 8 files changed, 35 insertions(+) - ---- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts -+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts -@@ -96,3 +96,7 @@ - }; - }; - }; -+ -+&uart0 { -+ status = "okay"; -+}; ---- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts -+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts -@@ -83,3 +83,7 @@ - }; - }; - }; -+ -+&uart0 { -+ status = "okay"; -+}; ---- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts -+++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts -@@ -83,3 +83,7 @@ - }; - }; - }; -+ -+&uart0 { -+ status = "okay"; -+}; ---- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts -+++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts -@@ -77,3 +77,7 @@ - }; - }; - }; -+ -+&uart0 { -+ status = "okay"; -+}; ---- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts -+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts -@@ -37,3 +37,7 @@ - }; - }; - }; -+ -+&uart0 { -+ status = "okay"; -+}; ---- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts -+++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts -@@ -65,3 +65,8 @@ - }; - }; - }; -+ -+&uart0 { -+ status = "okay"; -+ clock-frequency = <125000000>; -+}; ---- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts -+++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts -@@ -144,3 +144,8 @@ - }; - }; - }; -+ -+&uart0 { -+ status = "okay"; -+ clock-frequency = <125000000>; -+}; ---- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts -+++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts -@@ -127,3 +127,8 @@ - }; - }; - }; -+ -+&uart0 { -+ status = "okay"; -+ clock-frequency = <125000000>; -+}; ---- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts -+++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts -@@ -104,4 +104,5 @@ - - &uart0 { - status = "okay"; -+ clock-frequency = <125000000>; - }; diff --git a/target/linux/bcm53xx/patches-4.3/404-mtd-bcm53xxspiflash-new-driver-for-SPI-flahes-on-Bro.patch b/target/linux/bcm53xx/patches-4.3/404-mtd-bcm53xxspiflash-new-driver-for-SPI-flahes-on-Bro.patch deleted file mode 100644 index 79af78507c..0000000000 --- a/target/linux/bcm53xx/patches-4.3/404-mtd-bcm53xxspiflash-new-driver-for-SPI-flahes-on-Bro.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/drivers/mtd/spi-nor/Kconfig -+++ b/drivers/mtd/spi-nor/Kconfig -@@ -40,4 +40,10 @@ config SPI_NXP_SPIFI - Flash. Enable this option if you have a device with a SPIFI - controller and want to access the Flash as a mtd device. - -+config MTD_SPI_BCM53XXSPIFLASH -+ tristate "SPI-NOR flashes connected to the Broadcom ARM SoC" -+ depends on MTD_SPI_NOR -+ help -+ SPI driver for flashes used on Broadcom ARM SoCs. -+ - endif # MTD_SPI_NOR ---- a/drivers/mtd/spi-nor/Makefile -+++ b/drivers/mtd/spi-nor/Makefile -@@ -1,3 +1,4 @@ - obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o - obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o -+obj-$(CONFIG_MTD_SPI_BCM53XXSPIFLASH) += bcm53xxspiflash.o - obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o diff --git a/target/linux/bcm53xx/patches-4.3/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch b/target/linux/bcm53xx/patches-4.3/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch deleted file mode 100644 index a3d0f75b48..0000000000 --- a/target/linux/bcm53xx/patches-4.3/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 2a2af518266a29323cf30c3f9ba9ef2ceb1dd84b Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> -Date: Thu, 16 Oct 2014 20:52:16 +0200 -Subject: [PATCH] UBI: Detect EOF mark and erase all remaining blocks -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Rafał Miłecki <zajec5@gmail.com> ---- - drivers/mtd/ubi/attach.c | 5 +++++ - drivers/mtd/ubi/io.c | 4 ++++ - drivers/mtd/ubi/ubi.h | 1 + - 3 files changed, 10 insertions(+) - ---- a/drivers/mtd/ubi/attach.c -+++ b/drivers/mtd/ubi/attach.c -@@ -95,6 +95,9 @@ static int self_check_ai(struct ubi_devi - static struct ubi_ec_hdr *ech; - static struct ubi_vid_hdr *vidh; - -+/* Set on finding block with 0xdeadc0de, indicates erasing all blocks behind */ -+bool erase_all_next; -+ - /** - * add_to_list - add physical eraseblock to a list. - * @ai: attaching information -@@ -1427,6 +1430,8 @@ int ubi_attach(struct ubi_device *ubi, i - if (!ai) - return -ENOMEM; - -+ erase_all_next = false; -+ - #ifdef CONFIG_MTD_UBI_FASTMAP - /* On small flash devices we disable fastmap in any case. */ - if ((int)mtd_div_by_eb(ubi->mtd->size, ubi->mtd) <= UBI_FM_MAX_START) { ---- a/drivers/mtd/ubi/io.c -+++ b/drivers/mtd/ubi/io.c -@@ -755,6 +755,10 @@ int ubi_io_read_ec_hdr(struct ubi_device - } - - magic = be32_to_cpu(ec_hdr->magic); -+ if (magic == 0xdeadc0de) -+ erase_all_next = true; -+ if (erase_all_next) -+ return read_err ? UBI_IO_FF_BITFLIPS : UBI_IO_FF; - if (magic != UBI_EC_HDR_MAGIC) { - if (mtd_is_eccerr(read_err)) - return UBI_IO_BAD_HDR_EBADMSG; ---- a/drivers/mtd/ubi/ubi.h -+++ b/drivers/mtd/ubi/ubi.h -@@ -781,6 +781,7 @@ extern struct mutex ubi_devices_mutex; - extern struct blocking_notifier_head ubi_notifiers; - - /* attach.c */ -+extern bool erase_all_next; - int ubi_add_to_av(struct ubi_device *ubi, struct ubi_attach_info *ai, int pnum, - int ec, const struct ubi_vid_hdr *vid_hdr, int bitflips); - struct ubi_ainf_volume *ubi_find_av(const struct ubi_attach_info *ai, diff --git a/target/linux/bcm53xx/patches-4.3/710-b53-add-hacky-CPU-port-fixes-for-devices-not-using-p.patch b/target/linux/bcm53xx/patches-4.3/710-b53-add-hacky-CPU-port-fixes-for-devices-not-using-p.patch deleted file mode 100644 index dfc422ee3e..0000000000 --- a/target/linux/bcm53xx/patches-4.3/710-b53-add-hacky-CPU-port-fixes-for-devices-not-using-p.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 4abdde3ad6bc0b3b157c4bf6ec0bf139d11d07e8 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> -Date: Wed, 13 May 2015 14:13:28 +0200 -Subject: [PATCH] b53: add hacky CPU port fixes for devices not using port 5 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Rafał Miłecki <zajec5@gmail.com> ---- - drivers/net/phy/b53/b53_common.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/net/phy/b53/b53_common.c -+++ b/drivers/net/phy/b53/b53_common.c -@@ -25,6 +25,7 @@ - #include <linux/module.h> - #include <linux/switch.h> - #include <linux/platform_data/b53.h> -+#include <linux/of.h> - - #include "b53_regs.h" - #include "b53_priv.h" -@@ -1313,6 +1314,18 @@ static int b53_switch_init(struct b53_de - sw_dev->cpu_port = 5; - } - -+ if (of_machine_is_compatible("asus,rt-ac87u")) -+ sw_dev->cpu_port = 7; -+ else if (of_machine_is_compatible("netgear,r8000")) -+ sw_dev->cpu_port = 8; -+ -+ /* -+ * Workaround for devices using port 8 (connected to the 3rd iface). -+ * For some reason it doesn't work (no packets on eth2). -+ */ -+ if (of_machine_is_compatible("netgear,r8000")) -+ sw_dev->cpu_port = 5; -+ - /* cpu port is always last */ - sw_dev->ports = sw_dev->cpu_port + 1; - dev->enabled_ports |= BIT(sw_dev->cpu_port); diff --git a/target/linux/bcm53xx/patches-4.3/901-mtd-bcm47xxpart-workaround-for-Asus-RT-AC87U-asus-pa.patch b/target/linux/bcm53xx/patches-4.3/901-mtd-bcm47xxpart-workaround-for-Asus-RT-AC87U-asus-pa.patch deleted file mode 100644 index 774a186263..0000000000 --- a/target/linux/bcm53xx/patches-4.3/901-mtd-bcm47xxpart-workaround-for-Asus-RT-AC87U-asus-pa.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 21500872c1dba33848ddcf6bea97d58772675d36 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com> -Date: Sun, 17 May 2015 14:00:52 +0200 -Subject: [PATCH] mtd: bcm47xxpart: workaround for Asus RT-AC87U "asus" - partition -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Rafał Miłecki <zajec5@gmail.com> ---- - drivers/mtd/bcm47xxpart.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/drivers/mtd/bcm47xxpart.c -+++ b/drivers/mtd/bcm47xxpart.c -@@ -14,6 +14,7 @@ - #include <linux/slab.h> - #include <linux/mtd/mtd.h> - #include <linux/mtd/partitions.h> -+#include <linux/of.h> - - #include <uapi/linux/magic.h> - -@@ -132,6 +133,17 @@ static int bcm47xxpart_parse(struct mtd_ - break; - } - -+ /* -+ * Ugly workaround for Asus RT-AC87U and its "asus" partition. -+ * It uses JFFS2 which we don't (want to) detect. We should -+ * probably use DT to define partitions but we need a working -+ * TRX firmware splitter first. -+ */ -+ if (of_machine_is_compatible("asus,rt-ac87u") && offset == 0x7ec0000) { -+ bcm47xxpart_add_part(&parts[curr_part++], "asus", offset, MTD_WRITEABLE); -+ continue; -+ } -+ - /* Read beginning of the block */ - err = mtd_read(master, offset, BCM47XXPART_BYTES_TO_READ, - &bytes_read, (uint8_t *)buf); |