diff options
author | Sebastian Schaper <openwrt@sebastianschaper.net> | 2020-12-01 22:34:34 +0100 |
---|---|---|
committer | Adrian Schmutzler <freifunk@adrianschmutzler.de> | 2021-02-09 13:10:33 +0100 |
commit | dc4745da7a3900b5dcd9158d1b83c2cda1d1b9b8 (patch) | |
tree | 502edea49a41024d291b70c4fd65c2d11ac6b61b /target/linux/ath79/dts | |
parent | 82032f350991af08a918f0fcaac81ff82e836d88 (diff) | |
download | upstream-dc4745da7a3900b5dcd9158d1b83c2cda1d1b9b8.tar.gz upstream-dc4745da7a3900b5dcd9158d1b83c2cda1d1b9b8.tar.bz2 upstream-dc4745da7a3900b5dcd9158d1b83c2cda1d1b9b8.zip |
ath79: add support for D-Link DAP-3662 A1
Specifications:
* QCA9557, 16 MiB Flash, 128 MiB RAM, 802.11n 2T2R
* QCA9882, 802.11ac 2T2R
* 2x Gigabit LAN (1x 802.11af PoE)
* IP68 pole-mountable outdoor case
Installation:
* Factory Web UI is at 192.168.0.50
login with 'admin' and blank password, flash factory.bin
* Recovery Web UI is at 192.168.0.50
connect network cable, hold reset button during power-on and keep it
pressed until uploading has started (only required when checksum is ok,
e.g. for reverting back to oem firmware), flash factory.bin
After flashing factory.bin, additional free space can be reclaimed by
flashing sysupgrade.bin, since the factory image requires some padding
to be accepted for upgrading via OEM Web UI.
Both ethernet ports are set to LAN by default, matching the labelling on
the case. However, since both GMAC Interfaces eth0 and eth1 are connected
to the switch (QCA8337), the user may create an additional 'wan' interface
as desired and override the vlan id settings to map br-lan / wan to either
the PoE or non-PoE port, depending on the individual scenario of use.
So, the LAN and WAN ports would then be connected to different GMACs, e.g.
config interface 'lan'
option ifname 'eth0.1'
...
config interface 'wan'
option ifname 'eth1.2'
...
config switch_vlan
option device 'switch0'
option vlan '1'
option ports '1 0t'
config switch_vlan
option device 'switch0'
option vlan '2'
option ports '2 6t'
Signed-off-by: Sebastian Schaper <openwrt@sebastianschaper.net>
[add configuration example]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Diffstat (limited to 'target/linux/ath79/dts')
-rw-r--r-- | target/linux/ath79/dts/qca9558_dlink_dap-3662-a1.dts | 102 |
1 files changed, 102 insertions, 0 deletions
diff --git a/target/linux/ath79/dts/qca9558_dlink_dap-3662-a1.dts b/target/linux/ath79/dts/qca9558_dlink_dap-3662-a1.dts new file mode 100644 index 0000000000..55ac061a56 --- /dev/null +++ b/target/linux/ath79/dts/qca9558_dlink_dap-3662-a1.dts @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qca955x_dlink_dap-2xxx.dtsi" + +/ { + compatible = "dlink,dap-3662-a1", "qca,qca9558"; + model = "D-Link DAP-3662 A1"; + + aliases { + led-boot = &led_power_green; + led-failsafe = &led_power_red; + led-running = &led_power_green; + led-upgrade = &led_power_red; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_power_red: power_red { + label = "red:power"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + }; + + led_power_green: power_green { + label = "green:power"; + gpios = <&gpio 23 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; +}; + +&partitions { + partition@70000 { + label = "firmware"; + reg = <0x70000 0xef0000>; + compatible = "wrg"; + }; + + partition@f60000 { + label = "dlink"; + reg = <0xf60000 0x90000>; + read-only; + }; + + art: partition@ff0000 { + label = "art"; + reg = <0xff0000 0x10000>; + read-only; + }; +}; + +&mdio0 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + + qca,ar8327-initvals = < + 0x04 0x07600000 /* PORT0_PAD_CTRL */ + 0x0c 0x00080080 /* PORT6_PAD_CTRL */ + 0x7c 0x0000007e /* PORT0_STATUS */ + 0x94 0x0000007e /* PORT6_STATUS */ + >; + }; +}; + +ð0 { + status = "okay"; + + phy-handle = <&phy0>; + pll-data = <0x56000000 0x00000101 0x00001616>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +ð1 { + status = "okay"; + + pll-data = <0x03000101 0x00000101 0x00001616>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&pcie0 { + status = "okay"; +}; |