at91: add kernel support for sama7g5 soc

Add kernel support for SAMA7G5 by back-porting mainline kernel patches.
Among SAMA7G5 features could be remembered:
- ARM Cortex-A7
- double data rate multi-port dynamic RAM controller supporting DDR2,
  DDR3, DDR3L, LPDDR2, LPDDR3 up to 533MHz
- peripherals for audio, video processing
- 1 gigabit + 1 megabit Ethernet controllers
- 6 CAN controllers
- trust zone support
- DVFS for CPU
- criptography IPs

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>

1 files changed, 98 insertions, 0 deletions

diff --git a/target/linux/at91/patches-5.10/231-ARM-at91-pm-preload-base-address-of-controllers-in-t.patch b/target/linux/at91/patches-5.10/231-ARM-at91-pm-preload-base-address-of-controllers-in-t.patch
new file mode 100644
index 0000000000..86b07071a4
--- /dev/null
+++ b/target/linux/at91/patches-5.10/231-ARM-at91-pm-preload-base-address-of-controllers-in-t.patch
@@ -0,0 +1,98 @@
+From 6075bbc75e55258a762d618cd459dbe0dd38aff9 Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <claudiu.beznea@microchip.com>
+Date: Thu, 30 Sep 2021 18:42:19 +0300
+Subject: [PATCH 231/247] ARM: at91: pm: preload base address of controllers in
+ tlb
+
+In suspend/resume procedure for AT91 architecture different controllers
+(PMC, SHDWC, RAM, RAM PHY, SFRBU) are accessed to do the proper settings
+for power saving. Commit f0bbf17958e8 ("ARM: at91: pm: add self-refresh
+support for sama7g5") introduced the access to RAMC PHY controller for
+SAMA7G5. The access to this controller is done after RAMC ports are
+closed, thus any TLB walk necessary for RAMC PHY virtual address will
+fail. In the development branch this was not encountered. However, on
+current kernel the issue is reproducible.
+
+To solve the issue the previous mechanism of pre-loading the TLB with
+the RAMC PHY virtual address has been used. However, only the addition
+of this new pre-load breaks the functionality for ARMv5 based
+devices (SAM9X60). This behavior has been encountered previously
+while debugging this code and using the same mechanism for pre-loading
+address for different controllers (e.g. pin controller, the assumption
+being that other requested translations are replaced from TLB).
+
+To solve this new issue the TLB flush + the extension of pre-loading
+the rest of controllers to TLB (e.g. PMC, RAMC) has been added. The
+rest of the controllers should have been pre-loaded previously, anyway.
+
+Fixes: f0bbf17958e8 ("ARM: at91: pm: add self-refresh support for sama7g5")
+Depends-on: e42cbbe5c9a2 ("ARM: at91: pm: group constants and addresses loading")
+Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
+Link: https://lore.kernel.org/r/20210930154219.2214051-4-claudiu.beznea@microchip.com
+---
+ arch/arm/mach-at91/pm_suspend.S | 25 ++++++++++++++++++++++++-
+ 1 file changed, 24 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
+index 34f251fdb743..fdb4f63ecde4 100644
+--- a/arch/arm/mach-at91/pm_suspend.S
++++ b/arch/arm/mach-at91/pm_suspend.S
+@@ -1014,6 +1014,10 @@ ENTRY(at91_pm_suspend_in_sram)
+ 	mov	tmp1, #0
+ 	mcr	p15, 0, tmp1, c7, c10, 4
+ 
++	/* Flush tlb. */
++	mov	r4, #0
++	mcr	p15, 0, r4, c8, c7, 0
++
+ 	ldr	tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]
+ 	str	tmp1, .mckr_offset
+ 	ldr	tmp1, [r0, #PM_DATA_PMC_VERSION]
+@@ -1023,23 +1027,42 @@ ENTRY(at91_pm_suspend_in_sram)
+ 	ldr	tmp1, [r0, #PM_DATA_MODE]
+ 	str	tmp1, .pm_mode
+ 
++	/*
++	 * ldrne below are here to preload their address in the TLB as access
++	 * to RAM may be limited while in self-refresh.
++	 */
+ 	ldr	tmp1, [r0, #PM_DATA_PMC]
+ 	str	tmp1, .pmc_base
++	cmp	tmp1, #0
++	ldrne	tmp2, [tmp1, #0]
++
+ 	ldr	tmp1, [r0, #PM_DATA_RAMC0]
+ 	str	tmp1, .sramc_base
++	cmp	tmp1, #0
++	ldrne	tmp2, [tmp1, #0]
++
+ 	ldr	tmp1, [r0, #PM_DATA_RAMC1]
+ 	str	tmp1, .sramc1_base
++	cmp	tmp1, #0
++	ldrne	tmp2, [tmp1, #0]
++
++#ifndef CONFIG_SOC_SAM_V4_V5
++	/* ldrne below are here to preload their address in the TLB */
+ 	ldr	tmp1, [r0, #PM_DATA_RAMC_PHY]
+ 	str	tmp1, .sramc_phy_base
+-	/* Both ldrne below are here to preload their address in the TLB */
++	cmp	tmp1, #0
++	ldrne	tmp2, [tmp1, #0]
++
+ 	ldr	tmp1, [r0, #PM_DATA_SHDWC]
+ 	str	tmp1, .shdwc
+ 	cmp	tmp1, #0
+ 	ldrne	tmp2, [tmp1, #0]
++
+ 	ldr	tmp1, [r0, #PM_DATA_SFRBU]
+ 	str	tmp1, .sfrbu
+ 	cmp	tmp1, #0
+ 	ldrne	tmp2, [tmp1, #0x10]
++#endif
+ 
+ 	/* Active the self-refresh mode */
+ 	at91_sramc_self_refresh_ena
+-- 
+2.32.0
+