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| author | Gabor Juhos <juhosg@openwrt.org> | 2009-06-11 07:18:05 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2009-06-11 07:18:05 +0000 |
| commit | 31c9a411eb133e7f8154fd73fb2e125029be5a23 (patch) | |
| tree | 693718347800ac81122e97c5e56f4f2e269920a7 /target/linux/ar71xx | |
| parent | 73eee8e1389044dc06c904de4e410572a52ec4aa (diff) | |
| download | upstream-31c9a411eb133e7f8154fd73fb2e125029be5a23.tar.gz upstream-31c9a411eb133e7f8154fd73fb2e125029be5a23.tar.bz2 upstream-31c9a411eb133e7f8154fd73fb2e125029be5a23.zip | |
flush more register writings
SVN-Revision: 16415
Diffstat (limited to 'target/linux/ar71xx')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ar71xx/irq.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c b/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c index 797e6f81a5..7d204fd668 100644 --- a/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c +++ b/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c @@ -113,6 +113,9 @@ static void ar71xx_gpio_irq_unmask(unsigned int irq) irq -= AR71XX_GPIO_IRQ_BASE; ar71xx_gpio_wr(GPIO_REG_INT_ENABLE, ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) | (1 << irq)); + + /* flush write */ + ar71xx_gpio_rr(GPIO_REG_INT_ENABLE); } static void ar71xx_gpio_irq_mask(unsigned int irq) @@ -120,6 +123,9 @@ static void ar71xx_gpio_irq_mask(unsigned int irq) irq -= AR71XX_GPIO_IRQ_BASE; ar71xx_gpio_wr(GPIO_REG_INT_ENABLE, ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) & ~(1 << irq)); + + /* flush write */ + ar71xx_gpio_rr(GPIO_REG_INT_ENABLE); } #if 0 @@ -211,6 +217,9 @@ static void ar71xx_misc_irq_unmask(unsigned int irq) irq -= AR71XX_MISC_IRQ_BASE; ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq)); + + /* flush write */ + ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); } static void ar71xx_misc_irq_mask(unsigned int irq) @@ -218,6 +227,9 @@ static void ar71xx_misc_irq_mask(unsigned int irq) irq -= AR71XX_MISC_IRQ_BASE; ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) & ~(1 << irq)); + + /* flush write */ + ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); } struct irq_chip ar71xx_misc_irq_chip = { |