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| author | Baptiste Jonglez <git@bitsofnetworks.org> | 2020-03-26 19:03:42 +0100 |
|---|---|---|
| committer | Petr Štetiar <ynezz@true.cz> | 2020-03-28 13:46:26 +0100 |
| commit | f5b3cd15395c2617585e36b4acf40999616cc60c (patch) | |
| tree | e9ccfda35d1d23a5922997405763b369961e4eda /target/linux/ar71xx | |
| parent | bdbda30384980ed545391ddf23308ca4bde34770 (diff) | |
| download | upstream-f5b3cd15395c2617585e36b4acf40999616cc60c.tar.gz upstream-f5b3cd15395c2617585e36b4acf40999616cc60c.tar.bz2 upstream-f5b3cd15395c2617585e36b4acf40999616cc60c.zip | |
ar71xx: Fix gigabit switch support for Mikrotik RB951G-2HnD
Without this patch, when using rev 3 of the Atheros AR9344 SoC, the
gigabit switch (AR8327) does not work or works very erratically.
This is a re-spin of http://patchwork.ozlabs.org/patch/419857/ with a
different PLL value, according to the feedback from several users
(including myself) as shown here:
https://openwrt.org/toh/mikrotik/rb2011uias#tracking_reported_experience_with_suggested_patch_for_the_5_gige_ports
Performance is acceptable: testing L3 forwarding without NAT yields a
performance of 370 Mbit/s (iperf3 TCP) and 41 Kpps (iperf3 UDP with 64
bytes payload). Both tests show that 100% of CPU time is spent on softirq.
A similar fix for a different device (RB2011) was added in e457d22261
("Make GBit switch work on RB2011").
Signed-off-by: Baptiste Jonglez <git@bitsofnetworks.org>
(cherry picked from commit 247043c968d22c193055a97a9cdf5baef4aaf96d)
Diffstat (limited to 'target/linux/ar71xx')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c index 33c4f53133..c4cf5f12a8 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c @@ -266,6 +266,7 @@ static void __init rb951g_setup(void) return; ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | + AR934X_ETH_CFG_RXD_DELAY | AR934X_ETH_CFG_SW_ONLY_MODE); ath79_register_mdio(0, 0x0); @@ -276,6 +277,7 @@ static void __init rb951g_setup(void) ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_pll_data.pll_1000 = 0x6f000000; ath79_register_eth(0); |