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| author | Kevin Darbyshire-Bryant <kevin@darbyshire-bryant.me.uk> | 2016-12-16 11:33:38 +0000 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2016-12-20 09:35:36 +0100 |
| commit | 79abb8f140c0081145acc832cbbd65afcdd0176b (patch) | |
| tree | cb15543c2d9908e5d6f5d969eac2252b1c4f6619 /target/linux/ar71xx/patches-4.4 | |
| parent | 6a902108a8da710f5359db82bd8295eed571f0de (diff) | |
| download | upstream-79abb8f140c0081145acc832cbbd65afcdd0176b.tar.gz upstream-79abb8f140c0081145acc832cbbd65afcdd0176b.tar.bz2 upstream-79abb8f140c0081145acc832cbbd65afcdd0176b.zip | |
kernel: bump to 4.4.39
Bump & refresh patches for all 4.4 targets.
Compile & run tested: ar71xx Archer C7 v2
Signed-off-by: Kevin Darbyshire-Bryant <kevin@darbyshire-bryant.me.uk>
Diffstat (limited to 'target/linux/ar71xx/patches-4.4')
3 files changed, 13 insertions, 13 deletions
diff --git a/target/linux/ar71xx/patches-4.4/525-MIPS-ath79-enable-qca-usb-quirks.patch b/target/linux/ar71xx/patches-4.4/525-MIPS-ath79-enable-qca-usb-quirks.patch index 61b6b4ee16..0e33674adf 100644 --- a/target/linux/ar71xx/patches-4.4/525-MIPS-ath79-enable-qca-usb-quirks.patch +++ b/target/linux/ar71xx/patches-4.4/525-MIPS-ath79-enable-qca-usb-quirks.patch @@ -29,9 +29,7 @@ - u32 bootstrap; + void __iomem *phy_reg; + u32 t; - -- bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); -- if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE) ++ + phy_reg = ioremap(base, 4); + if (!phy_reg) + return; @@ -43,7 +41,9 @@ + + iounmap(phy_reg); +} -+ + +- bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); +- if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE) +static void ar934x_usb_reset_notifier(struct platform_device *pdev) +{ + if (pdev->id != -1) diff --git a/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch index c5035778a2..0126f6a3b9 100644 --- a/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch +++ b/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch @@ -155,7 +155,7 @@ +#define AR934X_RESET_LUT BIT(2) +#define AR934X_RESET_MBOX BIT(1) +#define AR934X_RESET_I2S BIT(0) - ++ +#define QCA955X_RESET_HOST BIT(31) +#define QCA955X_RESET_SLIC BIT(30) +#define QCA955X_RESET_HDMA BIT(29) @@ -188,7 +188,7 @@ +#define QCA955X_RESET_LUT BIT(2) +#define QCA955X_RESET_MBOX BIT(1) +#define QCA955X_RESET_I2S BIT(0) -+ + +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) diff --git a/target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch b/target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch index 5d9d802eda..4d7902e166 100644 --- a/target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch +++ b/target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch @@ -135,8 +135,7 @@ +static void __init ap136_common_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); - --static int ap136_pci_plat_dev_init(struct pci_dev *dev) ++ + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio), @@ -151,7 +150,8 @@ + ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); -+ + +-static int ap136_pci_plat_dev_init(struct pci_dev *dev) + ath79_register_mdio(0, 0x0); + ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0); + @@ -211,16 +211,16 @@ + /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */ + ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII; + ap136_ar8327_pad0_cfg.sgmii_delay_en = true; - -- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); -- ath79_register_pci(); ++ + /* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */ + ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII; + ap136_ar8327_pad6_cfg.txclk_delay_en = true; + ap136_ar8327_pad6_cfg.rxclk_delay_en = true; + ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1; + ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2; -+ + +- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); +- ath79_register_pci(); + ath79_eth0_pll_data.pll_1000 = 0x56000000; + ath79_eth1_pll_data.pll_1000 = 0x03000101; + |