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| author | Hauke Mehrtens <hauke@hauke-m.de> | 2016-02-25 21:54:39 +0000 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2016-02-25 21:54:39 +0000 |
| commit | cb04b8d58201f6aa35f99b76ee8b3435beb7a01e (patch) | |
| tree | f6b54298f21d3ba2166fd1621f86390e5c554f1a /target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch | |
| parent | 53814290e7f58f205c74ad1c2f8cedb7e1c2b5ef (diff) | |
| download | upstream-cb04b8d58201f6aa35f99b76ee8b3435beb7a01e.tar.gz upstream-cb04b8d58201f6aa35f99b76ee8b3435beb7a01e.tar.bz2 upstream-cb04b8d58201f6aa35f99b76ee8b3435beb7a01e.zip | |
kernel: update kernel 4.4 to version 4.4.3
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 48783
Diffstat (limited to 'target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch b/target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch index 5d9d802eda..4d7902e166 100644 --- a/target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch +++ b/target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch @@ -135,8 +135,7 @@ +static void __init ap136_common_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); - --static int ap136_pci_plat_dev_init(struct pci_dev *dev) ++ + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio), @@ -151,7 +150,8 @@ + ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); -+ + +-static int ap136_pci_plat_dev_init(struct pci_dev *dev) + ath79_register_mdio(0, 0x0); + ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0); + @@ -211,16 +211,16 @@ + /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */ + ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII; + ap136_ar8327_pad0_cfg.sgmii_delay_en = true; - -- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); -- ath79_register_pci(); ++ + /* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */ + ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII; + ap136_ar8327_pad6_cfg.txclk_delay_en = true; + ap136_ar8327_pad6_cfg.rxclk_delay_en = true; + ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1; + ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2; -+ + +- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); +- ath79_register_pci(); + ath79_eth0_pll_data.pll_1000 = 0x56000000; + ath79_eth1_pll_data.pll_1000 = 0x03000101; + |