diff options
| author | Felix Fietkau <nbd@nbd.name> | 2016-12-08 21:10:50 +0100 |
|---|---|---|
| committer | Felix Fietkau <nbd@nbd.name> | 2016-12-12 10:22:17 +0100 |
| commit | fa04682f213f81840ca17022ca5aa9439bc22f2c (patch) | |
| tree | 7df5bbad4ef622683414f6b1aa4f084845e0fbf3 /target/linux/ar71xx/patches-4.4/104-spi-spi-ath79-support-multiple-internal-chip-select-.patch | |
| parent | 52c7375c134afd204f6ac9d46265f77f7800123c (diff) | |
| download | upstream-fa04682f213f81840ca17022ca5aa9439bc22f2c.tar.gz upstream-fa04682f213f81840ca17022ca5aa9439bc22f2c.tar.bz2 upstream-fa04682f213f81840ca17022ca5aa9439bc22f2c.zip | |
ar71xx: clean up spi controller related patches
Remove various hacks for fast read, un-break device tree support
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Diffstat (limited to 'target/linux/ar71xx/patches-4.4/104-spi-spi-ath79-support-multiple-internal-chip-select-.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-4.4/104-spi-spi-ath79-support-multiple-internal-chip-select-.patch | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-4.4/104-spi-spi-ath79-support-multiple-internal-chip-select-.patch b/target/linux/ar71xx/patches-4.4/104-spi-spi-ath79-support-multiple-internal-chip-select-.patch new file mode 100644 index 0000000000..3c355cd21c --- /dev/null +++ b/target/linux/ar71xx/patches-4.4/104-spi-spi-ath79-support-multiple-internal-chip-select-.patch @@ -0,0 +1,70 @@ +From: Felix Fietkau <nbd@nbd.name> +Date: Fri, 9 Dec 2016 20:09:16 +0100 +Subject: [PATCH] spi: spi-ath79: support multiple internal chip select + lines + +Several devices with multiple flash chips use the internal chip select +lines. Don't assume that chip select 1 and above are GPIO lines. + +Signed-off-by: Felix Fietkau <nbd@nbd.name> +--- + +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -78,14 +78,16 @@ static void ath79_spi_chipselect(struct + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); + } + +- if (spi->chip_select) { ++ if (gpio_is_valid(spi->cs_gpio)) { + /* SPI is normally active-low */ + gpio_set_value(spi->cs_gpio, cs_high); + } else { ++ u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select); ++ + if (cs_high) +- sp->ioc_base |= AR71XX_SPI_IOC_CS0; ++ sp->ioc_base |= cs_bit; + else +- sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; ++ sp->ioc_base &= ~cs_bit; + + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); + } +@@ -118,11 +120,8 @@ static int ath79_spi_setup_cs(struct spi + struct ath79_spi *sp = ath79_spidev_to_sp(spi); + int status; + +- if (spi->chip_select && !gpio_is_valid(spi->cs_gpio)) +- return -EINVAL; +- + status = 0; +- if (spi->chip_select) { ++ if (gpio_is_valid(spi->cs_gpio)) { + unsigned long flags; + + flags = GPIOF_DIR_OUT; +@@ -134,10 +133,12 @@ static int ath79_spi_setup_cs(struct spi + status = gpio_request_one(spi->cs_gpio, flags, + dev_name(&spi->dev)); + } else { ++ u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select); ++ + if (spi->mode & SPI_CS_HIGH) +- sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; ++ sp->ioc_base &= ~cs_bit; + else +- sp->ioc_base |= AR71XX_SPI_IOC_CS0; ++ sp->ioc_base |= cs_bit; + + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); + } +@@ -147,7 +148,7 @@ static int ath79_spi_setup_cs(struct spi + + static void ath79_spi_cleanup_cs(struct spi_device *spi) + { +- if (spi->chip_select) { ++ if (gpio_is_valid(spi->cs_gpio)) { + gpio_free(spi->cs_gpio); + } + } |