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| author | Christian Lamparter <chunkeey@gmail.com> | 2018-09-30 11:40:13 +0200 |
|---|---|---|
| committer | Christian Lamparter <chunkeey@gmail.com> | 2018-12-27 14:36:23 +0100 |
| commit | 32141c183a28a55fd3288397348ca820b77265d3 (patch) | |
| tree | 04e7b6b8c5978a6362a0c519a990ac0441c54a40 /target/linux/apm821xx/patches-4.19/300-fix-atheros-nics-on-apm82181.patch | |
| parent | 96d55f9fd990beed06b79a65100ef7c942dc125d (diff) | |
| download | upstream-32141c183a28a55fd3288397348ca820b77265d3.tar.gz upstream-32141c183a28a55fd3288397348ca820b77265d3.tar.bz2 upstream-32141c183a28a55fd3288397348ca820b77265d3.zip | |
apm821xx: add linux 4.19 apm821xx patches
This patch updates the apm821xx target to use the 4.19 kernel.
4.19 ships with all the crypto4xx driver patches. Furthermore,
the DW-DMA fix for the SATA controller has been backported from
4.20 and integrated.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Diffstat (limited to 'target/linux/apm821xx/patches-4.19/300-fix-atheros-nics-on-apm82181.patch')
| -rw-r--r-- | target/linux/apm821xx/patches-4.19/300-fix-atheros-nics-on-apm82181.patch | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/target/linux/apm821xx/patches-4.19/300-fix-atheros-nics-on-apm82181.patch b/target/linux/apm821xx/patches-4.19/300-fix-atheros-nics-on-apm82181.patch new file mode 100644 index 0000000000..110726d258 --- /dev/null +++ b/target/linux/apm821xx/patches-4.19/300-fix-atheros-nics-on-apm82181.patch @@ -0,0 +1,51 @@ +--- a/arch/powerpc/platforms/4xx/pci.c ++++ b/arch/powerpc/platforms/4xx/pci.c +@@ -1060,15 +1060,24 @@ static int __init apm821xx_pciex_init_po + u32 val; + + /* +- * Do a software reset on PCIe ports. +- * This code is to fix the issue that pci drivers doesn't re-assign +- * bus number for PCIE devices after Uboot +- * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000 +- * PT quad port, SAS LSI 1064E) ++ * Only reset the PHY when no link is currently established. ++ * This is for the Atheros PCIe board which has problems to establish ++ * the link (again) after this PHY reset. All other currently tested ++ * PCIe boards don't show this problem. + */ +- +- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0); +- mdelay(10); ++ val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP); ++ if (!(val & 0x00001000)) { ++ /* ++ * Do a software reset on PCIe ports. ++ * This code is to fix the issue that pci drivers doesn't re-assign ++ * bus number for PCIE devices after Uboot ++ * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000 ++ * PT quad port, SAS LSI 1064E) ++ */ ++ ++ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0); ++ mdelay(10); ++ } + + if (port->endpoint) + val = PTYPE_LEGACY_ENDPOINT << 20; +@@ -1085,9 +1094,12 @@ static int __init apm821xx_pciex_init_po + mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130); + mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006); + +- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000); +- mdelay(50); +- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000); ++ val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP); ++ if (!(val & 0x00001000)) { ++ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000); ++ mdelay(50); ++ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000); ++ } + + mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, + mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | |