diff options
| author | Felix Fietkau <nbd@openwrt.org> | 2007-09-06 16:27:37 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2007-09-06 16:27:37 +0000 |
| commit | 56231056ea784f1cec6450f649b1adaed1f56366 (patch) | |
| tree | 7b130d72d854cde2bcd3af8b11bd0f7be3dbff6a /target/linux/amazon/files/include | |
| parent | e1184aaa1a7a5e5eeef8e072bf0ea98c291be22a (diff) | |
| download | upstream-56231056ea784f1cec6450f649b1adaed1f56366.tar.gz upstream-56231056ea784f1cec6450f649b1adaed1f56366.tar.bz2 upstream-56231056ea784f1cec6450f649b1adaed1f56366.zip | |
strip the kernel version suffix from target directories, except for brcm-2.4 (the -2.4 will be included in the board name here). CONFIG_LINUX_<ver>_<board> becomes CONFIG_TARGET_<board>, same for profiles.
SVN-Revision: 8653
Diffstat (limited to 'target/linux/amazon/files/include')
21 files changed, 6576 insertions, 0 deletions
diff --git a/target/linux/amazon/files/include/asm-mips/amazon/adm6996.h b/target/linux/amazon/files/include/asm-mips/amazon/adm6996.h new file mode 100644 index 0000000000..77cf4b131d --- /dev/null +++ b/target/linux/amazon/files/include/asm-mips/amazon/adm6996.h @@ -0,0 +1,232 @@ +/****************************************************************************** + Copyright (c) 2004, Infineon Technologies. All rights reserved. + + No Warranty + Because the program is licensed free of charge, there is no warranty for + the program, to the extent permitted by applicable law. Except when + otherwise stated in writing the copyright holders and/or other parties + provide the program "as is" without warranty of any kind, either + expressed or implied, including, but not limited to, the implied + warranties of merchantability and fitness for a particular purpose. The + entire risk as to the quality and performance of the program is with + you. should the program prove defective, you assume the cost of all + necessary servicing, repair or correction. + + In no event unless required by applicable law or agreed to in writing + will any copyright holder, or any other party who may modify and/or + redistribute the program as permitted above, be liable to you for + damages, including any general, special, incidental or consequential + damages arising out of the use or inability to use the program + (including but not limited to loss of data or data being rendered + inaccurate or losses sustained by you or third parties or a failure of + the program to operate with any other programs), even if such holder or + other party has been advised of the possibility of such damages. + ****************************************************************************** + Module : ifx_swdrv.h + Date : 2004-09-01 + Description : JoeLin + Remarks: + + *****************************************************************************/ + +#ifndef _ADM_6996_MODULE_H_ +#define _ADM_6996_MODULE_H_ + +#include <asm/amazon/amazon.h> + +#define ifx_printf(x) printk x + +/* command codes */ +#define ADM_SW_SMI_READ 0x02 +#define ADM_SW_SMI_WRITE 0x01 +#define ADM_SW_SMI_START 0x01 + +#define ADM_SW_EEPROM_WRITE 0x01 +#define ADM_SW_EEPROM_WRITE_ENABLE 0x03 +#define ADM_SW_EEPROM_WRITE_DISABLE 0x00 +#define EEPROM_TYPE 8 /* for 93C66 */ + +/* bit masks */ +#define ADM_SW_BIT_MASK_1 0x00000001 +#define ADM_SW_BIT_MASK_2 0x00000002 +#define ADM_SW_BIT_MASK_4 0x00000008 +#define ADM_SW_BIT_MASK_10 0x00000200 +#define ADM_SW_BIT_MASK_16 0x00008000 +#define ADM_SW_BIT_MASK_32 0x80000000 + +/* delay timers */ +#define ADM_SW_MDC_DOWN_DELAY 5 +#define ADM_SW_MDC_UP_DELAY 5 +#define ADM_SW_CS_DELAY 5 + +/* MDIO modes */ +#define ADM_SW_MDIO_OUTPUT 1 +#define ADM_SW_MDIO_INPUT 0 + +#define ADM_SW_MAX_PORT_NUM 5 +#define ADM_SW_MAX_VLAN_NUM 15 + +/* registers */ +#define ADM_SW_PORT0_CONF 0x1 +#define ADM_SW_PORT1_CONF 0x3 +#define ADM_SW_PORT2_CONF 0x5 +#define ADM_SW_PORT3_CONF 0x7 +#define ADM_SW_PORT4_CONF 0x8 +#define ADM_SW_PORT5_CONF 0x9 +#define ADM_SW_VLAN_MODE 0x11 +#define ADM_SW_MAC_LOCK 0x12 +#define ADM_SW_VLAN0_CONF 0x13 +#define ADM_SW_PORT0_PVID 0x28 +#define ADM_SW_PORT1_PVID 0x29 +#define ADM_SW_PORT2_PVID 0x2a +#define ADM_SW_PORT34_PVID 0x2b +#define ADM_SW_PORT5_PVID 0x2c +#define ADM_SW_PHY_RESET 0x2f +#define ADM_SW_MISC_CONF 0x30 +#define ADM_SW_BNDWDH_CTL0 0x31 +#define ADM_SW_BNDWDH_CTL1 0x32 +#define ADM_SW_BNDWDH_CTL_ENA 0x33 + +/* port modes */ +#define ADM_SW_PORT_FLOWCTL 0x1 /* 802.3x flow control */ +#define ADM_SW_PORT_AN 0x2 /* auto negotiation */ +#define ADM_SW_PORT_100M 0x4 /* 100M */ +#define ADM_SW_PORT_FULL 0x8 /* full duplex */ +#define ADM_SW_PORT_TAG 0x10 /* output tag on */ +#define ADM_SW_PORT_DISABLE 0x20 /* disable port */ +#define ADM_SW_PORT_TOS 0x40 /* TOS first */ +#define ADM_SW_PORT_PPRI 0x80 /* port based priority first */ +#define ADM_SW_PORT_MDIX 0x8000 /* auto MDIX on */ +#define ADM_SW_PORT_PVID_SHIFT 10 +#define ADM_SW_PORT_PVID_BITS 4 + +/* VLAN */ +#define ADM_SW_VLAN_PORT0 0x1 +#define ADM_SW_VLAN_PORT1 0x2 +#define ADM_SW_VLAN_PORT2 0x10 +#define ADM_SW_VLAN_PORT3 0x40 +#define ADM_SW_VLAN_PORT4 0x80 +#define ADM_SW_VLAN_PORT5 0x100 + + +/* GPIO 012 enabled, output mode */ +#define GPIO_ENABLEBITS 0x000700f8 + +/* + define AMAZON GPIO port to ADM6996 EEPROM interface + MDIO -> EEDI GPIO 16, AMAZON GPIO P1.0, bi-direction + MDC -> EESK GPIO 17, AMAZON GPIO P1.1, output only + MDCS -> EECS GPIO 18, AMAZON GPIO P1.2, output only + EEDO GPIO 15, AMAZON GPIO P0.15, do not need this one! */ + +#define GPIO_MDIO 1 //P1.0 +#define GPIO_MDC 2 //P1.1 +#define GPIO_MDCS 4 //P1.2 + +//joelin #define GPIO_MDIO 0 +//joelin #define GPIO_MDC 5 /* PORT 0 GPIO5 */ +//joelin #define GPIO_MDCS 6 /* PORT 0 GPIO6 */ + + +#define MDIO_INPUT 0x00000001 +#define MDIO_OUTPUT_EN 0x00010000 + + +/* type definitions */ +typedef unsigned char U8; +typedef unsigned short U16; +typedef unsigned int U32; + +typedef struct _REGRW_ +{ + unsigned int addr; + unsigned int value; + unsigned int mode; +}REGRW, *PREGRW; + +//joelin adm6996i +typedef struct _MACENTRY_ +{ + unsigned char mac_addr[6]; + unsigned long fid:4; + unsigned long portmap:6; + union { + unsigned long age_timer:9; + unsigned long info_ctrl:9; + } ctrl; + unsigned long occupy:1; + unsigned long info_type:1; + unsigned long bad:1; + unsigned long result:3;//000:command ok ,001:all entry used,010:Entry Not found ,011:try next entry ,101:command error + + }MACENTRY, *PMACENTRY; +typedef struct _PROTOCOLFILTER_ +{ + int protocol_filter_num;//[0~7] + int ip_p; //Value Compared with Protocol in IP Heade[7:0] + char action:2;//Action for protocol Filter . +//00 = Protocol Portmap is Default Output Ports. +//01 = Protocol Portmap is 6'b0. +//10 = Protocol Portmap is the CPU port if the incoming port +//is not the CPU port. But if the incoming port is the CPU port, then Type Portmap contains Default Output Ports, excluding the CPU port. + }PROTOCOLFILTER, *PPROTOCOLFILTER; + +//joelin adm6996i + +/* Santosh: for IGMP proxy/snooping */ + +//050614:fchang int adm_process_mac_table_request (unsigned int cmd, struct _MACENTRY_ *mac); +//050614:fchang int adm_process_protocol_filter_request (unsigned int cmd, struct _PROTOCOLFILTER_ *filter); + + +/* IOCTL keys */ +#define KEY_IOCTL_ADM_REGRW 0x01 +#define KEY_IOCTL_ADM_SW_REGRW 0x02 +#define KEY_IOCTL_ADM_SW_PORTSTS 0x03 +#define KEY_IOCTL_ADM_SW_INIT 0x04 +//for adm6996i-start +#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_ADD 0x05 +#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_DEL 0x06 +#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_INIT 0x07 +#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_MORE 0x08 +#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_ADD 0x09 +#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_DEL 0x0a +#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_GET 0x0b + +//adm6996i #define KEY_IOCTL_MAX_KEY 0x05 +#define KEY_IOCTL_MAX_KEY 0x0c +//for adm6996i-end +/* IOCTL MAGIC */ +#define ADM_MAGIC ('a'|'d'|'m'|'t'|'e'|'k') + +/* IOCTL parameters */ +#define ADM_IOCTL_REGRW _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_REGRW, REGRW) +#define ADM_SW_IOCTL_REGRW _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_REGRW, REGRW) +#define ADM_SW_IOCTL_PORTSTS _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_PORTSTS, NULL) +#define ADM_SW_IOCTL_INIT _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_INIT, NULL) + + +//6996i-stat +#define ADM_SW_IOCTL_MACENTRY_ADD _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_ADD,MACENTRY) +#define ADM_SW_IOCTL_MACENTRY_DEL _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_DEL,MACENTRY) +#define ADM_SW_IOCTL_MACENTRY_GET_INIT _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_INIT,MACENTRY) +#define ADM_SW_IOCTL_MACENTRY_GET_MORE _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_MORE,MACENTRY) +#define ADM_SW_IOCTL_FILTER_ADD _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_ADD,PROTOCOLFILTER) +#define ADM_SW_IOCTL_FILTER_DEL _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_DEL,PROTOCOLFILTER) +#define ADM_SW_IOCTL_FILTER_GET _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_GET,PROTOCOLFILTER) + +//6996i-end + + +#define REG_READ 0x0 +#define REG_WRITE 0x1 + +/* undefine symbol */ +#define AMAZON_SW_REG(reg) *((volatile U32*)(reg)) +//#define GPIO0_INPUT_MASK 0 +//#define GPIO_conf0_REG 0x12345678 +//#define GPIO_SET_HI +//#define GPIO_SET_LOW + +#endif +/* _ADM_6996_MODULE_H_ */ diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon.h new file mode 100644 index 0000000000..d28bb418f1 --- /dev/null +++ b/target/linux/amazon/files/include/asm-mips/amazon/amazon.h @@ -0,0 +1,1440 @@ +#ifndef AMAZON_H +#define AMAZON_H +/****************************************************************************** + Copyright (c) 2002, Infineon Technologies. All rights reserved. + + No Warranty + Because the program is licensed free of charge, there is no warranty for + the program, to the extent permitted by applicable law. Except when + otherwise stated in writing the copyright holders and/or other parties + provide the program "as is" without warranty of any kind, either + expressed or implied, including, but not limited to, the implied + warranties of merchantability and fitness for a particular purpose. The + entire risk as to the quality and performance of the program is with + you. should the program prove defective, you assume the cost of all + necessary servicing, repair or correction. + + In no event unless required by applicable law or agreed to in writing + will any copyright holder, or any other party who may modify and/or + redistribute the program as permitted above, be liable to you for + damages, including any general, special, incidental or consequential + damages arising out of the use or inability to use the program + (including but not limited to loss of data or data being rendered + inaccurate or losses sustained by you or third parties or a failure of + the program to operate with any other programs), even if such holder or + other party has been advised of the possibility of such damages. +******************************************************************************/ + +#define amazon_readl(a) readl(((u32*)(a))) +#define amazon_writel(a,b) writel(a, ((u32*)(b))) +#define amazon_writel_masked(a,b,c) writel((readl(((u32*)(a))) & ~b) | (c & b), ((u32*)(a))) + +/* check ADSL link status */ +#define AMAZON_CHECK_LINK + +/***********************************************************************/ +/* Module : WDT register address and bits */ +/***********************************************************************/ + +#define AMAZON_WDT (KSEG1+0x10100900) +/***********************************************************************/ + +/***Reset Request Register***/ +#define AMAZON_RST_REQ ((volatile u32*)(AMAZON_WDT+ 0x0010)) +#define AMAZON_RST_REQ_PLL (1 << 31) +#define AMAZON_RST_REQ_PCI_CORE (1 << 13) +#define AMAZON_RST_REQ_TPE (1 << 12) +#define AMAZON_RST_REQ_AFE (1 << 11) +#define AMAZON_RST_REQ_DMA (1 << 9) +#define AMAZON_RST_REQ_SWITCH (1 << 8) +#define AMAZON_RST_REQ_DFE (1 << 7) +#define AMAZON_RST_REQ_PHY (1 << 5) +#define AMAZON_RST_REQ_PCI (1 << 4) +#define AMAZON_RST_REQ_FPI (1 << 2) +#define AMAZON_RST_REQ_CPU (1 << 1) +#define AMAZON_RST_REQ_HRST (1 << 0) +#define AMAZON_RST_ALL (AMAZON_RST_REQ_PLL \ + |AMAZON_RST_REQ_PCI_CORE \ + |AMAZON_RST_REQ_TPE \ + |AMAZON_RST_REQ_AFE \ + |AMAZON_RST_REQ_DMA \ + |AMAZON_RST_REQ_SWITCH \ + |AMAZON_RST_REQ_DFE \ + |AMAZON_RST_REQ_PHY \ + |AMAZON_RST_REQ_PCI \ + |AMAZON_RST_REQ_FPI \ + |AMAZON_RST_REQ_CPU \ + |AMAZON_RST_REQ_HRST) + +/***Reset Status Register Power On***/ +#define AMAZON_RST_SR ((volatile u32*)(AMAZON_WDT+ 0x0014)) + +/***Watchdog Timer Control Register 0***/ +#define AMAZON_WDT_CON0 ((volatile u32*)(AMAZON_WDT+ 0x0020)) + +/***Watchdog Timer Control Register 1***/ +#define AMAZON_WDT_CON1 ((volatile u32*)(AMAZON_WDT+ 0x0024)) +#define AMAZON_WDT_CON1_WDTDR (1 << 3) +#define AMAZON_WDT_CON1_WDTIR (1 << 2) + +/***Watchdog Timer Status Register***/ +#define AMAZON_WDT_SR ((volatile u32*)(AMAZON_WDT+ 0x0028)) +#define AMAZON_WDT_SR_WDTTIM(value) (((( 1 << 16) - 1) & (value)) << 16) +#define AMAZON_WDT_SR_WDTPR (1 << 5) +#define AMAZON_WDT_SR_WDTTO (1 << 4) +#define AMAZON_WDT_SR_WDTDS (1 << 3) +#define AMAZON_WDT_SR_WDTIS (1 << 2) +#define AMAZON_WDT_SR_WDTOE (1 << 1) +#define AMAZON_WDT_SR_WDTAE (1 << 0) + +/***NMI Status Register***/ +#define AMAZON_WDT_NMISR ((volatile u32*)(AMAZON_WDT+ 0x002C)) +#define AMAZON_WDT_NMISR_NMIWDT (1 << 2) +#define AMAZON_WDT_NMISR_NMIPLL (1 << 1) +#define AMAZON_WDT_NMISR_NMIEXT (1 << 0) + +#define AMAZON_WDT_RST_MON ((volatile u32*)(AMAZON_WDT+ 0x0030)) + +/***********************************************************************/ +/* Module : MCD register address and bits */ +/***********************************************************************/ +#define AMAZON_MCD (KSEG1+0x1F106000) + +/***Manufacturer Identification Register***/ +#define AMAZON_MCD_MANID ((volatile u32*)(AMAZON_MCD+ 0x0024)) +#define AMAZON_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5) + +/***Chip Identification Register***/ +#define AMAZON_MCD_CHIPID ((volatile u32*)(AMAZON_MCD+ 0x0028)) +#define AMAZON_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) +#define AMAZON_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) +#define AMAZON_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1)) +#define AMAZON_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12) +#define AMAZON_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1)) +#define AMAZON_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1) + +#define AMAZON_CHIPID_STANDARD 0x00EB +#define AMAZON_CHIPID_YANGTSE 0x00ED + +/***Redesign Tracing Identification Register***/ +#define AMAZON_MCD_RTID ((volatile u32*)(AMAZON_MCD+ 0x002C)) +#define AMAZON_MCD_RTID_LC (1 << 15) +#define AMAZON_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0) + + +/***********************************************************************/ +/* Module : CGU register address and bits */ +/***********************************************************************/ + +#define AMAZON_CGU (KSEG1+0x1F103000) +/***********************************************************************/ + +/***CGU Clock Divider Select Register***/ +#define AMAZON_CGU_DIV (AMAZON_CGU + 0x0000) +/***CGU PLL0 Status Register***/ +#define AMAZON_CGU_PLL0SR (AMAZON_CGU + 0x0004) +/***CGU PLL1 Status Register***/ +#define AMAZON_CGU_PLL1SR (AMAZON_CGU + 0x0008) +/***CGU Interface Clock Control Register***/ +#define AMAZON_CGU_IFCCR (AMAZON_CGU + 0x000c) +/***CGU Oscillator Control Register***/ +#define AMAZON_CGU_OSCCR (AMAZON_CGU + 0x0010) +/***CGU Memory Clock Delay Register***/ +#define AMAZON_CGU_MCDEL (AMAZON_CGU + 0x0014) +/***CGU CPU Clock Reduction Register***/ +#define AMAZON_CGU_CPUCRD (AMAZON_CGU + 0x0018) +/***CGU Test Register**/ +#define AMAZON_CGU_TST (AMAZON_CGU + 0x003c) + +/***********************************************************************/ +/* Module : PMU register address and bits */ +/***********************************************************************/ + +#define AMAZON_PMU AMAZON_CGU +/***********************************************************************/ + + +/***PMU Power Down Control Register***/ +#define AMAZON_PMU_PWDCR ((volatile u32*)(AMAZON_PMU+ 0x001c)) +#define AMAZON_PMU_PWDCR_TPE (1 << 13) +#define AMAZON_PMU_PWDCR_PLL (1 << 12) +#define AMAZON_PMU_PWDCR_XTAL (1 << 11) +#define AMAZON_PMU_PWDCR_EBU (1 << 10) +#define AMAZON_PMU_PWDCR_DFE (1 << 9) +#define AMAZON_PMU_PWDCR_SPI (1 << 8) +#define AMAZON_PMU_PWDCR_UART (1 << 7) +#define AMAZON_PMU_PWDCR_GPT (1 << 6) +#define AMAZON_PMU_PWDCR_DMA (1 << 5) +#define AMAZON_PMU_PWDCR_PCI (1 << 4) +#define AMAZON_PMU_PWDCR_SW (1 << 3) +#define AMAZON_PMU_PWDCR_IOR (1 << 2) +#define AMAZON_PMU_PWDCR_FPI (1 << 1) +#define AMAZON_PMU_PWDCR_EPHY (1 << 0) + +/***PMU Status Register***/ +#define AMAZON_PMU_SR ((volatile u32*)(AMAZON_PMU+ 0x0020)) +#define AMAZON_PMU_SR_TPE (1 << 13) +#define AMAZON_PMU_SR_PLL (1 << 12) +#define AMAZON_PMU_SR_XTAL (1 << 11) +#define AMAZON_PMU_SR_EBU (1 << 10) +#define AMAZON_PMU_SR_DFE (1 << 9) +#define AMAZON_PMU_SR_SPI (1 << 8) +#define AMAZON_PMU_SR_UART (1 << 7) +#define AMAZON_PMU_SR_GPT (1 << 6) +#define AMAZON_PMU_SR_DMA (1 << 5) +#define AMAZON_PMU_SR_PCI (1 << 4) +#define AMAZON_PMU_SR_SW (1 << 3) +#define AMAZON_PMU_SR_IOR (1 << 2) +#define AMAZON_PMU_SR_FPI (1 << 1) +#define AMAZON_PMU_SR_EPHY (1 << 0) + +/***********************************************************************/ +/* Module : BCU register address and bits */ +/***********************************************************************/ + +#define AMAZON_BCU (KSEG1+0x10100000) +/***********************************************************************/ + + +/***BCU Control Register (0010H)***/ +#define AMAZON_BCU_CON ((volatile u32*)(AMAZON_BCU+ 0x0010)) +#define AMAZON_BCU_CON_SPC(value) (((( 1 << 8) - 1) & (value)) << 24) +#define AMAZON_BCU_CON_SPE (1 << 19) +#define AMAZON_BCU_CON_PSE (1 << 18) +#define AMAZON_BCU_CON_DBG (1 << 16) +#define AMAZON_BCU_CON_TOUT(value) (((( 1 << 16) - 1) & (value)) << 0) + +/***BCU Error Control Capture Register (0020H)***/ +#define AMAZON_BCU_ECON ((volatile u32*)(AMAZON_BCU+ 0x0020)) +#define AMAZON_BCU_ECON_TAG(value) (((( 1 << 4) - 1) & (value)) << 24) +#define AMAZON_BCU_ECON_RDN (1 << 23) +#define AMAZON_BCU_ECON_WRN (1 << 22) +#define AMAZON_BCU_ECON_SVM (1 << 21) +#define AMAZON_BCU_ECON_ACK(value) (((( 1 << 2) - 1) & (value)) << 19) +#define AMAZON_BCU_ECON_ABT (1 << 18) +#define AMAZON_BCU_ECON_RDY (1 << 17) +#define AMAZON_BCU_ECON_TOUT (1 << 16) +#define AMAZON_BCU_ECON_ERRCNT(value) (((( 1 << 16) - 1) & (value)) << 0) +#define AMAZON_BCU_ECON_OPC(value) (((( 1 << 4) - 1) & (value)) << 28) + +/***BCU Error Address Capture Register (0024 H)***/ +#define AMAZON_BCU_EADD ((volatile u32*)(AMAZON_BCU+ 0x0024)) +#define AMAZON_BCU_EADD_FPIADR + +/***BCU Error Data Capture Register (0028H)***/ +#define AMAZON_BCU_EDAT ((volatile u32*)(AMAZON_BCU+ 0x0028)) +#define AMAZON_BCU_EDAT_FPIDAT + +/***********************************************************************/ +/* Module : Switch register address and bits */ +/***********************************************************************/ + +#define AMAZON_SWITCH (KSEG1+0x10106000) +/***********************************************************************/ +#define AMAZON_SW_UN_DEST AMAZON_SWITCH+0x00 /*Unknown destination register*/ +#define AMAZON_SW_VLAN_CTRL AMAZON_SWITCH+0x04 /*VLAN control register*/ +#define AMAZON_SW_PS_CTL AMAZON_SWITCH+0x08 /*port status control register*/ +#define AMAZON_SW_COS_CTL AMAZON_SWITCH+0x0c /*Cos control register*/ +#define AMAZON_SW_VLAN_COS AMAZON_SWITCH+0x10 /*VLAN priority cos mapping register*/ +#define AMAZON_SW_DSCP_COS3 AMAZON_SWITCH+0x14 /*DSCP cos mapping register3*/ +#define AMAZON_SW_DSCP_COS2 AMAZON_SWITCH+0x18 /*DSCP cos mapping register2*/ +#define AMAZON_SW_DSCP_COS1 AMAZON_SWITCH+0x1c /*DSCP cos mapping register1*/ +#define AMAZON_SW_DSCP_COS0 AMAZON_SWITCH+0x20 /*DSCP cos mapping register*/ +#define AMAZON_SW_ARL_CTL AMAZON_SWITCH+0x24 /*ARL control register*/ +#define AMAZON_SW_PKT_LEN AMAZON_SWITCH+0x28 /*packet length register*/ +#define AMAZON_SW_CPU_ACTL AMAZON_SWITCH+0x2c /*CPU control register1*/ +#define AMAZON_SW_DATA1 AMAZON_SWITCH+0x30 /*CPU access control register1*/ +#define AMAZON_SW_DATA2 AMAZON_SWITCH+0x34 /*CPU access control register2*/ +#define AMAZON_SW_P2_PCTL AMAZON_SWITCH+0x38 /*Port2 control register*/ +#define AMAZON_SW_P0_TX_CTL AMAZON_SWITCH+0x3c /*port0 TX control register*/ +#define AMAZON_SW_P1_TX_CTL AMAZON_SWITCH+0x40 /*port 1 TX control register*/ +#define AMAZON_SW_P0_WM AMAZON_SWITCH+0x44 /*port 0 watermark control register*/ +#define AMAZON_SW_P1_WM AMAZON_SWITCH+0x48 /*port 1 watermark control register*/ +#define AMAZON_SW_P2_WM AMAZON_SWITCH+0x4c /*port 2 watermark control register*/ +#define AMAZON_SW_GBL_WM AMAZON_SWITCH+0x50 /*Global watermark register*/ +#define AMAZON_SW_PM_CTL AMAZON_SWITCH+0x54 /*PM control register*/ +#define AMAZON_SW_P2_CTL AMAZON_SWITCH+0x58 /*PMAC control register*/ +#define AMAZON_SW_P2_TX_IPG AMAZON_SWITCH+0x5c /*port2 TX IPG control register*/ +#define AMAZON_SW_P2_RX_IPG AMAZON_SWITCH+0x60 /*prot2 RX IPG control register*/ +#define AMAZON_SW_MDIO_ACC AMAZON_SWITCH+0x64 /*MDIO access register*/ +#define AMAZON_SW_EPHY AMAZON_SWITCH+0x68 /*Ethernet PHY register*/ +#define AMAZON_SW_MDIO_CFG AMAZON_SWITCH+0x6c /*MDIO configuration register*/ +#define AMAZON_SW_P0_RCV_DROP_CNT AMAZON_SWITCH+0x70 /*port0 receive drop counter */ +#define AMAZON_SW_P0_RCV_FRAME_ERR_CNT AMAZON_SWITCH+0x74 /*port0 receive frame error conter*/ +#define AMAZON_SW_P0_TX_COLL_CNT AMAZON_SWITCH+0x78 /*port0 transmit collision counter*/ +#define AMAZON_SW_P0_TX_DROP_CNT AMAZON_SWITCH+0x7c /*port1 transmit drop counter*/ +#define AMAZON_SW_P1_RCV_DROP_CNT AMAZON_SWITCH+0x80 /*port1 receive drop counter*/ +#define AMAZON_SW_P1_RCV_FRAME_ERR_CNT AMAZON_SWITCH+0x84 /*port1 receive error counter*/ +#define AMAZON_SW_P1_TX_COLL_CNT AMAZON_SWITCH+0x88 /*port1 transmit collision counter*/ +#define AMAZON_SW_P1_TX_DROP_CNT AMAZON_SWITCH+0x8c /*port1 transmit drop counter*/ + + + +/***********************************************************************/ +/* Module : SSC register address and bits */ +/***********************************************************************/ +#define AMAZON_SSC_BASE_ADD_0 (KSEG1+0x10100800) + +/*165001:henryhsu:20050603:Source add by Bing Tao*/ + +/*configuration/Status Registers in Bus Clock Domain*/ +#define AMAZON_SSC_CLC ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0000)) +#define AMAZON_SSC_ID ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0008)) +#define AMAZON_SSC_CON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0010)) +#define AMAZON_SSC_STATE ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0014)) +#define AMAZON_SSC_WHBSTATE ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0018)) +#define AMAZON_SSC_TB ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0020)) +#define AMAZON_SSC_RB ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0024)) +#define AMAZON_SSC_FSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0038)) + +/*Configuration/Status Registers in Kernel Clock Domain*/ +#define AMAZON_SSC_PISEL ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0004)) +#define AMAZON_SSC_RXFCON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0030)) +#define AMAZON_SSC_TXFCON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0034)) +#define AMAZON_SSC_BR ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0040)) +#define AMAZON_SSC_BRSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0044)) +#define AMAZON_SSC_SFCON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0060)) +#define AMAZON_SSC_SFSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0064)) +#define AMAZON_SSC_GPOCON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0070)) +#define AMAZON_SSC_GPOSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0074)) +#define AMAZON_SSC_WHBGPOSTAT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0078)) +#define AMAZON_SSC_RXREQ ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0080)) +#define AMAZON_SSC_RXCNT ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x0084)) + +/*DMA Registers in Bus Clock Domain*/ +#define AMAZON_SSC_DMA_CON ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x00ec)) + +/*interrupt Node Registers in Bus Clock Domain*/ +#define AMAZON_SSC_IRNEN ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x00F4)) +#define AMAZON_SSC_IRNICR ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x00FC)) +#define AMAZON_SSC_IRNCR ((volatile u32*)(AMAZON_SSC_BASE_ADD_0+0x00F8)) + +/*165001*/ + +/***********************************************************************/ + + + +/***********************************************************************/ +/* Module : EBU register address and bits */ +/***********************************************************************/ + +#define AMAZON_EBU (KSEG1+0x10105300) +/***********************************************************************/ + + +/***EBU Clock Control Register***/ +#define AMAZON_EBU_CLC ((volatile u32*)(AMAZON_EBU+ 0x0000)) +#define AMAZON_EBU_CLC_DISS (1 << 1) +#define AMAZON_EBU_CLC_DISR (1 << 0) + +/***EBU Global Control Register***/ +#define AMAZON_EBU_CON ((volatile u32*)(AMAZON_EBU+ 0x0010)) +#define AMAZON_EBU_CON_DTACS(value) (((( 1 << 3) - 1) & (value)) << 20) +#define AMAZON_EBU_CON_DTARW(value) (((( 1 << 3) - 1) & (value)) << 16) +#define AMAZON_EBU_CON_TOUTC(value) (((( 1 << 8) - 1) & (value)) << 8) +#define AMAZON_EBU_CON_ARBMODE(value) (((( 1 << 2) - 1) & (value)) << 6) +#define AMAZON_EBU_CON_ARBSYNC (1 << 5) +#define AMAZON_EBU_CON_1 (1 << 3) + +/***EBU Address Select Register 0***/ +#define AMAZON_EBU_ADDSEL0 ((volatile u32*)(AMAZON_EBU+ 0x0020)) +#define AMAZON_EBU_ADDSEL0_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) +#define AMAZON_EBU_ADDSEL0_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) +#define AMAZON_EBU_ADDSEL0_MIRRORE (1 << 1) +#define AMAZON_EBU_ADDSEL0_REGEN (1 << 0) + +/***EBU Address Select Register 1***/ +#define AMAZON_EBU_ADDSEL1 ((volatile u32*)(AMAZON_EBU+ 0x0024)) +#define AMAZON_EBU_ADDSEL1_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) +#define AMAZON_EBU_ADDSEL1_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) +#define AMAZON_EBU_ADDSEL1_MIRRORE (1 << 1) +#define AMAZON_EBU_ADDSEL1_REGEN (1 << 0) + +/***EBU Address Select Register 2***/ +#define AMAZON_EBU_ADDSEL2 ((volatile u32*)(AMAZON_EBU+ 0x0028)) +#define AMAZON_EBU_ADDSEL2_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) +#define AMAZON_EBU_ADDSEL2_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) +#define AMAZON_EBU_ADDSEL2_MIRRORE (1 << 1) +#define AMAZON_EBU_ADDSEL2_REGEN (1 << 0) + +/***EBU Bus Configuration Register 0***/ +#define AMAZON_EBU_BUSCON0 ((volatile u32*)(AMAZON_EBU+ 0x0060)) +#define AMAZON_EBU_BUSCON0_WRDIS (1 << 31) +#define AMAZON_EBU_BUSCON0_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) +#define AMAZON_EBU_BUSCON0_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) +#define AMAZON_EBU_BUSCON0_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) +#define AMAZON_EBU_BUSCON0_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) +#define AMAZON_EBU_BUSCON0_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) +#define AMAZON_EBU_BUSCON0_WAITINV (1 << 19) +#define AMAZON_EBU_BUSCON0_SETUP (1 << 18) +#define AMAZON_EBU_BUSCON0_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) +#define AMAZON_EBU_BUSCON0_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) +#define AMAZON_EBU_BUSCON0_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) +#define AMAZON_EBU_BUSCON0_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) +#define AMAZON_EBU_BUSCON0_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) +#define AMAZON_EBU_BUSCON0_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) + +/***EBU Bus Configuration Register 1***/ +#define AMAZON_EBU_BUSCON1 ((volatile u32*)(AMAZON_EBU+ 0x0064)) +#define AMAZON_EBU_BUSCON1_WRDIS (1 << 31) +#define AMAZON_EBU_BUSCON1_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) +#define AMAZON_EBU_BUSCON1_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) +#define AMAZON_EBU_BUSCON1_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) +#define AMAZON_EBU_BUSCON1_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) +#define AMAZON_EBU_BUSCON1_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) +#define AMAZON_EBU_BUSCON1_WAITINV (1 << 19) +#define AMAZON_EBU_BUSCON1_SETUP (1 << 18) +#define AMAZON_EBU_BUSCON1_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) +#define AMAZON_EBU_BUSCON1_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) +#define AMAZON_EBU_BUSCON1_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) +#define AMAZON_EBU_BUSCON1_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) +#define AMAZON_EBU_BUSCON1_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) +#define AMAZON_EBU_BUSCON1_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) + +/***EBU Bus Configuration Register 2***/ +#define AMAZON_EBU_BUSCON2 ((volatile u32*)(AMAZON_EBU+ 0x0068)) +#define AMAZON_EBU_BUSCON2_WRDIS (1 << 31) +#define AMAZON_EBU_BUSCON2_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) +#define AMAZON_EBU_BUSCON2_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) +#define AMAZON_EBU_BUSCON2_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) +#define AMAZON_EBU_BUSCON2_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) +#define AMAZON_EBU_BUSCON2_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) +#define AMAZON_EBU_BUSCON2_WAITINV (1 << 19) +#define AMAZON_EBU_BUSCON2_SETUP (1 << 18) +#define AMAZON_EBU_BUSCON2_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) +#define AMAZON_EBU_BUSCON2_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) +#define AMAZON_EBU_BUSCON2_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) +#define AMAZON_EBU_BUSCON2_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) +#define AMAZON_EBU_BUSCON2_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) +#define AMAZON_EBU_BUSCON2_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) + +/***********************************************************************/ +/* Module : SDRAM register address and bits */ +/***********************************************************************/ + +#define AMAZON_SDRAM (KSEG1+0x1F800000) +/***********************************************************************/ + + +/***MC Access Error Cause Register***/ +#define AMAZON_SDRAM_MC_ERRCAUSE ((volatile u32*)(AMAZON_SDRAM+ 0x0010)) +#define AMAZON_SDRAM_MC_ERRCAUSE_ERR (1 << 31) +#define AMAZON_SDRAM_MC_ERRCAUSE_PORT(value) (((( 1 << 4) - 1) & (value)) << 16) +#define AMAZON_SDRAM_MC_ERRCAUSE_CAUSE(value) (((( 1 << 2) - 1) & (value)) << 0) +#define AMAZON_SDRAM_MC_ERRCAUSE_Res(value) (((( 1 << NaN) - 1) & (value)) << NaN) + +/***MC Access Error Address Register***/ +#define AMAZON_SDRAM_MC_ERRADDR ((volatile u32*)(AMAZON_SDRAM+ 0x0020)) +#define AMAZON_SDRAM_MC_ERRADDR_ADDR + +/***MC I/O General Purpose Register***/ +#define AMAZON_SDRAM_MC_IOGP ((volatile u32*)(AMAZON_SDRAM+ 0x0100)) +#define AMAZON_SDRAM_MC_IOGP_GPR6(value) (((( 1 << 4) - 1) & (value)) << 28) +#define AMAZON_SDRAM_MC_IOGP_GPR5(value) (((( 1 << 4) - 1) & (value)) << 24) +#define AMAZON_SDRAM_MC_IOGP_GPR4(value) (((( 1 << 4) - 1) & (value)) << 20) +#define AMAZON_SDRAM_MC_IOGP_GPR3(value) (((( 1 << 4) - 1) & (value)) << 16) +#define AMAZON_SDRAM_MC_IOGP_GPR2(value) (((( 1 << 4) - 1) & (value)) << 12) +#define AMAZON_SDRAM_MC_IOGP_CPS (1 << 11) +#define AMAZON_SDRAM_MC_IOGP_CLKDELAY(value) (((( 1 << 3) - 1) & (value)) << 8) +#define AMAZON_SDRAM_MC_IOGP_CLKRAT(value) (((( 1 << 4) - 1) & (value)) << 4) +#define AMAZON_SDRAM_MC_IOGP_RDDEL(value) (((( 1 << 4) - 1) & (value)) << 0) + +/***MC Self Refresh Register***/ +#define AMAZON_SDRAM_MC_SELFRFSH ((volatile u32*)(AMAZON_SDRAM+ 0x01A0)) +#define AMAZON_SDRAM_MC_SELFRFSH_PWDS (1 << 1) +#define AMAZON_SDRAM_MC_SELFRFSH_PWD (1 << 0) +#define AMAZON_SDRAM_MC_SELFRFSH_Res(value) (((( 1 << 30) - 1) & (value)) << 2) + +/***MC Enable Register***/ +#define AMAZON_SDRAM_MC_CTRLENA ((volatile u32*)(AMAZON_SDRAM+ 0x0110)) +#define AMAZON_SDRAM_MC_CTRLENA_ENA (1 << 0) +#define AMAZON_SDRAM_MC_CTRLENA_Res(value) (((( 1 << 31) - 1) & (value)) << 1) + +/***MC Mode Register Setup Code***/ +#define AMAZON_SDRAM_MC_MRSCODE ((volatile u32*)(AMAZON_SDRAM+ 0x0120)) +#define AMAZON_SDRAM_MC_MRSCODE_UMC(value) (((( 1 << 5) - 1) & (value)) << 7) +#define AMAZON_SDRAM_MC_MRSCODE_CL(value) (((( 1 << 3) - 1) & (value)) << 4) +#define AMAZON_SDRAM_MC_MRSCODE_WT (1 << 3) +#define AMAZON_SDRAM_MC_MRSCODE_BL(value) (((( 1 << 3) - 1) & (value)) << 0) + +/***MC Configuration Data-word Width Register***/ +#define AMAZON_SDRAM_MC_CFGDW ((volatile u32*)(AMAZON_SDRAM+ 0x0130)) +#define AMAZON_SDRAM_MC_CFGDW_DW(value) (((( 1 << 4) - 1) & (value)) << 0) +#define AMAZON_SDRAM_MC_CFGDW_Res(value) (((( 1 << 28) - 1) & (value)) << 4) + +/***MC Configuration Physical Bank 0 Register***/ +#define AMAZON_SDRAM_MC_CFGPB0 ((volatile u32*)(AMAZON_SDRAM+ 0x140)) +#define AMAZON_SDRAM_MC_CFGPB0_MCSEN0(value) (((( 1 << 4) - 1) & (value)) << 12) +#define AMAZON_SDRAM_MC_CFGPB0_BANKN0(value) (((( 1 << 4) - 1) & (value)) << 8) +#define AMAZON_SDRAM_MC_CFGPB0_ROWW0(value) (((( 1 << 4) - 1) & (value)) << 4) +#define AMAZON_SDRAM_MC_CFGPB0_COLW0(value) (((( 1 << 4) - 1) & (value)) << 0) +#define AMAZON_SDRAM_MC_CFGPB0_Res(value) (((( 1 << 16) - 1) & (value)) << 16) + +/***MC Latency Register***/ +#define AMAZON_SDRAM_MC_LATENCY ((volatile u32*)(AMAZON_SDRAM+ 0x0180)) +#define AMAZON_SDRAM_MC_LATENCY_TRP(value) (((( 1 << 4) - 1) & (value)) << 16) +#define AMAZON_SDRAM_MC_LATENCY_TRAS(value) (((( 1 << 4) - 1) & (value)) << 12) +#define AMAZON_SDRAM_MC_LATENCY_TRCD(value) (((( 1 << 4) - 1) & (value)) << 8) +#define AMAZON_SDRAM_MC_LATENCY_TDPL(value) (((( 1 << 4) - 1) & (value)) << 4) +#define AMAZON_SDRAM_MC_LATENCY_TDAL(value) (((( 1 << 4) - 1) & (value)) << 0) +#define AMAZON_SDRAM_MC_LATENCY_Res(value) (((( 1 << 12) - 1) & (value)) << 20) + +/***MC Refresh Cycle Time Register***/ +#define AMAZON_SDRAM_MC_TREFRESH ((volatile u32*)(AMAZON_SDRAM+ 0x0190)) +#define AMAZON_SDRAM_MC_TREFRESH_TREF(value) (((( 1 << 13) - 1) & (value)) << 0) +#define AMAZON_SDRAM_MC_TREFRESH_Res(value) (((( 1 << 19) - 1) & (value)) << 13) + +/***********************************************************************/ +/* Module : GPTU register address and bits */ +/***********************************************************************/ + +#define AMAZON_GPTU (KSEG1+0x10100A00) +/***********************************************************************/ + + +/***GPT Clock Control Register***/ +#define AMAZON_GPTU_CLC ((volatile u32*)(AMAZON_GPTU+ 0x0000)) +#define AMAZON_GPTU_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) +#define AMAZON_GPTU_CLC_DISS (1 << 1) +#define AMAZON_GPTU_CLC_DISR (1 << 0) + +/***GPT Timer 3 Control Register***/ +#define AMAZON_GPTU_T3CON ((volatile u32*)(AMAZON_GPTU+ 0x0014)) +#define AMAZON_GPTU_T3CON_T3RDIR (1 << 15) +#define AMAZON_GPTU_T3CON_T3CHDIR (1 << 14) +#define AMAZON_GPTU_T3CON_T3EDGE (1 << 13) +#define AMAZON_GPTU_T3CON_BPS1(value) (((( 1 << 2) - 1) & (value)) << 11) +#define AMAZON_GPTU_T3CON_T3OTL (1 << 10) +#define AMAZON_GPTU_T3CON_T3UD (1 << 7) +#define AMAZON_GPTU_T3CON_T3R (1 << 6) +#define AMAZON_GPTU_T3CON_T3M(value) (((( 1 << 3) - 1) & (value)) << 3) +#define AMAZON_GPTU_T3CON_T3I(value) (((( 1 << 3) - 1) & (value)) << 0) + +/***GPT Write Hardware Modified Timer 3 Control Register +If set and clear bit are written concurrently with 1, the associated bit is not changed.***/ +#define AMAZON_GPTU_WHBT3CON ((volatile u32*)(AMAZON_GPTU+ 0x004C)) +#define AMAZON_GPTU_WHBT3CON_SETT3CHDIR (1 << 15) +#define AMAZON_GPTU_WHBT3CON_CLRT3CHDIR (1 << 14) +#define AMAZON_GPTU_WHBT3CON_SETT3EDGE (1 << 13) +#define AMAZON_GPTU_WHBT3CON_CLRT3EDGE (1 << 12) +#define AMAZON_GPTU_WHBT3CON_SETT3OTL (1 << 11) +#define AMAZON_GPTU_WHBT3CON_CLRT3OTL (1 << 10) + +/***GPT Timer 2 Control Register***/ +#define AMAZON_GPTU_T2CON ((volatile u32*)(AMAZON_GPTU+ 0x0010)) +#define AMAZON_GPTU_T2CON_TxRDIR (1 << 15) +#define AMAZON_GPTU_T2CON_TxCHDIR (1 << 14) +#define AMAZON_GPTU_T2CON_TxEDGE (1 << 13) +#define AMAZON_GPTU_T2CON_TxIRDIS (1 << 12) +#define AMAZON_GPTU_T2CON_TxRC (1 << 9) +#define AMAZON_GPTU_T2CON_TxUD (1 << 7) +#define AMAZON_GPTU_T2CON_TxR (1 << 6) +#define AMAZON_GPTU_T2CON_TxM(value) (((( 1 << 3) - 1) & (value)) << 3) +#define AMAZON_GPTU_T2CON_TxI(value) (((( 1 << 3) - 1) & (value)) << 0) + +/***GPT Timer 4 Control Register***/ +#define AMAZON_GPTU_T4CON ((volatile u32*)(AMAZON_GPTU+ 0x0018)) +#define AMAZON_GPTU_T4CON_TxRDIR (1 << 15) +#define AMAZON_GPTU_T4CON_TxCHDIR (1 << 14) +#define AMAZON_GPTU_T4CON_TxEDGE (1 << 13) +#define AMAZON_GPTU_T4CON_TxIRDIS (1 << 12) +#define AMAZON_GPTU_T4CON_TxRC (1 << 9) +#define AMAZON_GPTU_T4CON_TxUD (1 << 7) +#define AMAZON_GPTU_T4CON_TxR (1 << 6) +#define AMAZON_GPTU_T4CON_TxM(value) (((( 1 << 3) - 1) & (value)) << 3) +#define AMAZON_GPTU_T4CON_TxI(value) (((( 1 << 3) - 1) & (value)) << 0) + +/***GPT Write HW Modified Timer 2 Control Register If set + and clear bit are written concurrently with 1, the associated bit is not changed.***/ +#define AMAZON_GPTU_WHBT2CON ((volatile u32*)(AMAZON_GPTU+ 0x0048)) +#define AMAZON_GPTU_WHBT2CON_SETTxCHDIR (1 << 15) +#define AMAZON_GPTU_WHBT2CON_CLRTxCHDIR (1 << 14) +#define AMAZON_GPTU_WHBT2CON_SETTxEDGE (1 << 13) +#define AMAZON_GPTU_WHBT2CON_CLRTxEDGE (1 << 12) + +/***GPT Write HW Modified Timer 4 Control Register If set + and clear bit are written concurrently with 1, the associated bit is not changed.***/ +#define AMAZON_GPTU_WHBT4CON ((volatile u32*)(AMAZON_GPTU+ 0x0050)) +#define AMAZON_GPTU_WHBT4CON_SETTxCHDIR (1 << 15) +#define AMAZON_GPTU_WHBT4CON_CLRTxCHDIR (1 << 14) +#define AMAZON_GPTU_WHBT4CON_SETTxEDGE (1 << 13) +#define AMAZON_GPTU_WHBT4CON_CLRTxEDGE (1 << 12) + +/***GPT Capture Reload Register***/ +#define AMAZON_GPTU_CAPREL ((volatile u32*)(AMAZON_GPTU+ 0x0030)) +#define AMAZON_GPTU_CAPREL_CAPREL(value) (((( 1 << 16) - 1) & (value)) << 0) + +/***GPT Timer 2 Register***/ +#define AMAZON_GPTU_T2 ((volatile u32*)(AMAZON_GPTU+ 0x0034)) +#define AMAZON_GPTU_T2_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0) + +/***GPT Timer 3 Register***/ +#define AMAZON_GPTU_T3 ((volatile u32*)(AMAZON_GPTU+ 0x0038)) +#define AMAZON_GPTU_T3_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0) + +/***GPT Timer 4 Register***/ +#define AMAZON_GPTU_T4 ((volatile u32*)(AMAZON_GPTU+ 0x003C)) +#define AMAZON_GPTU_T4_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0) + +/***GPT Timer 5 Register***/ +#define AMAZON_GPTU_T5 ((volatile u32*)(AMAZON_GPTU+ 0x0040)) +#define AMAZON_GPTU_T5_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0) + +/***GPT Timer 6 Register***/ +#define AMAZON_GPTU_T6 ((volatile u32*)(AMAZON_GPTU+ 0x0044)) +#define AMAZON_GPTU_T6_TVAL(value) (((( 1 << 16) - 1) & (value)) << 0) + +/***GPT Timer 6 Control Register***/ +#define AMAZON_GPTU_T6CON ((volatile u32*)(AMAZON_GPTU+ 0x0020)) +#define AMAZON_GPTU_T6CON_T6SR (1 << 15) +#define AMAZON_GPTU_T6CON_T6CLR (1 << 14) +#define AMAZON_GPTU_T6CON_BPS2(value) (((( 1 << 2) - 1) & (value)) << 11) +#define AMAZON_GPTU_T6CON_T6OTL (1 << 10) +#define AMAZON_GPTU_T6CON_T6UD (1 << 7) +#define AMAZON_GPTU_T6CON_T6R (1 << 6) +#define AMAZON_GPTU_T6CON_T6M(value) (((( 1 << 3) - 1) & (value)) << 3) +#define AMAZON_GPTU_T6CON_T6I(value) (((( 1 << 3) - 1) & (value)) << 0) + +/***GPT Write HW Modified Timer 6 Control Register If set + and clear bit are written concurrently with 1, the associated bit is not changed.***/ +#define AMAZON_GPTU_WHBT6CON ((volatile u32*)(AMAZON_GPTU+ 0x0054)) +#define AMAZON_GPTU_WHBT6CON_SETT6OTL (1 << 11) +#define AMAZON_GPTU_WHBT6CON_CLRT6OTL (1 << 10) + +/***GPT Timer 5 Control Register***/ +#define AMAZON_GPTU_T5CON ((volatile u32*)(AMAZON_GPTU+ 0x001C)) +#define AMAZON_GPTU_T5CON_T5SC (1 << 15) +#define AMAZON_GPTU_T5CON_T5CLR (1 << 14) +#define AMAZON_GPTU_T5CON_CI(value) (((( 1 << 2) - 1) & (value)) << 12) +#define AMAZON_GPTU_T5CON_T5CC (1 << 11) +#define AMAZON_GPTU_T5CON_CT3 (1 << 10) +#define AMAZON_GPTU_T5CON_T5RC (1 << 9) +#define AMAZON_GPTU_T5CON_T5UDE (1 << 8) +#define AMAZON_GPTU_T5CON_T5UD (1 << 7) +#define AMAZON_GPTU_T5CON_T5R (1 << 6) +#define AMAZON_GPTU_T5CON_T5M(value) (((( 1 << 3) - 1) & (value)) << 3) +#define AMAZON_GPTU_T5CON_T5I(value) (((( 1 << 3) - 1) & (value)) << 0) + + +/***********************************************************************/ +/* Module : ASC register address and bits */ +/***********************************************************************/ + +#define AMAZON_ASC (KSEG1+0x10100400) +/***********************************************************************/ + + +/***ASC Port Input Select Register***/ +#define AMAZON_ASC_PISEL (AMAZON_ASC+ 0x0004) +#define AMAZON_ASC_PISEL_RIS (1 << 0) + +/***ASC Control Register***/ +#define AMAZON_ASC_CON (AMAZON_ASC+ 0x0010) +#define AMAZON_ASC_CON_R (1 << 15) +#define AMAZON_ASC_CON_LB (1 << 14) +#define AMAZON_ASC_CON_BRS (1 << 13) +#define AMAZON_ASC_CON_ODD (1 << 12) +#define AMAZON_ASC_CON_FDE (1 << 11) +#define AMAZON_ASC_CON_OE (1 << 10) +#define AMAZON_ASC_CON_FE (1 << 9) +#define AMAZON_ASC_CON_PE (1 << 8) +#define AMAZON_ASC_CON_OEN (1 << 7) +#define AMAZON_ASC_CON_FEN (1 << 6) +#define AMAZON_ASC_CON_PENRXDI (1 << 5) +#define AMAZON_ASC_CON_REN (1 << 4) +#define AMAZON_ASC_CON_STP (1 << 3) +#define AMAZON_ASC_CON_M(value) (((( 1 << 3) - 1) & (value)) << 0) + +/***ASC Write Hardware Modified Control Register***/ +#define AMAZON_ASC_WHBCON (AMAZON_ASC+ 0x0050) +#define AMAZON_ASC_WHBCON_SETOE (1 << 13) +#define AMAZON_ASC_WHBCON_SETFE (1 << 12) +#define AMAZON_ASC_WHBCON_SETPE (1 << 11) +#define AMAZON_ASC_WHBCON_CLROE (1 << 10) +#define AMAZON_ASC_WHBCON_CLRFE (1 << 9) +#define AMAZON_ASC_WHBCON_CLRPE (1 << 8) +#define AMAZON_ASC_WHBCON_SETREN (1 << 5) +#define AMAZON_ASC_WHBCON_CLRREN (1 << 4) + +/***ASC Baudrate Timer/Reload Register***/ +#define AMAZON_ASC_BTR (AMAZON_ASC+ 0x0014) +#define AMAZON_ASC_BTR_BR_VALUE(value) (((( 1 << 13) - 1) & (value)) << 0) + +/***ASC Fractional Divider Register***/ +#define AMAZON_ASC_FDV (AMAZON_ASC+ 0x0018) +#define AMAZON_ASC_FDV_FD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) + +/***ASC IrDA Pulse Mode/Width Register***/ +#define AMAZON_ASC_PMW (AMAZON_ASC+ 0x001C) +#define AMAZON_ASC_PMW_IRPW (1 << 8) +#define AMAZON_ASC_PMW_PW_VALUE(value) (((( 1 << 8) - 1) & (value)) << 0) + +/***ASC Transmit Buffer Register***/ +#define AMAZON_ASC_TBUF (AMAZON_ASC+ 0x0020) +#define AMAZON_ASC_TBUF_TD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) + +/***ASC Receive Buffer Register***/ +#define AMAZON_ASC_RBUF (AMAZON_ASC+ 0x0024) +#define AMAZON_ASC_RBUF_RD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) + +/***ASC Autobaud Control Register***/ +#define AMAZON_ASC_ABCON (AMAZON_ASC+ 0x0030) +#define AMAZON_ASC_ABCON_RXINV (1 << 11) +#define AMAZON_ASC_ABCON_TXINV (1 << 10) +#define AMAZON_ASC_ABCON_ABEM(value) (((( 1 << 2) - 1) & (value)) << 8) +#define AMAZON_ASC_ABCON_FCDETEN (1 << 4) +#define AMAZON_ASC_ABCON_ABDETEN (1 << 3) +#define AMAZON_ASC_ABCON_ABSTEN (1 << 2) +#define AMAZON_ASC_ABCON_AUREN (1 << 1) +#define AMAZON_ASC_ABCON_ABEN (1 << 0) + +/***Receive FIFO Control Register***/ +#define AMAZON_ASC_RXFCON (AMAZON_ASC+ 0x0040) +#define AMAZON_ASC_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) +#define AMAZON_ASC_RXFCON_RXTMEN (1 << 2) +#define AMAZON_ASC_RXFCON_RXFFLU (1 << 1) +#define AMAZON_ASC_RXFCON_RXFEN (1 << 0) + +/***Transmit FIFO Control Register***/ +#define AMAZON_ASC_TXFCON (AMAZON_ASC+ 0x0044) +#define AMAZON_ASC_TXFCON_TXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) +#define AMAZON_ASC_TXFCON_TXTMEN (1 << 2) +#define AMAZON_ASC_TXFCON_TXFFLU (1 << 1) +#define AMAZON_ASC_TXFCON_TXFEN (1 << 0) + +/***FIFO Status Register***/ +#define AMAZON_ASC_FSTAT (AMAZON_ASC+ 0x0048) +#define AMAZON_ASC_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8) +#define AMAZON_ASC_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0) + +/***ASC Write HW Modified Autobaud Control Register***/ +#define AMAZON_ASC_WHBABCON (AMAZON_ASC+ 0x0054) +#define AMAZON_ASC_WHBABCON_SETABEN (1 << 1) +#define AMAZON_ASC_WHBABCON_CLRABEN (1 << 0) + +/***ASC Autobaud Status Register***/ +#define AMAZON_ASC_ABSTAT (AMAZON_ASC+ 0x0034) +#define AMAZON_ASC_ABSTAT_DETWAIT (1 << 4) +#define AMAZON_ASC_ABSTAT_SCCDET (1 << 3) +#define AMAZON_ASC_ABSTAT_SCSDET (1 << 2) +#define AMAZON_ASC_ABSTAT_FCCDET (1 << 1) +#define AMAZON_ASC_ABSTAT_FCSDET (1 << 0) + +/***ASC Write HW Modified Autobaud Status Register***/ +#define AMAZON_ASC_WHBABSTAT (AMAZON_ASC+ 0x0058) +#define AMAZON_ASC_WHBABSTAT_SETDETWAIT (1 << 9) +#define AMAZON_ASC_WHBABSTAT_CLRDETWAIT (1 << 8) +#define AMAZON_ASC_WHBABSTAT_SETSCCDET (1 << 7) +#define AMAZON_ASC_WHBABSTAT_CLRSCCDET (1 << 6) +#define AMAZON_ASC_WHBABSTAT_SETSCSDET (1 << 5) +#define AMAZON_ASC_WHBABSTAT_CLRSCSDET (1 << 4) +#define AMAZON_ASC_WHBABSTAT_SETFCCDET (1 << 3) +#define AMAZON_ASC_WHBABSTAT_CLRFCCDET (1 << 2) +#define AMAZON_ASC_WHBABSTAT_SETFCSDET (1 << 1) +#define AMAZON_ASC_WHBABSTAT_CLRFCSDET (1 << 0) + +/***ASC Clock Control Register***/ +#define AMAZON_ASC_CLC (AMAZON_ASC+ 0x0000) +#define AMAZON_ASC_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) +#define AMAZON_ASC_CLC_DISS (1 << 1) +#define AMAZON_ASC_CLC_DISR (1 << 0) + +/***ASC IRNCR0 **/ +#define AMAZON_ASC_IRNCR0 (AMAZON_ASC+ 0x00FC) +/***ASC IRNCR1 **/ +#define AMAZON_ASC_IRNCR1 (AMAZON_ASC+ 0x00F8) +#define ASC_IRNCR_TIR 0x1 +#define ASC_IRNCR_RIR 0x2 +#define ASC_IRNCR_EIR 0x4 +/***********************************************************************/ +/* Module : DMA register address and bits */ +/***********************************************************************/ + +#define AMAZON_DMA (KSEG1+0x10103000) +/***********************************************************************/ +#define AMAZON_DMA_CH_ON AMAZON_DMA+0x28 +#define AMAZON_DMA_CH_RST AMAZON_DMA+0x2c +#define AMAZON_DMA_CH0_ISR AMAZON_DMA+0x30 +#define AMAZON_DMA_CH1_ISR AMAZON_DMA+0x34 +#define AMAZON_DMA_CH2_ISR AMAZON_DMA+0x38 +#define AMAZON_DMA_CH3_ISR AMAZON_DMA+0x3c +#define AMAZON_DMA_CH4_ISR AMAZON_DMA+0x40 +#define AMAZON_DMA_CH5_ISR AMAZON_DMA+0x44 +#define AMAZON_DMA_CH6_ISR AMAZON_DMA+0x48 +#define AMAZON_DMA_CH7_ISR AMAZON_DMA+0x4c +#define AMAZON_DMA_CH8_ISR AMAZON_DMA+0x50 +#define AMAZON_DMA_CH9_ISR AMAZON_DMA+0x54 +#define AMAZON_DMA_CH10_ISR AMAZON_DMA+0x58 +#define AMAZON_DMA_CH11_ISR AMAZON_DMA+0x5c +#define AMAZON_DMA_CH0_MSK AMAZON_DMA+0x60 +#define AMAZON_DMA_CH1_MSK AMAZON_DMA+0x64 +#define AMAZON_DMA_CH2_MSK AMAZON_DMA+0x68 +#define AMAZON_DMA_CH3_MSK AMAZON_DMA+0x6c +#define AMAZON_DMA_CH4_MSK AMAZON_DMA+0x70 +#define AMAZON_DMA_CH5_MSK AMAZON_DMA+0x74 +#define AMAZON_DMA_CH6_MSK AMAZON_DMA+0x78 +#define AMAZON_DMA_CH7_MSK AMAZON_DMA+0x7c +#define AMAZON_DMA_CH8_MSK AMAZON_DMA+0x80 +#define AMAZON_DMA_CH9_MSK AMAZON_DMA+0x84 +#define AMAZON_DMA_CH10_MSK AMAZON_DMA+0x88 +#define AMAZON_DMA_CH11_MSK AMAZON_DMA+0x8c +#define AMAZON_DMA_Desc_BA AMAZON_DMA+0x90 +#define AMAZON_DMA_CH0_DES_LEN AMAZON_DMA+0x94 +#define AMAZON_DMA_CH1_DES_LEN AMAZON_DMA+0x98 +#define AMAZON_DMA_CH2_DES_LEN AMAZON_DMA+0x9c +#define AMAZON_DMA_CH3_DES_LEN AMAZON_DMA+0xa0 +#define AMAZON_DMA_CH4_DES_LEN AMAZON_DMA+0xa4 +#define AMAZON_DMA_CH5_DES_LEN AMAZON_DMA+0xa8 +#define AMAZON_DMA_CH6_DES_LEN AMAZON_DMA+0xac +#define AMAZON_DMA_CH7_DES_LEN AMAZON_DMA+0xb0 +#define AMAZON_DMA_CH8_DES_LEN AMAZON_DMA+0xb4 +#define AMAZON_DMA_CH9_DES_LEN AMAZON_DMA+0xb8 +#define AMAZON_DMA_CH10_DES_LEN AMAZON_DMA+0xbc +#define AMAZON_DMA_CH11_DES_LEN AMAZON_DMA+0xc0 +#define AMAZON_DMA_CH1_DES_OFST AMAZON_DMA+0xc4 +#define AMAZON_DMA_CH2_DES_OFST AMAZON_DMA+0xc8 +#define AMAZON_DMA_CH3_DES_OFST AMAZON_DMA+0xcc +#define AMAZON_DMA_CH4_DES_OFST AMAZON_DMA+0xd0 +#define AMAZON_DMA_CH5_DES_OFST AMAZON_DMA+0xd4 +#define AMAZON_DMA_CH6_DES_OFST AMAZON_DMA+0xd8 +#define AMAZON_DMA_CH7_DES_OFST AMAZON_DMA+0xdc +#define AMAZON_DMA_CH8_DES_OFST AMAZON_DMA+0xe0 +#define AMAZON_DMA_CH9_DES_OFST AMAZON_DMA+0xe4 +#define AMAZON_DMA_CH10_DES_OFST AMAZON_DMA+0xe8 +#define AMAZON_DMA_CH11_DES_OFST AMAZON_DMA+0xec +#define AMAZON_DMA_SW_BL AMAZON_DMA+0xf0 +#define AMAZON_DMA_TPE_BL AMAZON_DMA+0xf4 +#define AMAZON_DMA_DPlus2FPI_BL AMAZON_DMA+0xf8 +#define AMAZON_DMA_GRX_BUF_LEN AMAZON_DMA+0xfc +#define AMAZON_DMA_DMA_ECON_REG AMAZON_DMA+0x100 +#define AMAZON_DMA_POLLING_REG AMAZON_DMA+0x104 +#define AMAZON_DMA_CH_WGT AMAZON_DMA+0x108 +#define AMAZON_DMA_TX_WGT AMAZON_DMA+0x10c +#define AMAZON_DMA_DPLus2FPI_CLASS AMAZON_DMA+0x110 +#define AMAZON_DMA_COMB_ISR AMAZON_DMA+0x114 + +//channel reset +#define SWITCH1_RST_MASK 0x83 /* Switch1 channel mask */ +#define SWITCH2_RST_MASK 0x10C /* Switch1 channel mask */ +#define TPE_RST_MASK 0x630 /* TPE channel mask */ +#define DPlus2FPI_RST_MASK 0x840 /* DPlusFPI channel mask */ + +//ISR +#define DMA_ISR_RDERR 0x20 +#define DMA_ISR_CMDCPT 0x10 +#define DMA_ISR_CPT 0x8 +#define DMA_ISR_DURR 0x4 +#define DMA_ISR_EOP 0x2 +#define DMA_DESC_BYTEOFF_SHIFT 23 + +#define DMA_POLLING_ENABLE 0x80000000 +#define DMA_POLLING_CNT 0x50 /*minimum 0x10, max 0xfff0*/ + +/***********************************************************************/ +/* Module : Debug register address and bits */ +/***********************************************************************/ + +#define AMAZON_DEBUG (KSEG1+0x1F106000) +/***********************************************************************/ + + +/***MCD Break System Control Register***/ +#define AMAZON_DEBUG_MCD_BSCR ((volatile u32*)(AMAZON_DEBUG+ 0x0000)) + +/***PMC Performance Counter Control Register0***/ +#define AMAZON_DEBUG_PMC_PCCR0 ((volatile u32*)(AMAZON_DEBUG+ 0x0010)) + +/***PMC Performance Counter Control Register1***/ +#define AMAZON_DEBUG_PMC_PCCR1 ((volatile u32*)(AMAZON_DEBUG+ 0x0014)) + +/***PMC Performance Counter Register0***/ +#define AMAZON_DEBUG_PMC_PCR0 ((volatile u32*)(AMAZON_DEBUG+ 0x0018)) + +/*165001:henryhsu:20050603:Source modified by Bing Tao*/ + +/***PMC Performance Counter Register1***/ +//#define AMAZON_DEBUG_PMC_PCR1 ((volatile u32*)(AMAZON_DEBUG+ 0x0020)) +#define AMAZON_DEBUG_PMC_PCR1 ((volatile u32*)(AMAZON_DEBUG+ 0x001c)) + +/*165001*/ + + + +/***MCD Suspend Mode Control Register***/ +#define AMAZON_DEBUG_MCD_SMCR ((volatile u32*)(AMAZON_DEBUG+ 0x0024)) + +/***********************************************************************/ +/* Module : GPIO register address and bits */ +/***********************************************************************/ + +#define AMAZON_GPIO (KSEG1+0x10100B00) +/***********************************************************************/ + + +/***Port 0 Data Output Register (0010H)***/ +#define AMAZON_GPIO_P0_OUT ((volatile u32*)(AMAZON_GPIO+ 0x0010)) + +/***Port 1 Data Output Register (0040H)***/ +#define AMAZON_GPIO_P1_OUT ((volatile u32*)(AMAZON_GPIO+ 0x0040)) + +/***Port 0 Data Input Register (0014H)***/ +#define AMAZON_GPIO_P0_IN ((volatile u32*)(AMAZON_GPIO+ 0x0014)) + +/***Port 1 Data Input Register (0044H)***/ +#define AMAZON_GPIO_P1_IN ((volatile u32*)(AMAZON_GPIO+ 0x0044)) + +/***Port 0 Direction Register (0018H)***/ +#define AMAZON_GPIO_P0_DIR ((volatile u32*)(AMAZON_GPIO+ 0x0018)) + +/***Port 1 Direction Register (0048H)***/ +#define AMAZON_GPIO_P1_DIR ((volatile u32*)(AMAZON_GPIO+ 0x0048)) + +/***Port 0 Alternate Function Select Register 0 (001C H) ***/ +#define AMAZON_GPIO_P0_ALTSEL0 ((volatile u32*)(AMAZON_GPIO+ 0x001C)) + +/***Port 1 Alternate Function Select Register 0 (004C H) ***/ +#define AMAZON_GPIO_P1_ALTSEL0 ((volatile u32*)(AMAZON_GPIO+ 0x004C)) + +/***Port 0 Alternate Function Select Register 1 (0020 H) ***/ +#define AMAZON_GPIO_P0_ALTSEL1 ((volatile u32*)(AMAZON_GPIO+ 0x0020)) + +/***Port 1 Alternate Function Select Register 0 (0050 H) ***/ +#define AMAZON_GPIO_P1_ALTSEL1 ((volatile u32*)(AMAZON_GPIO+ 0x0050)) + +/***Port 0 Open Drain Control Register (0024H)***/ +#define AMAZON_GPIO_P0_OD ((volatile u32*)(AMAZON_GPIO+ 0x0024)) + +/***Port 1 Open Drain Control Register (0054H)***/ +#define AMAZON_GPIO_P1_OD ((volatile u32*)(AMAZON_GPIO+ 0x0054)) + +/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/ +#define AMAZON_GPIO_P0_STOFF ((volatile u32*)(AMAZON_GPIO+ 0x0028)) + +/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/ +#define AMAZON_GPIO_P1_STOFF ((volatile u32*)(AMAZON_GPIO+ 0x0058)) + +/***Port 0 Pull Up/Pull Down Select Register (002C H)***/ +#define AMAZON_GPIO_P0_PUDSEL ((volatile u32*)(AMAZON_GPIO+ 0x002C)) + +/***Port 1 Pull Up/Pull Down Select Register (005C H)***/ +#define AMAZON_GPIO_P1_PUDSEL ((volatile u32*)(AMAZON_GPIO+ 0x005C)) + +/***Port 0 Pull Up Device Enable Register (0030 H)***/ +#define AMAZON_GPIO_P0_PUDEN ((volatile u32*)(AMAZON_GPIO+ 0x0030)) + +/***Port 1 Pull Up Device Enable Register (0060 H)***/ +#define AMAZON_GPIO_P1_PUDEN ((volatile u32*)(AMAZON_GPIO+ 0x0060)) + +/***********************************************************************/ +/* Module : BIU register address and bits */ +/***********************************************************************/ + +#define AMAZON_BIU (KSEG1+0x1FA80000) +/***********************************************************************/ + + +/***BIU Identification Register***/ +#define AMAZON_BIU_ID ((volatile u32*)(AMAZON_BIU+ 0x0000)) +#define AMAZON_BIU_ID_ARCH (1 << 16) +#define AMAZON_BIU_ID_ID(value) (((( 1 << 8) - 1) & (value)) << 8) +#define AMAZON_BIU_ID_REV(value) (((( 1 << 8) - 1) & (value)) << 0) + +/***BIU Access Error Cause Register***/ +#define AMAZON_BIU_ERRCAUSE ((volatile u32*)(AMAZON_BIU+ 0x0100)) +#define AMAZON_BIU_ERRCAUSE_ERR (1 << 31) +#define AMAZON_BIU_ERRCAUSE_PORT(value) (((( 1 << 4) - 1) & (value)) << 16) +#define AMAZON_BIU_ERRCAUSE_CAUSE(value) (((( 1 << 2) - 1) & (value)) << 0) + +/***BIU Access Error Address Register***/ +#define AMAZON_BIU_ERRADDR ((volatile u32*)(AMAZON_BIU+ 0x0108)) +#define AMAZON_BIU_ERRADDR_ADDR + +/***********************************************************************/ +/* Module : ICU register address and bits */ +/***********************************************************************/ + +#define AMAZON_ICU (KSEG1+0x1F101000) +/***********************************************************************/ + +/***IM0 Interrupt Status Register***/ +#define AMAZON_ICU_IM0_ISR (AMAZON_ICU + 0x0010) +#define AMAZON_ICU_IM1_ISR (AMAZON_ICU + 0x0020) +#define AMAZON_ICU_IM2_ISR (AMAZON_ICU + 0x0030) +#define AMAZON_ICU_IM3_ISR (AMAZON_ICU + 0x0040) +#define AMAZON_ICU_IM4_ISR (AMAZON_ICU + 0x0050) + +/***IM0 Interrupt Enable Register***/ +#define AMAZON_ICU_IM0_IER (AMAZON_ICU + 0x0014) +#define AMAZON_ICU_IM1_IER (AMAZON_ICU + 0x0024) +#define AMAZON_ICU_IM2_IER (AMAZON_ICU + 0x0034) +#define AMAZON_ICU_IM3_IER (AMAZON_ICU + 0x0044) +#define AMAZON_ICU_IM4_IER (AMAZON_ICU + 0x0054) + +/***IM0 Interrupt Output Status Register***/ +#define AMAZON_ICU_IM0_IOSR (AMAZON_ICU + 0x0018) +#define AMAZON_ICU_IM1_IOSR (AMAZON_ICU + 0x0028) +#define AMAZON_ICU_IM2_IOSR (AMAZON_ICU + 0x0038) +#define AMAZON_ICU_IM3_IOSR (AMAZON_ICU + 0x0048) +#define AMAZON_ICU_IM4_IOSR (AMAZON_ICU + 0x0058) + +/***IM0 Interrupt Request Set Register***/ +#define AMAZON_ICU_IM0_IRSR (AMAZON_ICU + 0x001c) +#define AMAZON_ICU_IM1_IRSR (AMAZON_ICU + 0x002c) +#define AMAZON_ICU_IM2_IRSR (AMAZON_ICU + 0x003c) +#define AMAZON_ICU_IM3_IRSR (AMAZON_ICU + 0x004c) +#define AMAZON_ICU_IM4_IRSR (AMAZON_ICU + 0x005c) + +/***Interrupt Vector Value Register***/ +#define AMAZON_ICU_IM_VEC (AMAZON_ICU + 0x0060) + +/***Interrupt Vector Value Mask***/ +#define AMAZON_ICU_IM0_VEC_MASK 0x0000001f +#define AMAZON_ICU_IM1_VEC_MASK 0x000003e0 +#define AMAZON_ICU_IM2_VEC_MASK 0x00007c00 +#define AMAZON_ICU_IM3_VEC_MASK 0x000f8000 +#define AMAZON_ICU_IM4_VEC_MASK 0x01f00000 + +/***DMA Interrupt Mask Value***/ +#define AMAZON_DMA_H_MASK 0x00000fff + +/***External Interrupt Control Register***/ +#define AMAZON_ICU_EXTINTCR (AMAZON_ICU + 0x0000) +#define AMAZON_ICU_IRNICR (AMAZON_ICU + 0x0004) +#define AMAZON_ICU_IRNCR (AMAZON_ICU + 0x0008) +#define AMAZON_ICU_IRNEN (AMAZON_ICU + 0x000c) + +/***********************************************************************/ +/* Module : PCI/Card-BUS/PC-Card register address and bits */ +/***********************************************************************/ + +#define AMAZON_PCI (KSEG1+0x10105400) +#define AMAZON_PCI_CFG_BASE (KSEG1+0x11000000) +#define AMAZON_PCI_MEM_BASE (KSEG1+0x12000000) + +#define CLOCK_CONTROL AMAZON_PCI + 0x00000000 +#define ARB_CTRL_bit 1 +#define IDENTIFICATION AMAZON_PCI + 0x00000004 +#define SOFTRESET AMAZON_PCI + 0x00000010 +#define PCI_FPI_ERROR_ADDRESS AMAZON_PCI + 0x00000014 +#define FPI_PCI_ERROR_ADDRESS AMAZON_PCI + 0x00000018 +#define FPI_ERROR_TAG AMAZON_PCI + 0x0000001c +#define IRR AMAZON_PCI + 0x00000020 +#define IRA_IR AMAZON_PCI + 0x00000024 +#define IRM AMAZON_PCI + 0x00000028 +#define DMA_COMPLETE_BIT 0 +#define PCI_POWER_CHANGE_BIT 16 +#define PCI_MASTER0_BROKEN_INT_BIT 24 +#define PCI_MASTER1_BROKEN_INT_BIT 25 +#define PCI_MASTER2_BROKEN_INT_BIT 26 +#define EOI AMAZON_PCI + 0x0000002c +#define PCI_MODE AMAZON_PCI + 0x00000030 +#define PCI_MODE_cfgok_bit 24 +#define DEVICE_VENDOR_ID AMAZON_PCI + 0x00000034 +#define SUBSYSTEM_VENDOR_ID AMAZON_PCI + 0x00000038 +#define POWER_MANAGEMENT AMAZON_PCI + 0x0000003c +#define CLASS_CODE1 AMAZON_PCI + 0x00000040 +#define BAR11_MASK AMAZON_PCI + 0x00000044 +#define BAR12_MASK AMAZON_PCI + 0x00000048 +#define BAR13_MASK AMAZON_PCI + 0x0000004c +#define BAR14_MASK AMAZON_PCI + 0x00000050 +#define BAR15_MASK AMAZON_PCI + 0x00000054 +#define BAR16_MASK AMAZON_PCI + 0x00000058 +#define CARDBUS_CIS_POINTER1 AMAZON_PCI + 0x0000005c +#define SUBSYSTEM_ID1 AMAZON_PCI + 0x00000060 +#define PCI_ADDRESS_MAP_11 AMAZON_PCI + 0x00000064 +#define PCI_ADDRESS_MAP_12 AMAZON_PCI + 0x00000068 +#define PCI_ADDRESS_MAP_13 AMAZON_PCI + 0x0000006c +#define PCI_ADDRESS_MAP_14 AMAZON_PCI + 0x00000070 +#define PCI_ADDRESS_MAP_15 AMAZON_PCI + 0x00000074 +#define PCI_ADDRESS_MAP_16 AMAZON_PCI + 0x00000078 +#define FPI_SEGMENT_ENABLE AMAZON_PCI + 0x0000007c +#define CLASS_CODE2 AMAZON_PCI + 0x00000080 +#define BAR21_MASK AMAZON_PCI + 0x00000084 +#define BAR22_MASK AMAZON_PCI + 0x00000088 +#define BAR23_MASK AMAZON_PCI + 0x0000008c +#define BAR24_MASK AMAZON_PCI + 0x00000090 +#define BAR25_MASK AMAZON_PCI + 0x00000094 +#define BAR26_MASK AMAZON_PCI + 0x00000098 +#define CARDBUS_CIS_POINTER2 AMAZON_PCI + 0x0000009c +#define SUBSYSTEM_ID2 AMAZON_PCI + 0x000000a0 +#define PCI_ADDRESS_MAP_21 AMAZON_PCI + 0x000000a4 +#define PCI_ADDRESS_MAP_22 AMAZON_PCI + 0x000000a8 +#define PCI_ADDRESS_MAP_23 AMAZON_PCI + 0x000000ac +#define PCI_ADDRESS_MAP_24 AMAZON_PCI + 0x000000b0 +#define PCI_ADDRESS_MAP_25 AMAZON_PCI + 0x000000b4 +#define PCI_ADDRESS_MAP_26 AMAZON_PCI + 0x000000b8 +#define FPI_ADDRESS_MASK11LOW AMAZON_PCI + 0x000000bc +#define FPI_ADDRESS_MAP_0 AMAZON_PCI + 0x000000c0 +#define FPI_ADDRESS_MAP_1 AMAZON_PCI + 0x000000c4 +#define FPI_ADDRESS_MAP_2 AMAZON_PCI + 0x000000c8 +#define FPI_ADDRESS_MAP_3 AMAZON_PCI + 0x000000cc +#define FPI_ADDRESS_MAP_4 AMAZON_PCI + 0x000000d0 +#define FPI_ADDRESS_MAP_5 AMAZON_PCI + 0x000000d4 +#define FPI_ADDRESS_MAP_6 AMAZON_PCI + 0x000000d8 +#define FPI_ADDRESS_MAP_7 AMAZON_PCI + 0x000000dc +#define FPI_ADDRESS_MAP_11LOW AMAZON_PCI + 0x000000e0 +#define FPI_ADDRESS_MAP_11HIGH AMAZON_PCI + 0x000000e4 +#define FPI_BURST_LENGTH AMAZON_PCI + 0x000000e8 +#define SET_PCI_SERR AMAZON_PCI + 0x000000ec +#define DMA_FPI_START_ADDR AMAZON_PCI + 0x000000f0 +#define DMA_PCI_START_ADDR AMAZON_PCI + 0x000000f4 +#define DMA_TRANSFER_COUNT AMAZON_PCI + 0x000000f8 +#define DMA_CONTROL_STATUS AMAZON_PCI + 0x000000fc + +#define EXT_PCI1_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x0800 +#define EXT_PCI2_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x1000 +#define EXT_PCI3_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x1800 +#define EXT_PCI4_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x2000 +#define EXT_PCI5_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x2800 +#define EXT_PCI6_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x3000 +#define EXT_PCI7_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x3800 +#define EXT_PCI8_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x4000 +#define EXT_PCI9_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x4800 +#define EXT_PCI10_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x5000 +#define EXT_PCI11_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x5800 +#define EXT_PCI12_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x6000 +#define EXT_PCI13_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x6800 +#define EXT_PCI14_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x7000 +#define EXT_PCI15_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x7800 +#define EXT_CARDBUS_CONFIG_SPACE_BASE_ADDR AMAZON_PCI_CFG_BASE + 0XF000 +#define EXT_PCI_BAR1_ADDR 0x10 +#define EXT_PCI_BAR2_ADDR 0x14 +#define EXT_PCI_BAR3_ADDR 0x18 +#define EXT_PCI_BAR4_ADDR 0x1C +#define EXT_PCI_BAR5_ADDR 0x20 +#define EXT_PCI_BAR6_ADDR 0x24 + +#define DEVICE_ID_VECDOR_ID_ADDR AMAZON_PCI_CFG_BASE + 0x0 +#define STATUS_COMMAND_ADDR AMAZON_PCI_CFG_BASE + 0x4 +#define BUS_MASTER_ENABLE_BIT 2 +#define MEM_SPACE_ENABLE_BIT 1 +#define CLASS_CODE_REVISION_ADDR AMAZON_PCI_CFG_BASE + 0x8 +#define BIST_HEADER_TYPE_LATENCY_CAHCE_ADDR AMAZON_PCI_CFG_BASE + 0xC +#define BAR1_ADDR AMAZON_PCI_CFG_BASE + 0x10 +#define BAR2_ADDR AMAZON_PCI_CFG_BASE + 0x14 +#define BAR3_ADDR AMAZON_PCI_CFG_BASE + 0x18 +#define BAR4_ADDR AMAZON_PCI_CFG_BASE + 0x1C +#define BAR3_ADDR AMAZON_PCI_CFG_BASE + 0x18 +#define BAR4_ADDR AMAZON_PCI_CFG_BASE + 0x1C +#define BAR5_ADDR AMAZON_PCI_CFG_BASE + 0x20 +#define BAR6_ADDR AMAZON_PCI_CFG_BASE + 0x24 +#define CARDBUS_CIS_POINTER_ADDR AMAZON_PCI_CFG_BASE + 0x28 +#define SUBSYSTEM_ID_VENDOR_ID_ADDR AMAZON_PCI_CFG_BASE + 0x2C +#define EXPANSION_ROM_BASE_ADDR AMAZON_PCI_CFG_BASE + 0x30 +#define CAPABILITIES_POINTER_ADDR AMAZON_PCI_CFG_BASE + 0x34 +#define RESERVED_0x38 AMAZON_PCI_CFG_BASE + 0x38 +#define MAX_LAT_MIN_GNT_INT_PIN_LINE_ADDR AMAZON_PCI_CFG_BASE + 0x3C +#define POWER_MNGT_NEXT_POINTER_CAP_ID_ADDR AMAZON_PCI_CFG_BASE + 0x40 +#define POWER_MANAGEMENT_CTRL_STATUS_ADDR AMAZON_PCI_CFG_BASE + 0x44 +#define RESERVED_0x48 AMAZON_PCI_CFG_BASE + 0x48 +#define RESERVED_0x4C AMAZON_PCI_CFG_BASE + 0x4C +#define ERROR_ADDR_PCI_FPI_ADDR AMAZON_PCI_CFG_BASE + 0x50 +#define ERROR_ADdR_FPI_PCI_ADDR AMAZON_PCI_CFG_BASE + 0x54 +#define ERROR_TAG_FPI_PCI_ADDR AMAZON_PCI_CFG_BASE + 0x58 +#define PCI_ARB_CTRL_STATUS_ADDR AMAZON_PCI_CFG_BASE + 0x5C +#define INTERNAL_ARB_ENABLE_BIT 0 +#define ARB_SCHEME_BIT 1 +#define PCI_MASTER0_PRIOR_2BITS 2 +#define PCI_MASTER1_PRIOR_2BITS 4 +#define PCI_MASTER2_PRIOR_2BITS 6 +#define PCI_MASTER0_REQ_MASK_2BITS 8 +#define PCI_MASTER1_REQ_MASK_2BITS 10 +#define PCI_MASTER2_REQ_MASK_2BITS 12 +#define PCI_MASTER0_GNT_MASK_2BITS 14 +#define PCI_MASTER1_GNT_MASK_2BITS 16 +#define PCI_MASTER2_GNT_MASK_2BITS 18 +#define FPI_PCI_INT_STATUS_ADDR AMAZON_PCI_CFG_BASE + 0x60 +#define FPI_PCI_INT_ACK_ADDR AMAZON_PCI_CFG_BASE + 0x64 +#define FPI_PCI_INT_MASK_ADDR AMAZON_PCI_CFG_BASE + 0x68 +#define CARDBUS_CTRL_STATUS_ADDR AMAZON_PCI_CFG_BASE + 0x6C +#define CARDBUS_CFRAME_ENABLE 0 + +#define CLOCK_CONTROL_default 0x00000000 +#define CLOCK_CONTROL_mask 0x00000003 + +#define IDENTIFICATION_default 0x0011C002 +#define IDENTIFICATION_mask 0x00000000 + +#define SOFTRESET_default 0x00000000 +// SOFTRESET bit 0 is writable but will be reset to 0 after software reset is over +#define SOFTRESET_mask 0x00000000 + +#define PCI_FPI_ERROR_ADDRESS_default 0xFFFFFFFF +#define PCI_FPI_ERROR_ADDRESS_mask 0x00000000 + +#define FPI_PCI_ERROR_ADDRESS_default 0xFFFFFFFF +#define FPI_PCI_ERROR_ADDRESS_mask 0x00000000 + +#define FPI_ERROR_TAG_default 0x0000000F +#define FPI_ERROR_TAG_mask 0x00000000 + +#define IRR_default 0x00000000 +#define IRR_mask 0x07013b2F + +#define IRA_IR_default 0x00000000 +#define IRA_IR_mask 0x07013b2F + +#define IRM_default 0x00000000 +#define IRM_mask 0xFFFFFFFF + +#define EOI_default 0x00000000 +#define EOI_mask 0x00000000 + +#define PCI_MODE_default 0x01000103 +#define PCI_MODE_mask 0x1107070F + +#define DEVICE_VENDOR_ID_default 0x000C15D1 +#define DEVICE_VENDOR_ID_mask 0xFFFFFFFF + +#define SUBSYSTEM_VENDOR_ID_default 0x000015D1 +#define SUBSYSTEM_VENDOR_ID_mask 0x0000FFFF + +#define POWER_MANAGEMENT_default 0x0000001B +#define POWER_MANAGEMENT_mask 0x0000001F + +#define CLASS_CODE1_default 0x00028000 +#define CLASS_CODE1_mask 0x00FFFFFF + +#define BAR11_MASK_default 0x0FF00008 +#define BAR11_MASK_mask 0x8FF00008 + +#define BAR12_MASK_default 0x80001800 +#define BAR12_MASK_mask 0x80001F08 + +#define BAR13_MASK_default 0x8FF00008 +#define BAR13_MASK_mask 0x8FF00008 + +#define BAR14_MASK_default 0x8F000000 +#define BAR14_MASK_mask 0x8FFFFF08 + +#define BAR15_MASK_default 0x80000000 +#define BAR15_MASK_mask 0x8FFFFF08 + +#define BAR16_MASK_default 0x80000001 +// bit 0 and bit 3 is mutually exclusive +#define BAR16_MASK_mask 0x8FFFFFF9 + +#define CARDBUS_CIS_POINTER1_default 0x00000000 +#define CARDBUS_CIS_POINTER1_mask 0x03FFFFFF + +#define SUBSYSTEM_ID1_default 0x0000000C +#define SUBSYSTEM_ID1_mask 0x0000FFFF + +#define PCI_ADDRESS_MAP_11_default 0x18000000 +#define PCI_ADDRESS_MAP_11_mask 0x7FFFFFF1 + +#define PCI_ADDRESS_MAP_12_default 0x18100000 +#define PCI_ADDRESS_MAP_12_mask 0x7FFFFF01 + +#define PCI_ADDRESS_MAP_13_default 0x18200000 +#define PCI_ADDRESS_MAP_13_mask 0x7FF00001 + +#define PCI_ADDRESS_MAP_14_default 0x70000000 +#define PCI_ADDRESS_MAP_14_mask 0x7FFFFF01 + +#define PCI_ADDRESS_MAP_15_default 0x00000001 +#define PCI_ADDRESS_MAP_15_mask 0x7FFFFF01 + +#define PCI_ADDRESS_MAP_16_default 0x60000000 +#define PCI_ADDRESS_MAP_16_mask 0x7FF00001 + +#define FPI_SEGMENT_ENABLE_default 0x000003FF +#define FPI_SEGMENT_ENABLE_mask 0x000003FF + +#define CLASS_CODE2_default 0x00FF0000 +#define CLASS_CODE2_mask 0x00FFFFFF + +#define BAR21_MASK_default 0x80000008 +#define BAR21_MASK_mask 0x8FFFFFF8 + +#define BAR22_MASK_default 0x80000008 +#define BAR22_MASK_mask 0x80001F08 + +#define BAR23_MASK_default 0x80000008 +#define BAR23_MASK_mask 0x8FF00008 + +#define BAR24_MASK_default 0x8FE00000 +#define BAR24_MASK_mask 0x8FFFFF08 + +#define BAR25_MASK_default 0x8FFFF000 +#define BAR25_MASK_mask 0x8FFFFF08 + +#define BAR26_MASK_default 0x8FFFFFE1 +#define BAR26_MASK_mask 0x8FFFFFF1 + +#define CARDBUS_CIS_POINTER2_default 0x00000000 +#define CARDBUS_CIS_POINTER2_mask 0x03FFFFFF + +#define SUBSYSTEM_ID2_default 0x0000000C +#define SUBSYSTEM_ID2_mask 0x0000FFFF + +#define PCI_ADDRESS_MAP_21_default 0x3FE00000 +#define PCI_ADDRESS_MAP_21_mask 0x7FFFFFF1 + +#define PCI_ADDRESS_MAP_22_default 0x68000000 +#define PCI_ADDRESS_MAP_22_mask 0x7FFFFF01 + +#define PCI_ADDRESS_MAP_23_default 0x20000000 +#define PCI_ADDRESS_MAP_23_mask 0x7FF00001 + +#define PCI_ADDRESS_MAP_24_default 0x70000001 +#define PCI_ADDRESS_MAP_24_mask 0x7FFFFF01 + +#define PCI_ADDRESS_MAP_25_default 0x78000001 +#define PCI_ADDRESS_MAP_25_mask 0x7FFFFF01 + +#define PCI_ADDRESS_MAP_26_default 0x20000000 +#define PCI_ADDRESS_MAP_26_mask 0x7FF00001 + +#define FPI_ADDRESS_MASK11LOW_default 0x00000000 +#define FPI_ADDRESS_MASK11LOW_mask 0x00070000 + +#define FPI_ADDRESS_MAP_0_default 0x00000000 +#define FPI_ADDRESS_MAP_0_mask 0xFFF00000 + +#define FPI_ADDRESS_MAP_1_default 0x10000000 +#define FPI_ADDRESS_MAP_1_mask 0xFFF00000 + +#define FPI_ADDRESS_MAP_2_default 0x20000000 +#define FPI_ADDRESS_MAP_2_mask 0xFFF00000 + +#define FPI_ADDRESS_MAP_3_default 0x30000000 +#define FPI_ADDRESS_MAP_3_mask 0xFFF00000 + +#define FPI_ADDRESS_MAP_4_default 0x40000000 +#define FPI_ADDRESS_MAP_4_mask 0xFFF00000 + +#define FPI_ADDRESS_MAP_5_default 0x50000000 +#define FPI_ADDRESS_MAP_5_mask 0xFFF00000 + +#define FPI_ADDRESS_MAP_6_default 0x60000000 +#define FPI_ADDRESS_MAP_6_mask 0xFFF00000 + +#define FPI_ADDRESS_MAP_7_default 0x70000000 +#define FPI_ADDRESS_MAP_7_mask 0xFFF00000 + +#define FPI_ADDRESS_MAP_11LOW_default 0xB0000000 +#define FPI_ADDRESS_MAP_11LOW_mask 0xFFFF0000 + +#define FPI_ADDRESS_MAP_11HIGH_default 0xB8000000 +#define FPI_ADDRESS_MAP_11HIGH_mask 0xFFF80000 + +#define FPI_BURST_LENGTH_default 0x00000000 +#define FPI_BURST_LENGTH_mask 0x00000303 + +#define SET_PCI_SERR_default 0x00000000 +#define SET_PCI_SERR_mask 0x00000000 + +#define DMA_FPI_START_ADDRESS_default 0x00000000 +#define DMA_FPI_START_ADDRESS_mask 0xFFFFFFFF + +#define DMA_PCI_START_ADDRESS_default 0x00000000 +#define DMA_PCI_START_ADDRESS_mask 0xFFFFFFFF + +#define DMA_TRANSFER_COUNT_default 0x00000000 +#define DMA_TRANSFER_COUNT_mask 0x0000FFFF + +#define DMA_CONTROL_STATUS_default 0x00000000 +#define DMA_CONTROL_STATUS_mask 0x00000000 // bit 0,1 is writable + +/***********************************************************************/ +#undef IKOS_MINI_BOOT //don't run a full booting +#ifdef CONFIG_USE_IKOS +#define CONFIG_USE_VENUS //Faster, 10M CPU and 192k baudrate +#ifdef CONFIG_USE_VENUS +#define IKOS_CPU_SPEED 10000000 +#else +#define IKOS_CPU_SPEED 180000 //IKOS is slow +#endif +#endif //CONFIG_USE_IKOS + +/* 165001:henryhsu:20050603:Source Modify form Bing Tao */ + +#if defined(CONFIG_NET_WIRELESS_SPURS) || defined(CONFIG_NET_WIRELESS_SPURS_MODULE) +#define EBU_PCI_SOFTWARE_ARBITOR +#endif + +#define AMAZON_B11 +#ifdef AMAZON_B11 +#define SWITCH_BUF_FPI_ADDR (0x10110000) +#define SWITCH_BUF_ADDR (KSEG1+SWITCH_BUF_FPI_ADDR) +#define SWITCH_BUF_SIZE (0x2800) +#define AMAZON_B11_CBM_QD_ADDR (SWITCH_BUF_ADDR+0x0) +#define AMAZON_B11_BOND_CELL_ADDR (SWITCH_BUF_ADDR+0x000) +#endif +#define AMAZON_REFERENCE_BOARD +//for AMAZON ATM bonding application +#ifdef AMAZON_REFERENCE_BOARD +#define GPIO_DETECT_LOW +#else +#undef GPIO_DETECT_LOW +#endif + +/* 165001 */ + +#undef AMAZON_IKOS_DEBUG_MSG +#undef AMAZON_INT_DEBUG_MSG +#undef AMAZON_ATM_DEBUG_MSG +#undef AMAZON_DMA_DEBUG_MSG +#undef AMAZON_SW_DEBUG_MSG +#undef AMAZON_WDT_DEBUG_MSG +#undef AMAZON_MTD_DEBUG_MSG +#undef AMAZON_SSC_DEBUG_MSG +#undef AMAZON_MEI_DEBUG_MSG + +#ifdef AMAZON_IKOS_DEBUG_MSG +#define AMAZON_IKOS_DMSG(fmt,args...) printk("%s:" fmt, __FUNCTION__, ##args) +#else +#define AMAZON_IKOS_DMSG(fmt,args...) +#endif + +#ifdef AMAZON_WDT_DEBUG_MSG +#define AMAZON_WDT_DMSG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ##args) +#else +#define AMAZON_WDT_DMSG(fm,args...) +#endif + +#ifdef AMAZON_SSC_DEBUG_MSG +#define AMAZON_SSC_DMSG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ##args) +#else +#define AMAZON_SSC_DMSG(fm,args...) +#endif + +#ifdef AMAZON_DMA_DEBUG_MSG +#define AMAZON_DMA_DMSG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ##args) +#else +#define AMAZON_DMA_DMSG(fm,args...) +#endif + +#ifdef AMAZON_ATM_DEBUG_MSG +#define AMAZON_TPE_DMSG(fmt, args...) printk( "%s: " fmt, __FUNCTION__ , ##args) +#else //not AMAZON_ATM_DEBUG +#define AMAZON_TPE_DMSG(fmt, args...) +#endif //AMAZON_ATM_DEBUG + +#ifdef AMAZON_SW_DEBUG_MSG +#define AMAZON_SW_DMSG(fmt,args...) printk("%s: " fmt, __FUNCTION__ , ##args) +#else +#define AMAZON_SW_DMSG(fmt,args...) +#endif + +#ifdef AMAZON_MTD_DEBUG_MSG +#define AMAZON_MTD_DMSG(fmt,args...) printk("%s: " fmt, __FUNCTION__ , ##args) +#else +#define AMAZON_MTD_DMSG(fmt,args...) +#endif + +#ifdef AMAZON_INT_DEBUG_MSG +#define AMAZON_INT_DMSG(x...) printk(x) +#else +#define AMAZON_INT_DMSG(x...) +#endif + +#ifdef AMAZON_MEI_DEBUG_MSG +#define AMAZON_MEI_DMSG(fmt,args...) printk("%s:" fmt, __FUNCTION__, ##args) +#else +#define AMAZON_MEI_DMSG(fmt,args...) +#endif + +#endif //AMAZON_H diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_dma.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_dma.h new file mode 100644 index 0000000000..63ab5924e5 --- /dev/null +++ b/target/linux/amazon/files/include/asm-mips/amazon/amazon_dma.h @@ -0,0 +1,148 @@ +#ifndef AMAZON_DMA_H +#define AMAZON_DMA_H + +#define RCV_INT 1 +#define TX_BUF_FULL_INT 2 +#define TRANSMIT_CPT_INT 4 + +#define QOS_DEFAULT_WGT 0x7fffffffUL; + + +enum attr_t{ + TX=0, + RX=1, + RESERVED=2, + DEFAULT=3, + +}; + +#ifdef CONFIG_CPU_LITTLE_ENDIAN +typedef struct rx_desc{ + u32 data_length:16; + volatile u32 reserved:7; + volatile u32 byte_offset:2; + volatile u32 Burst_length_offset:3; + volatile u32 EoP:1; + volatile u32 Res:1; + volatile u32 C:1; + volatile u32 OWN:1; + volatile u32 Data_Pointer; + /*fix me:should be 28 bits here, 32 bits just for host simulatiuon purpose*/ +}_rx_desc; + + +typedef struct tx_desc{ + volatile u32 data_length:16; + volatile u32 reserved1:7; + volatile u32 byte_offset:5; + volatile u32 EoP:1; + volatile u32 SoP:1; + volatile u32 C:1; + volatile u32 OWN:1; + volatile u32 Data_Pointer;//fix me:should be 28 bits here +}_tx_desc; +#else //BIG +typedef struct rx_desc{ + union + { + struct + { + volatile u32 OWN :1; + volatile u32 C :1; + volatile u32 SoP :1; + volatile u32 EoP :1; + volatile u32 Burst_length_offset :3; + volatile u32 byte_offset :2; + volatile u32 reserve :7; + volatile u32 data_length :16; + }field; + + volatile u32 word; + }status; + + volatile u32 Data_Pointer; +}_rx_desc; + + +typedef struct tx_desc{ + union + { + struct + { + volatile u32 OWN :1; + volatile u32 C :1; + volatile u32 SoP :1; + volatile u32 EoP :1; + volatile u32 byte_offset :5; + volatile u32 reserved :7; + volatile u32 data_length :16; + }field; + + volatile u32 word; + }status; + + volatile u32 Data_Pointer; +}_tx_desc; + +#endif //ENDIAN + +struct dma_channel_info{ + /*filled by driver, optional*/ + enum attr_t attr;/*TX or RX*/ + int weight; + int desc_num; + int packet_size; + int control;/*on or off*/ + + int desc_base; + int status; +}; + +typedef struct dma_channel_info _dma_channel_info; + +struct dma_device_info{ + /*variables*/ + /*filled by driver, compulsary*/ + char device_name[15]; + enum attr_t attr;/*default or else*/ + int tx_burst_len; + int rx_burst_len; + + int logic_rx_chan_base; + int logic_tx_chan_base; + u8 on_ch_bit; + /*filled by driver, optional*/ + int weight; + int current_tx_chan; + int current_rx_chan; + int num_tx_chan; + int num_rx_chan; + struct dma_channel_info tx_chan[2]; + struct dma_channel_info rx_chan[4]; + + /*functions, optional*/ + u8* (*buffer_alloc)(int len,int* offset, void** opt); + int (*buffer_free)(u8* dataptr, void* opt); + int (*intr_handler)(struct dma_device_info* info, int status); + /*set by device, clear by dma*/ + int ack; + void * priv; /* used by peripheral driver only */ +}; +typedef struct dma_device_info _dma_device_info; + +int dma_device_register(struct dma_device_info* info); + +int dma_device_unregister(struct dma_device_info* info); + +int dma_device_read(struct dma_device_info* info, u8** dataptr, void** opt); + +int dma_device_write(struct dma_device_info* info, u8* dataptr, int len, void* opt); + +int dma_device_update(struct dma_device_info* info); + +void dma_device_update_rx(struct dma_device_info* dma_dev); + +void dma_device_update_tx(struct dma_device_info* dma_dev); + +void register_handler_sim(int (*handler)(int)); +#endif /* AMAZON_DMA_H */ diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei.h new file mode 100644 index 0000000000..6ac8ab310b --- /dev/null +++ b/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei.h @@ -0,0 +1,220 @@ +#ifndef _AMAZON_MEI_H +#define _AMAZON_MEI_H +///////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#include "amazon_mei_app.h" + +#define AMAZON_MEI_DEBUG_ON +#define AMAZON_MEI_CMV_EXTRA + +#define AMAZON_MEI_MAJOR 106 + +/* +** Define where in ME Processor's memory map the Stratify chip lives +*/ +#define MEI_SPACE_ACCESS 0xB0100C00 + +#define MAXSWAPSIZE 8 * 1024 //8k *(32bits) +//#define AMAZON_ADSL_IMAGESIZE 16*1024 // 16k * (32bits) + + +// Mailboxes +#define MSG_LENGTH 16 // x16 bits +#define YES_REPLY 1 +#define NO_REPLY 0 + +#define CMV_TIMEOUT 100 //jiffies +#define MIB_INTERVAL 10000 //msec + +/*** Bit definitions ***/ + +#define FALSE 0 +#define TRUE 1 +#define BIT0 1<<0 +#define BIT1 1<<1 +#define BIT2 1<<2 +#define BIT3 1<<3 +#define BIT4 1<<4 +#define BIT5 1<<5 +#define BIT6 1<<6 +#define BIT7 1<<7 +#define BIT8 1<<8 +#define BIT9 1<<9 +#define BIT10 1<<10 +#define BIT11 1<<11 +#define BIT12 1<<12 +#define BIT13 1<<13 +#define BIT14 1<<14 +#define BIT15 1<<15 +#define BIT16 1<<16 +#define BIT17 1<<17 +#define BIT18 1<<18 +#define BIT19 1<<19 +#define BIT20 1<<20 +#define BIT21 1<<21 +#define BIT22 1<<22 +#define BIT23 1<<23 +#define BIT24 1<<24 +#define BIT25 1<<25 +#define BIT26 1<<26 +#define BIT27 1<<27 +#define BIT28 1<<28 +#define BIT29 1<<29 +#define BIT30 1<<30 +#define BIT31 1<<31 + + +/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/ +#define MEI_DATA_XFR (0x0000 + MEI_SPACE_ACCESS) +#define MEI_VERSION (0x0200 + MEI_SPACE_ACCESS) +#define ARC_GP_STAT (0x0204 + MEI_SPACE_ACCESS) +#define MEI_XFR_ADDR (0x020C + MEI_SPACE_ACCESS) +#define MEI_TO_ARC_INT (0x021C + MEI_SPACE_ACCESS) +#define ARC_TO_MEI_INT (0x0220 + MEI_SPACE_ACCESS) +#define ARC_TO_MEI_INT_MASK (0x0224 + MEI_SPACE_ACCESS) +#define MEI_DEBUG_WAD (0x0228 + MEI_SPACE_ACCESS) +#define MEI_DEBUG_RAD (0x022C + MEI_SPACE_ACCESS) +#define MEI_DEBUG_DATA (0x0230 + MEI_SPACE_ACCESS) +#define MEI_DEBUG_DEC (0x0234 + MEI_SPACE_ACCESS) +#define MEI_CONTROL (0x0238 + MEI_SPACE_ACCESS) +#define AT_CELLRDY_BC0 (0x023C + MEI_SPACE_ACCESS) +#define AT_CELLRDY_BC1 (0x0240 + MEI_SPACE_ACCESS) +#define AR_CELLRDY_BC0 (0x0244 + MEI_SPACE_ACCESS) +#define AR_CELLRDY_BC1 (0x0248 + MEI_SPACE_ACCESS) +#define AAI_ACCESS (0x024C + MEI_SPACE_ACCESS) +#define AAITXCB0 (0x0300 + MEI_SPACE_ACCESS) +#define AAITXCB1 (0x0304 + MEI_SPACE_ACCESS) +#define AAIRXCB0 (0x0308 + MEI_SPACE_ACCESS) +#define AAIRXCB1 (0x030C + MEI_SPACE_ACCESS) + + +// MEI_TO_ARC_INTERRUPT Register definitions +#define MEI_TO_ARC_INT1 BIT3 +#define MEI_TO_ARC_INT0 BIT2 +#define MEI_TO_ARC_CS_DONE BIT1 +#define MEI_TO_ARC_MSGAV BIT0 + +// ARC_TO_MEI_INTERRUPT Register definitions +#define ARC_TO_MEI_INT1 BIT8 +#define ARC_TO_MEI_INT0 BIT7 +#define ARC_TO_MEI_CS_REQ BIT6 +#define ARC_TO_MEI_DBG_DONE BIT5 +#define ARC_TO_MEI_MSGACK BIT4 +#define ARC_TO_MEI_NO_ACCESS BIT3 +#define ARC_TO_MEI_CHECK_AAITX BIT2 +#define ARC_TO_MEI_CHECK_AAIRX BIT1 +#define ARC_TO_MEI_MSGAV BIT0 + +// ARC_TO_MEI_INTERRUPT_MASK Register definitions +#define GP_INT1_EN BIT8 +#define GP_INT0_EN BIT7 +#define CS_REQ_EN BIT6 +#define DBG_DONE_EN BIT5 +#define MSGACK_EN BIT4 +#define NO_ACC_EN BIT3 +#define AAITX_EN BIT2 +#define AAIRX_EN BIT1 +#define MSGAV_EN BIT0 + +// MEI_CONTROL Register definitions +#define INT_LEVEL BIT2 +#define SOFT_RESET BIT1 +#define HOST_MSTR BIT0 + +// MEI_DEBUG_DECODE Register definitions +#define MEI_DEBUG_DEC_MASK (0x3) +#define MEI_DEBUG_DEC_AUX_MASK (0x0) +#define MEI_DEBUG_DEC_DMP1_MASK (0x1) +#define MEI_DEBUG_DEC_DMP2_MASK (0x2) +#define MEI_DEBUG_DEC_CORE_MASK (0x3) + + +// ARC_TO_MEI_MAILBOX[11] is a special location used to indicate +// page swap requests. +#define MEI_TO_ARC_MAILBOX (0x15FC0) +#define MEI_TO_ARC_MAILBOXR (0x15FEC) +#define ARC_TO_MEI_MAILBOX (0x15F90) +#define ARC_MEI_MAILBOXR (0x15FBC) + +// Codeswap request messages are indicated by setting BIT31 +#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000) + +/* +** Swap page header +*/ +// Page must be loaded at boot time if size field has BIT31 set +#define BOOT_FLAG (BIT31) +#define BOOT_FLAG_MASK ~BOOT_FLAG + +// Swap page header describes size in 32-bit words, load location, and image offset +// for program and/or data segments +typedef struct _arc_swp_page_hdr +{ + u32 p_offset; // Offset bytes of progseg from beginning of image + u32 p_dest; // Destination addr of progseg on processor + u32 p_size; // Size in 32-bitwords of program segment + u32 d_offset; // Offset bytes of dataseg from beginning of image + u32 d_dest; // Destination addr of dataseg on processor + u32 d_size; // Size in 32-bitwords of data segment +}ARC_SWP_PAGE_HDR; + + +/* +** Swap image header +*/ +#define GET_PROG 0 // Flag used for program mem segment +#define GET_DATA 1 // Flag used for data mem segment + +// Image header contains size of image, checksum for image, and count of +// page headers. Following that are 'count' page headers followed by +// the code and/or data segments to be loaded +typedef struct _arc_img_hdr +{ + u32 size; // Size of binary image in bytes + u32 checksum; // Checksum for image + u32 count; // Count of swp pages in image + ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy +}ARC_IMG_HDR; + + + +/* +** Native size for the Stratiphy interface is 32-bits. All reads and writes +** MUST be aligned on 32-bit boundaries. Trickery must be invoked to read word and/or +** byte data. Read routines are provided. Write routines are probably a bad idea, as the +** Arc has unrestrained, unseen access to the same memory, so a read-modify-write cycle +** could very well have unintended results. +*/ +MEI_ERROR meiCMV(u16 *, int); // first arg is CMV to ARC, second to indicate whether need reply + +void meiLongwordWrite(u32 ul_address, u32 ul_data); +void meiLongwordRead(u32 ul_address, u32 *pul_data); + + +MEI_ERROR meiDMAWrite(u32 destaddr, u32 *databuff, u32 databuffsize); +MEI_ERROR meiDebugWrite(u32 destaddr, u32 *databuff, u32 databuffsize); + +MEI_ERROR meiDMARead(u32 srcaddr, u32 *databuff, u32 databuffsize); +MEI_ERROR meiDebugRead(u32 srcaddr, u32 *databuff, u32 databuffsize); + +void meiPollForDbgDone(void); + +void meiMailboxInterruptsDisable(void); +void meiMailboxInterruptsEnable(void); + +MEI_ERROR meiMailboxWrite(u16 *msgsrcbuffer, u16 msgsize); +MEI_ERROR meiMailboxRead(u16 *msgdestbuffer, u16 msgsize); + +int meiGetPage( u32 Page, u32 data, u32 MaxSize, u32 *Buffer, u32 *Dest); + +MEI_ERROR meiHaltArc(void); +MEI_ERROR meiRunArc(void); + +MEI_ERROR meiDownloadBootCode(void); + +MEI_ERROR meiForceRebootAdslModem(void); + +void makeCMV(u8 opcode, u8 group, u16 address, u16 index, int size, u16 * data); + +#endif + diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_app.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_app.h new file mode 100644 index 0000000000..89700d9d76 --- /dev/null +++ b/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_app.h @@ -0,0 +1,54 @@ +//509221:tc.chen 2005/09/22 Reset DFE added when MEI_TO_ARC_CS_DONE not cleared by ARC and Added AMAZON_MEI_DEBUG_MODE ioctl + +#ifndef _AMAZON_MEI_APP_H +#define _AMAZON_MEI_APP_H + +///////////////////////////////////////////////////////////////////////////////////////////////////// + + // ioctl control +#define AMAZON_MEI_START 300 +#define AMAZON_MEI_REPLY 301 +#define AMAZON_MEI_NOREPLY 302 + +#define AMAZON_MEI_RESET 303 +#define AMAZON_MEI_REBOOT 304 +#define AMAZON_MEI_HALT 305 +#define AMAZON_MEI_CMV_WINHOST 306 +#define AMAZON_MEI_CMV_READ 307 +#define AMAZON_MEI_CMV_WRITE 308 +#define AMAZON_MEI_MIB_DAEMON 309 +#define AMAZON_MEI_SHOWTIME 310 +#define AMAZON_MEI_REMOTE 311 +#define AMAZON_MEI_READDEBUG 312 +#define AMAZON_MEI_WRITEDEBUG 313 +#define AMAZON_MEI_LOP 314 + +#define AMAZON_MEI_PCM_SETUP 315 +#define AMAZON_MEI_PCM_START_TIMER 316 +#define AMAZON_MEI_PCM_STOP_TIMER 317 +#define AMAZON_MEI_PCM_CHECK 318 +#define AMAZON_MEI_GET_EOC_LEN 319 +#define AMAZON_MEI_GET_EOC_DATA 320 +#define AMAZON_MEI_PCM_GETDATA 321 +#define AMAZON_MEI_PCM_GPIO 322 +#define AMAZON_MEI_EOC_SEND 323 +//MIB +#define AMAZON_MIB_LO_ATUC 324 +#define AMAZON_MIB_LO_ATUR 325 +#define AMAZON_MEI_DOWNLOAD 326 + +#define AMAZON_MEI_DEBUG_MODE 327 //509221:tc.chen +#define LOOP_DIAGNOSTIC_MODE_COMPLETE 328 + + +/*** Enums ***/ +typedef enum mei_error +{ + MEI_SUCCESS = 0, + MEI_FAILURE = -1, + MEI_MAILBOX_FULL = -2, + MEI_MAILBOX_EMPTY = -3, + MEI_MAILBOX_TIMEOUT = -4, +}MEI_ERROR; + +#endif diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_app_ioctl.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_app_ioctl.h new file mode 100644 index 0000000000..d98f60b171 --- /dev/null +++ b/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_app_ioctl.h @@ -0,0 +1,1169 @@ +// 603221:tc.chen 2006/03/21 added APIs to support the WEB related parameters for ADSL Statistics + +#ifndef __AMAZON_MEI_APP_IOCTL_H +#define __AMAZON_MEI_APP_IOCTL_H + +#ifdef __KERNEL__ +#include "amazon_mei_ioctl.h" +#endif + +/* Interface Name */ +//#define INTERFACE_NAME <define the interface> + +/* adslLineTable constants */ +#define GET_ADSL_LINE_CODE 1 + +/* adslAtucPhysTable constants */ +#define GET_ADSL_ATUC_PHY 4 + +/* adslAturPhysTable constants */ +#define GET_ADSL_ATUR_PHY 10 + +/* adslAtucChanTable constants */ +#define GET_ADSL_ATUC_CHAN_INFO 15 + +/* adslAturChanTable constants */ +#define GET_ADSL_ATUR_CHAN_INFO 18 + +/* adslAtucPerfDataTable constants */ +#define GET_ADSL_ATUC_PERF_DATA 21 + +/* adslAturPerfDataTable constants */ +#define GET_ADSL_ATUR_PERF_DATA 40 + +/* adslAtucIntervalTable constants */ +#define GET_ADSL_ATUC_INTVL_INFO 60 + +/* adslAturIntervalTable constants */ +#define GET_ADSL_ATUR_INTVL_INFO 65 + +/* adslAtucChanPerfDataTable constants */ +#define GET_ADSL_ATUC_CHAN_PERF_DATA 70 + +/* adslAturChanPerfDataTable constants */ +#define GET_ADSL_ATUR_CHAN_PERF_DATA 90 + +/* adslAtucChanIntervalTable constants */ +#define GET_ADSL_ATUC_CHAN_INTVL_INFO 110 + +/* adslAturChanIntervalTable constants */ +#define GET_ADSL_ATUR_CHAN_INTVL_INFO 115 + +/* adslLineAlarmConfProfileTable constants */ +#define GET_ADSL_ALRM_CONF_PROF 120 +#define SET_ADSL_ALRM_CONF_PROF 121 + +/* adslAturTrap constants */ +#define ADSL_ATUR_TRAPS 135 + +////////////////// RFC-3440 ////////////// + +#ifdef AMAZON_MEI_MIB_RFC3440 +/* adslLineExtTable */ +#define GET_ADSL_ATUC_LINE_EXT 201 +#define SET_ADSL_ATUC_LINE_EXT 203 + +/* adslAtucPerfDateExtTable */ +#define GET_ADSL_ATUC_PERF_DATA_EXT 205 + +/* adslAtucIntervalExtTable */ +#define GET_ADSL_ATUC_INTVL_EXT_INFO 221 + +/* adslAturPerfDataExtTable */ +#define GET_ADSL_ATUR_PERF_DATA_EXT 225 + +/* adslAturIntervalExtTable */ +#define GET_ADSL_ATUR_INTVL_EXT_INFO 233 + +/* adslAlarmConfProfileExtTable */ +#define GET_ADSL_ALRM_CONF_PROF_EXT 235 +#define SET_ADSL_ALRM_CONF_PROF_EXT 236 + +/* adslAturExtTrap */ +#define ADSL_ATUR_EXT_TRAPS 240 + +#endif + +// 603221:tc.chen start +/* The following constants are added to support the WEB related ADSL Statistics */ + +/* adslLineStatus constants */ +#define GET_ADSL_LINE_STATUS 245 + +/* adslLineRate constants */ +#define GET_ADSL_LINE_RATE 250 + +/* adslLineInformation constants */ +#define GET_ADSL_LINE_INFO 255 + +/* adslNearEndPerformanceStats constants */ +#define GET_ADSL_NEAREND_STATS 270 + +/* adslFarEndPerformanceStats constants */ +#define GET_ADSL_FAREND_STATS 290 + +// 603221:tc.chen end + +/* Loop diagnostics mode of the ADSL line related constants */ +#define GET_ADSL_LOOP_DIAGNOSTICS_MODE 295 +#define SET_ADSL_LOOP_DIAGNOSTICS_MODE 296 +#define IS_ADSL_LOOP_DIAGNOSTICS_MODE_COMPLETE 299 + +/* Sub-carrier related parameters */ +#define GET_ADSL_ATUC_SUBCARRIER_STATS 297 +#define GET_ADSL_ATUR_SUBCARRIER_STATS 298 +#define GET_ADSL_LINE_INIT_STATS 150 +#define GET_ADSL_POWER_SPECTRAL_DENSITY 151 + + +/////////////////////////////////////////////////////////// +// makeCMV(Opcode, Group, Address, Index, Size, Data) + +/* adslLineCode Flags */ +#define LINE_CODE_FLAG 0x1 /* BIT 0th position */ + +/* adslAtucPhysTable Flags */ +#define ATUC_PHY_SER_NUM_FLAG 0x1 /* BIT 0th position */ +#define ATUC_PHY_SER_NUM_FLAG_MAKECMV1 makeCMV(H2D_CMV_READ, INFO, 57, 0, 12, data) +#define ATUC_PHY_SER_NUM_FLAG_MAKECMV2 makeCMV(H2D_CMV_READ, INFO, 57, 12, 4, data) + +#define ATUC_PHY_VENDOR_ID_FLAG 0x2 /* BIT 1 */ +#define ATUC_PHY_VENDOR_ID_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 64, 0, 4, data) + +#define ATUC_PHY_VER_NUM_FLAG 0x4 /* BIT 2 */ +#define ATUC_PHY_VER_NUM_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 58, 0, 8, data) + +#define ATUC_CURR_STAT_FLAG 0x8 /* BIT 3 */ + +#define ATUC_CURR_OUT_PWR_FLAG 0x10 /* BIT 4 */ +#define ATUC_CURR_OUT_PWR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 5, 1, data) + +#define ATUC_CURR_ATTR_FLAG 0x20 /* BIT 5 */ +#define ATUC_CURR_ATTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 0, 2, data) + + +/* adslAturPhysTable Flags */ +#define ATUR_PHY_SER_NUM_FLAG 0x1 /* BIT 0th position */ +#define ATUR_PHY_SER_NUM_FLAG_MAKECMV1 makeCMV(H2D_CMV_READ, INFO, 62, 0, 12, data) +#define ATUR_PHY_SER_NUM_FLAG_MAKECMV2 makeCMV(H2D_CMV_READ, INFO, 62, 12, 4, data) + +#define ATUR_PHY_VENDOR_ID_FLAG 0x2 /* BIT 1 */ +#define ATUR_PHY_VENDOR_ID_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 65, 0, 4, data) + +#define ATUR_PHY_VER_NUM_FLAG 0x4 /* BIT 2 */ +#define ATUR_PHY_VER_NUM_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 61, 0, 8, data) + +#define ATUR_SNRMGN_FLAG 0x8 +#define ATUR_SNRMGN_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 4, 1, data) + +#define ATUR_ATTN_FLAG 0x10 +#define ATUR_ATTN_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 2, 1, data) + +#define ATUR_CURR_STAT_FLAG 0x20 /* BIT 3 */ + +#define ATUR_CURR_OUT_PWR_FLAG 0x40 /* BIT 4 */ +#define ATUR_CURR_OUT_PWR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 5, 1, data) + +#define ATUR_CURR_ATTR_FLAG 0x80 /* BIT 5 */ +#define ATUR_CURR_ATTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 0, 2, data) + +/* adslAtucChanTable Flags */ +#define ATUC_CHAN_INTLV_DELAY_FLAG 0x1 /* BIT 0th position */ +#define ATUC_CHAN_INTLV_DELAY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 3, 1, 1, data) + +#define ATUC_CHAN_CURR_TX_RATE_FLAG 0x2 /* BIT 1 */ +#define ATUC_CHAN_CURR_TX_RATE_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 1, 0, 2, data) + +#define ATUC_CHAN_PREV_TX_RATE_FLAG 0x4 /* BIT 2 */ + +/* adslAturChanTable Flags */ +#define ATUR_CHAN_INTLV_DELAY_FLAG 0x1 /* BIT 0th position */ +#define ATUR_CHAN_INTLV_DELAY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 2, 1, 1, data) + +#define ATUR_CHAN_CURR_TX_RATE_FLAG 0x2 /* BIT 1 */ +#define ATUR_CHAN_CURR_TX_RATE_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 0, 0, 2, data) + +#define ATUR_CHAN_PREV_TX_RATE_FLAG 0x4 /* BIT 2 */ + +#define ATUR_CHAN_CRC_BLK_LEN_FLAG 0x8 /* BIT 3 */ + +/* adslAtucPerfDataTable Flags */ +#define ATUC_PERF_LOFS_FLAG 0x1 /* BIT 0th position */ +#define ATUC_PERF_LOSS_FLAG 0x2 /* BIT 1 */ +#define ATUC_PERF_LO_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 0, 0, 1, data) +#define ATUC_PERF_ESS_FLAG 0x4 /* BIT 2 */ +#define ATUC_PERF_ESS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 7, 0, 1, data) +#define ATUC_PERF_INITS_FLAG 0x8 /* BIT 3 */ +#define ATUC_PERF_VALID_INTVLS_FLAG 0x10 /* BIT 4 */ +#define ATUC_PERF_INVALID_INTVLS_FLAG 0x20 /* BIT 5 */ +#define ATUC_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */ +#define ATUC_PERF_CURR_15MIN_LOFS_FLAG 0x80 /* BIT 7 */ +#define ATUC_PERF_CURR_15MIN_LOSS_FLAG 0x100 /* BIT 8 */ +#define ATUC_PERF_CURR_15MIN_ESS_FLAG 0x200 /* BIT 9 */ +#define ATUC_PERF_CURR_15MIN_INIT_FLAG 0x400 /* BIT 10 */ +#define ATUC_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11 */ +#define ATUC_PERF_CURR_1DAY_LOFS_FLAG 0x1000 /* BIT 12 */ +#define ATUC_PERF_CURR_1DAY_LOSS_FLAG 0x2000 /* BIT 13 */ +#define ATUC_PERF_CURR_1DAY_ESS_FLAG 0x4000 /* BIT 14 */ +#define ATUC_PERF_CURR_1DAY_INIT_FLAG 0x8000 /* BIT 15 */ +#define ATUC_PERF_PREV_1DAY_MON_SEC_FLAG 0x10000 /* BIT 16 */ +#define ATUC_PERF_PREV_1DAY_LOFS_FLAG 0x20000 /* BIT 17 */ +#define ATUC_PERF_PREV_1DAY_LOSS_FLAG 0x40000 /* BIT 18 */ +#define ATUC_PERF_PREV_1DAY_ESS_FLAG 0x80000 /* BIT 19 */ +#define ATUC_PERF_PREV_1DAY_INITS_FLAG 0x100000 /* BIT 20 */ + +/* adslAturPerfDataTable Flags */ +#define ATUR_PERF_LOFS_FLAG 0x1 /* BIT 0th position */ +#define ATUR_PERF_LOSS_FLAG 0x2 /* BIT 1 */ +#define ATUR_PERF_LPR_FLAG 0x4 /* BIT 2 */ +#define ATUR_PERF_LO_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 1, 0, 1, data) +#define ATUR_PERF_ESS_FLAG 0x8 /* BIT 3 */ +#define ATUR_PERF_ESS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 33, 0, 1, data) +#define ATUR_PERF_VALID_INTVLS_FLAG 0x10 /* BIT 4 */ +#define ATUR_PERF_INVALID_INTVLS_FLAG 0x20 /* BIT 5 */ +#define ATUR_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */ +#define ATUR_PERF_CURR_15MIN_LOFS_FLAG 0x80 /* BIT 7 */ +#define ATUR_PERF_CURR_15MIN_LOSS_FLAG 0x100 /* BIT 8 */ +#define ATUR_PERF_CURR_15MIN_LPR_FLAG 0x200 /* BIT 9 */ +#define ATUR_PERF_CURR_15MIN_ESS_FLAG 0x400 /* BIT 10 */ +#define ATUR_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11 */ +#define ATUR_PERF_CURR_1DAY_LOFS_FLAG 0x1000 /* BIT 12 */ +#define ATUR_PERF_CURR_1DAY_LOSS_FLAG 0x2000 /* BIT 13 */ +#define ATUR_PERF_CURR_1DAY_LPR_FLAG 0x4000 /* BIT 14 */ +#define ATUR_PERF_CURR_1DAY_ESS_FLAG 0x8000 /* BIT 15 */ +#define ATUR_PERF_PREV_1DAY_MON_SEC_FLAG 0x10000 /* BIT 16 */ +#define ATUR_PERF_PREV_1DAY_LOFS_FLAG 0x20000 /* BIT 17 */ +#define ATUR_PERF_PREV_1DAY_LOSS_FLAG 0x40000 /* BIT 18 */ +#define ATUR_PERF_PREV_1DAY_LPR_FLAG 0x80000 /* BIT 19 */ +#define ATUR_PERF_PREV_1DAY_ESS_FLAG 0x100000 /* BIT 20 */ + +/* adslAtucIntervalTable Flags */ +#define ATUC_INTVL_LOF_FLAG 0x1 /* BIT 0th position */ +#define ATUC_INTVL_LOS_FLAG 0x2 /* BIT 1 */ +#define ATUC_INTVL_ESS_FLAG 0x4 /* BIT 2 */ +#define ATUC_INTVL_INIT_FLAG 0x8 /* BIT 3 */ +#define ATUC_INTVL_VALID_DATA_FLAG 0x10 /* BIT 4 */ + +/* adslAturIntervalTable Flags */ +#define ATUR_INTVL_LOF_FLAG 0x1 /* BIT 0th position */ +#define ATUR_INTVL_LOS_FLAG 0x2 /* BIT 1 */ +#define ATUR_INTVL_LPR_FLAG 0x4 /* BIT 2 */ +#define ATUR_INTVL_ESS_FLAG 0x8 /* BIT 3 */ +#define ATUR_INTVL_VALID_DATA_FLAG 0x10 /* BIT 4 */ + +/* adslAtucChanPerfDataTable Flags */ +#define ATUC_CHAN_RECV_BLK_FLAG 0x01 /* BIT 0th position */ +#define ATUC_CHAN_TX_BLK_FLAG 0x02 /* BIT 1 */ +#define ATUC_CHAN_CORR_BLK_FLAG 0x04 /* BIT 2 */ +#define ATUC_CHAN_UNCORR_BLK_FLAG 0x08 /* BIT 3 */ +#define ATUC_CHAN_PERF_VALID_INTVL_FLAG 0x10 /* BIT 4 */ +#define ATUC_CHAN_PERF_INVALID_INTVL_FLAG 0x20 /* BIT 5 */ +#define ATUC_CHAN_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */ +#define ATUC_CHAN_PERF_CURR_15MIN_RECV_BLK_FLAG 0x80 /* BIT 7 */ +#define ATUC_CHAN_PERF_CURR_15MIN_TX_BLK_FLAG 0x100 /* BIT 8 */ +#define ATUC_CHAN_PERF_CURR_15MIN_CORR_BLK_FLAG 0x200 /* BIT 9 */ +#define ATUC_CHAN_PERF_CURR_15MIN_UNCORR_BLK_FLAG 0x400 /* BIT 10 */ +#define ATUC_CHAN_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11*/ +#define ATUC_CHAN_PERF_CURR_1DAY_RECV_BLK_FLAG 0x1000 /* BIT 12 */ +#define ATUC_CHAN_PERF_CURR_1DAY_TX_BLK_FLAG 0x2000 /* BIT 13 */ +#define ATUC_CHAN_PERF_CURR_1DAY_CORR_BLK_FLAG 0x4000 /* BIT 14 */ +#define ATUC_CHAN_PERF_CURR_1DAY_UNCORR_BLK_FLAG 0x8000 /* BIT 15 */ +#define ATUC_CHAN_PERF_PREV_1DAY_MONI_SEC_FLAG 0x10000 /* BIT 16 */ +#define ATUC_CHAN_PERF_PREV_1DAY_RECV_BLK_FLAG 0x20000 /* BIT 17 */ +#define ATUC_CHAN_PERF_PREV_1DAY_TX_BLK_FLAG 0x40000 /* BIT 18 */ +#define ATUC_CHAN_PERF_PREV_1DAY_CORR_BLK_FLAG 0x80000 /* BIT 19 */ +#define ATUC_CHAN_PERF_PREV_1DAY_UNCORR_BLK_FLAG 0x100000 /* BIT 20 */ + + +/* adslAturChanPerfDataTable Flags */ +#define ATUR_CHAN_RECV_BLK_FLAG 0x01 /* BIT 0th position */ +#define ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_LSW makeCMV(H2D_CMV_READ, PLAM, 20, 0, 1, data) +#define ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_MSW makeCMV(H2D_CMV_READ, PLAM, 21, 0, 1, data) +#define ATUR_CHAN_TX_BLK_FLAG 0x02 /* BIT 1 */ +#define ATUR_CHAN_TX_BLK_FLAG_MAKECMV_LSW makeCMV(H2D_CMV_READ, PLAM, 20, 0, 1, data) +#define ATUR_CHAN_TX_BLK_FLAG_MAKECMV_MSW makeCMV(H2D_CMV_READ, PLAM, 21, 0, 1, data) +#define ATUR_CHAN_CORR_BLK_FLAG 0x04 /* BIT 2 */ +#define ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_INTL makeCMV(H2D_CMV_READ, PLAM, 3, 0, 1, data) +#define ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_FAST makeCMV(H2D_CMV_READ, PLAM, 3, 1, 1, data) +#define ATUR_CHAN_UNCORR_BLK_FLAG 0x08 /* BIT 3 */ +#define ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_INTL makeCMV(H2D_CMV_READ, PLAM, 2, 0, 1, data) +#define ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_FAST makeCMV(H2D_CMV_READ, PLAM, 2, 1, 1, data) +#define ATUR_CHAN_PERF_VALID_INTVL_FLAG 0x10 /* BIT 4 */ +#define ATUR_CHAN_PERF_INVALID_INTVL_FLAG 0x20 /* BIT 5 */ +#define ATUR_CHAN_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */ +#define ATUR_CHAN_PERF_CURR_15MIN_RECV_BLK_FLAG 0x80 /* BIT 7 */ +#define ATUR_CHAN_PERF_CURR_15MIN_TX_BLK_FLAG 0x100 /* BIT 8 */ +#define ATUR_CHAN_PERF_CURR_15MIN_CORR_BLK_FLAG 0x200 /* BIT 9 */ +#define ATUR_CHAN_PERF_CURR_15MIN_UNCORR_BLK_FLAG 0x400 /* BIT 10 */ +#define ATUR_CHAN_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11 */ +#define ATUR_CHAN_PERF_CURR_1DAY_RECV_BLK_FLAG 0x1000 /* BIT 12 */ +#define ATUR_CHAN_PERF_CURR_1DAY_TX_BLK_FLAG 0x2000 /* BIT 13 */ +#define ATUR_CHAN_PERF_CURR_1DAY_CORR_BLK_FLAG 0x4000 /* BIT 14 */ +#define ATUR_CHAN_PERF_CURR_1DAY_UNCORR_BLK_FLAG 0x8000 /* BIT 15 */ +#define ATUR_CHAN_PERF_PREV_1DAY_MONI_SEC_FLAG 0x10000 /* BIT 16 */ +#define ATUR_CHAN_PERF_PREV_1DAY_RECV_BLK_FLAG 0x20000 /* BIT 17 */ +#define ATUR_CHAN_PERF_PREV_1DAY_TRANS_BLK_FLAG 0x40000 /* BIT 18 */ +#define ATUR_CHAN_PERF_PREV_1DAY_CORR_BLK_FLAG 0x80000 /* BIT 19 */ +#define ATUR_CHAN_PERF_PREV_1DAY_UNCORR_BLK_FLAG 0x100000 /* BIT 20 */ + +/* adslAtucChanIntervalTable Flags */ +#define ATUC_CHAN_INTVL_NUM_FLAG 0x1 /* BIT 0th position */ +#define ATUC_CHAN_INTVL_RECV_BLK_FLAG 0x2 /* BIT 1 */ +#define ATUC_CHAN_INTVL_TX_BLK_FLAG 0x4 /* BIT 2 */ +#define ATUC_CHAN_INTVL_CORR_BLK_FLAG 0x8 /* BIT 3 */ +#define ATUC_CHAN_INTVL_UNCORR_BLK_FLAG 0x10 /* BIT 4 */ +#define ATUC_CHAN_INTVL_VALID_DATA_FLAG 0x20 /* BIT 5 */ + +/* adslAturChanIntervalTable Flags */ +#define ATUR_CHAN_INTVL_NUM_FLAG 0x1 /* BIT 0th Position */ +#define ATUR_CHAN_INTVL_RECV_BLK_FLAG 0x2 /* BIT 1 */ +#define ATUR_CHAN_INTVL_TX_BLK_FLAG 0x4 /* BIT 2 */ +#define ATUR_CHAN_INTVL_CORR_BLK_FLAG 0x8 /* BIT 3 */ +#define ATUR_CHAN_INTVL_UNCORR_BLK_FLAG 0x10 /* BIT 4 */ +#define ATUR_CHAN_INTVL_VALID_DATA_FLAG 0x20 /* BIT 5 */ + +/* adslLineAlarmConfProfileTable Flags */ +#define ATUC_THRESH_15MIN_LOFS_FLAG 0x01 /* BIT 0th position */ +#define ATUC_THRESH_15MIN_LOSS_FLAG 0x02 /* BIT 1 */ +#define ATUC_THRESH_15MIN_ESS_FLAG 0x04 /* BIT 2 */ +#define ATUC_THRESH_FAST_RATEUP_FLAG 0x08 /* BIT 3 */ +#define ATUC_THRESH_INTERLEAVE_RATEUP_FLAG 0x10 /* BIT 4 */ +#define ATUC_THRESH_FAST_RATEDOWN_FLAG 0x20 /* BIT 5 */ +#define ATUC_THRESH_INTERLEAVE_RATEDOWN_FLAG 0x40 /* BIT 6 */ +#define ATUC_INIT_FAILURE_TRAP_ENABLE_FLAG 0x80 /* BIT 7 */ +#define ATUR_THRESH_15MIN_LOFS_FLAG 0x100 /* BIT 8 */ +#define ATUR_THRESH_15MIN_LOSS_FLAG 0x200 /* BIT 9 */ +#define ATUR_THRESH_15MIN_LPRS_FLAG 0x400 /* BIT 10 */ +#define ATUR_THRESH_15MIN_ESS_FLAG 0x800 /* BIT 11 */ +#define ATUR_THRESH_FAST_RATEUP_FLAG 0x1000 /* BIT 12 */ +#define ATUR_THRESH_INTERLEAVE_RATEUP_FLAG 0x2000 /* BIT 13 */ +#define ATUR_THRESH_FAST_RATEDOWN_FLAG 0x4000 /* BIT 14 */ +#define ATUR_THRESH_INTERLEAVE_RATEDOWN_FLAG 0x8000 /* BIT 15 */ +#define LINE_ALARM_CONF_PROFILE_ROWSTATUS_FLAG 0x10000 /* BIT 16 */ + + +/* adslAturTraps Flags */ +#define ATUC_PERF_LOFS_THRESH_FLAG 0x1 /* BIT 0th position */ +#define ATUC_PERF_LOSS_THRESH_FLAG 0x2 /* BIT 1 */ +#define ATUC_PERF_ESS_THRESH_FLAG 0x4 /* BIT 2 */ +#define ATUC_RATE_CHANGE_FLAG 0x8 /* BIT 3 */ +#define ATUR_PERF_LOFS_THRESH_FLAG 0x10 /* BIT 4 */ +#define ATUR_PERF_LOSS_THRESH_FLAG 0x20 /* BIT 5 */ +#define ATUR_PERF_LPRS_THRESH_FLAG 0x40 /* BIT 6 */ +#define ATUR_PERF_ESS_THRESH_FLAG 0x80 /* BIT 7 */ +#define ATUR_RATE_CHANGE_FLAG 0x100 /* BIT 8 */ + +//RFC- 3440 FLAG DEFINITIONS + +#ifdef AMAZON_MEI_MIB_RFC3440 +/* adslLineExtTable flags */ +#define ATUC_LINE_TRANS_CAP_FLAG 0x1 /* BIT 0th position */ +#define ATUC_LINE_TRANS_CAP_FLAG_MAKECMV makeCMV(H2D_CMV_READ,INFO, 67, 0, 1, data) +#define ATUC_LINE_TRANS_CONFIG_FLAG 0x2 /* BIT 1 */ +#define ATUC_LINE_TRANS_CONFIG_FLAG_MAKECMV makeCMV(H2D_CMV_READ,INFO, 67, 0, 1, data) +#define ATUC_LINE_TRANS_CONFIG_FLAG_MAKECMV_WR makeCMV(H2D_CMV_WRITE,INFO, 67, 0, 1, data) +#define ATUC_LINE_TRANS_ACTUAL_FLAG 0x4 /* BIT 2 */ +#define ATUC_LINE_TRANS_ACTUAL_FLAG_MAKECMV makeCMV(H2D_CMV_READ,STAT, 1, 0, 1, data) +#define LINE_GLITE_POWER_STATE_FLAG 0x8 /* BIT 3 */ +#define LINE_GLITE_POWER_STATE_FLAG_MAKECMV makeCMV(H2D_CMV_READ,STAT, 0, 0, 1, data) + +/* adslAtucPerfDataExtTable flags */ +#define ATUC_PERF_STAT_FASTR_FLAG 0x1 /* BIT 0th position */ +#define ATUC_PERF_STAT_FASTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, data) +#define ATUC_PERF_STAT_FAILED_FASTR_FLAG 0x2 /* BIT 1 */ +#define ATUC_PERF_STAT_FAILED_FASTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, data) +#define ATUC_PERF_STAT_SESL_FLAG 0X4 /* BIT 2 */ +#define ATUC_PERF_STAT_SESL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 8, 0, 1, data) +#define ATUC_PERF_STAT_UASL_FLAG 0X8 /* BIT 3 */ +#define ATUC_PERF_STAT_UASL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 10, 0, 1, data) +#define ATUC_PERF_CURR_15MIN_FASTR_FLAG 0X10 /* BIT 4 */ +#define ATUC_PERF_CURR_15MIN_FAILED_FASTR_FLAG 0X20 /* BIT 5 */ +#define ATUC_PERF_CURR_15MIN_SESL_FLAG 0X40 /* BIT 6 */ +#define ATUC_PERF_CURR_15MIN_UASL_FLAG 0X80 /* BIT 7 */ +#define ATUC_PERF_CURR_1DAY_FASTR_FLAG 0X100 /* BIT 8 */ +#define ATUC_PERF_CURR_1DAY_FAILED_FASTR_FLAG 0X200 /* BIT 9 */ +#define ATUC_PERF_CURR_1DAY_SESL_FLAG 0X400 /* BIT 10 */ +#define ATUC_PERF_CURR_1DAY_UASL_FLAG 0X800 /* BIT 11 */ +#define ATUC_PERF_PREV_1DAY_FASTR_FLAG 0X1000 /* BIT 12 */ +#define ATUC_PERF_PREV_1DAY_FAILED_FASTR_FLAG 0X2000 /* BIT 13 */ +#define ATUC_PERF_PREV_1DAY_SESL_FLAG 0X4000 /* BIT 14 */ +#define ATUC_PERF_PREV_1DAY_UASL_FLAG 0X8000 /* BIT 15 */ + +/* adslAturPerfDataExtTable */ +#define ATUR_PERF_STAT_SESL_FLAG 0X1 /* BIT 0th position */ +#define ATUR_PERF_STAT_SESL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 34, 0, 1, data) +#define ATUR_PERF_STAT_UASL_FLAG 0X2 /* BIT 1 */ +#define ATUR_PERF_STAT_UASL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 36, 0, 1, data) +#define ATUR_PERF_CURR_15MIN_SESL_FLAG 0X4 /* BIT 2 */ +#define ATUR_PERF_CURR_15MIN_UASL_FLAG 0X8 /* BIT 3 */ +#define ATUR_PERF_CURR_1DAY_SESL_FLAG 0X10 /* BIT 4 */ +#define ATUR_PERF_CURR_1DAY_UASL_FLAG 0X20 /* BIT 5 */ +#define ATUR_PERF_PREV_1DAY_SESL_FLAG 0X40 /* BIT 6 */ +#define ATUR_PERF_PREV_1DAY_UASL_FLAG 0X80 /* BIT 7 */ + +/* adslAutcIntervalExtTable flags */ +#define ATUC_INTERVAL_FASTR_FLAG 0x1 /* Bit 0 */ +#define ATUC_INTERVAL_FAILED_FASTR_FLAG 0x2 /* Bit 1 */ +#define ATUC_INTERVAL_SESL_FLAG 0x4 /* Bit 2 */ +#define ATUC_INTERVAL_UASL_FLAG 0x8 /* Bit 3 */ + +/* adslAturIntervalExtTable */ +#define ATUR_INTERVAL_SESL_FLAG 0X1 /* BIT 0th position */ +#define ATUR_INTERVAL_UASL_FLAG 0X2 /* BIT 1 */ + +/* adslAlarmConfProfileExtTable */ +#define ATUC_THRESH_15MIN_FAILED_FASTR_FLAG 0X1/* BIT 0th position */ +#define ATUC_THRESH_15MIN_SESL_FLAG 0X2 /* BIT 1 */ +#define ATUC_THRESH_15MIN_UASL_FLAG 0X4 /* BIT 2 */ +#define ATUR_THRESH_15MIN_SESL_FLAG 0X8 /* BIT 3 */ +#define ATUR_THRESH_15MIN_UASL_FLAG 0X10 /* BIT 4 */ + +/* adslAturExtTraps */ +#define ATUC_15MIN_FAILED_FASTR_TRAP_FLAG 0X1 /* BIT 0th position */ +#define ATUC_15MIN_SESL_TRAP_FLAG 0X2 /* BIT 1 */ +#define ATUC_15MIN_UASL_TRAP_FLAG 0X4 /* BIT 2 */ +#define ATUR_15MIN_SESL_TRAP_FLAG 0X8 /* BIT 3 */ +#define ATUR_15MIN_UASL_TRAP_FLAG 0X10 /* BIT 4 */ + +// 603221:tc.chen start +/* adslLineStatus Flags */ +#define LINE_STAT_MODEM_STATUS_FLAG 0x1 /* BIT 0th position */ +#define LINE_STAT_MODEM_STATUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, data) +#define LINE_STAT_MODE_SEL_FLAG 0x2 /* BIT 1 */ +#define LINE_STAT_MODE_SEL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 1, 0, 1, data) +#define LINE_STAT_TRELLCOD_ENABLE_FLAG 0x4 /* BIT 2 */ +#define LINE_STAT_TRELLCOD_ENABLE_FLAG_MAKECMV makeCMV(H2D_CMV_READ, OPTN, 2, 0, 1, data) +#define LINE_STAT_LATENCY_FLAG 0x8 /* BIT 3 */ +#define LINE_STAT_LATENCY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 12, 0, 1, data) + +/* adslLineRate Flags */ +#define LINE_RATE_DATA_RATEDS_FLAG 0x1 /* BIT 0th position */ +#define LINE_RATE_DATA_RATEDS_FLAG_ADSL1_LP0_MAKECMV makeCMV(H2D_CMV_READ, RATE, 1, 0, 2, data) +#define LINE_RATE_DATA_RATEDS_FLAG_ADSL1_LP1_MAKECMV makeCMV(H2D_CMV_READ, RATE, 1, 2, 2, data) + + +#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_RP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 12, 0, 1, data) +#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_MP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 13, 0, 1, data) +#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_LP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 14, 0, 1, data) +#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_TP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 15, 0, 1, data) +#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_KP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 17, 0, 2, data) + +#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_RP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 12, 1, 1, data) +#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_MP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 13, 1, 1, data) +#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_LP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 14, 1, 1, data) +#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_TP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 15, 1, 1, data) +#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_KP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 17, 2, 2, data) + +#define LINE_RATE_DATA_RATEUS_FLAG 0x2 /* BIT 1 */ +#define LINE_RATE_DATA_RATEUS_FLAG_ADSL1_LP0_MAKECMV makeCMV(H2D_CMV_READ, RATE, 0, 0, 2, data) +#define LINE_RATE_DATA_RATEUS_FLAG_ADSL1_LP1_MAKECMV makeCMV(H2D_CMV_READ, RATE, 0, 2, 2, data) + + +#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_RP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 23, 0, 1, data) +#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_MP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 24, 0, 1, data) +#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_LP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 25, 0, 1, data) +#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_TP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 26, 0, 1, data) +#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_KP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 28, 0, 2, data) + +#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_RP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 23, 1, 1, data) +#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_MP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 24, 1, 1, data) +#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_LP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 25, 1, 1, data) +#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_TP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 26, 1, 1, data) +#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_KP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 28, 2, 2, data) + +#define LINE_RATE_ATTNDRDS_FLAG 0x4 /* BIT 2 */ +#define LINE_RATE_ATTNDRDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 4, 2, data) + +#define LINE_RATE_ATTNDRUS_FLAG 0x8 /* BIT 3 */ +#define LINE_RATE_ATTNDRUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 4, 2, data) + +/* adslLineInformation Flags */ +#define LINE_INFO_INTLV_DEPTHDS_FLAG 0x1 /* BIT 0th position */ +#define LINE_INFO_INTLV_DEPTHDS_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 27, 0, 1, data) +#define LINE_INFO_INTLV_DEPTHDS_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 27, 1, 1, data) +#define LINE_INFO_INTLV_DEPTHUS_FLAG 0x2 /* BIT 1 */ +#define LINE_INFO_INTLV_DEPTHUS_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 16, 0, 1, data) +#define LINE_INFO_INTLV_DEPTHUS_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 16, 1, 1, data) +#define LINE_INFO_LATNDS_FLAG 0x4 /* BIT 2 */ +#define LINE_INFO_LATNDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 1, 1, data) +#define LINE_INFO_LATNUS_FLAG 0x8 /* BIT 3 */ +#define LINE_INFO_LATNUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 1, 1, data) +#define LINE_INFO_SATNDS_FLAG 0x10 /* BIT 4 */ +#define LINE_INFO_SATNDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 2, 1, data) +#define LINE_INFO_SATNUS_FLAG 0x20 /* BIT 5 */ +#define LINE_INFO_SATNUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 2, 1, data) +#define LINE_INFO_SNRMNDS_FLAG 0x40 /* BIT 6 */ +#define LINE_INFO_SNRMNDS_FLAG_ADSL1_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 3, 1, data) +#define LINE_INFO_SNRMNDS_FLAG_ADSL2_MAKECMV makeCMV(H2D_CMV_READ, RATE, 3, 0, 1, data) +#define LINE_INFO_SNRMNDS_FLAG_ADSL2PLUS_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 46, 0, 1, data) +#define LINE_INFO_SNRMNUS_FLAG 0x80 /* BIT 7 */ +#define LINE_INFO_SNRMNUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 3, 1, data) +#define LINE_INFO_ACATPDS_FLAG 0x100 /* BIT 8 */ +#define LINE_INFO_ACATPDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 6, 1, data) +#define LINE_INFO_ACATPUS_FLAG 0x200 /* BIT 9 */ +#define LINE_INFO_ACATPUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 6, 1, data) + +/* adslNearEndPerformanceStats Flags */ +#define NEAREND_PERF_SUPERFRAME_FLAG_LSW_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 20, 0, 1, data) +#define NEAREND_PERF_SUPERFRAME_FLAG_MSW_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 21, 0, 1, data) +#define NEAREND_PERF_SUPERFRAME_FLAG 0x1 /* BIT 0th position */ +#define NEAREND_PERF_LOS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 0, 0, 1, data) +#define NEAREND_PERF_LOS_FLAG 0x2 /* BIT 1 */ +#define NEAREND_PERF_LOF_FLAG 0x4 /* BIT 2 */ +#define NEAREND_PERF_LPR_FLAG 0x8 /* BIT 3 */ +#define NEAREND_PERF_NCD_FLAG 0x10 /* BIT 4 */ +#define NEAREND_PERF_LCD_FLAG 0x20 /* BIT 5 */ +#define NEAREND_PERF_CRC_FLAG 0x40 /* BIT 6 */ +#define NEAREND_PERF_CRC_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 2, 0, 1, data) +#define NEAREND_PERF_CRC_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 2, 1, 1, data) +#define NEAREND_PERF_RSCORR_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 3, 0, 1, data) +#define NEAREND_PERF_RSCORR_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 3, 1, 1, data) +#define NEAREND_PERF_RSCORR_FLAG 0x80 /* BIT 7 */ +#define NEAREND_PERF_FECS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 6, 0, 1, data) +#define NEAREND_PERF_FECS_FLAG 0x100 /* BIT 8 */ +#define NEAREND_PERF_ES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 7, 0, 1, data) +#define NEAREND_PERF_ES_FLAG 0x200 /* BIT 9 */ +#define NEAREND_PERF_SES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 8, 0, 1, data) +#define NEAREND_PERF_SES_FLAG 0x400 /* BIT 10 */ +#define NEAREND_PERF_LOSS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 9, 0, 1, data) +#define NEAREND_PERF_LOSS_FLAG 0x800 /* BIT 11 */ +#define NEAREND_PERF_UAS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 10, 0, 1, data) +#define NEAREND_PERF_UAS_FLAG 0x1000 /* BIT 12 */ +#define NEAREND_PERF_HECERR_FLAG_BC0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 11, 0, 2, data) +#define NEAREND_PERF_HECERR_FLAG_BC1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 11, 2, 2, data) +#define NEAREND_PERF_HECERR_FLAG 0x2000 /* BIT 13 */ + +/* adslFarEndPerformanceStats Flags */ +#define FAREND_PERF_LOS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 1, 0, 1, data) +#define FAREND_PERF_LOS_FLAG 0x1 /* BIT 0th position */ +#define FAREND_PERF_LOF_FLAG 0x2 /* BIT 1 */ +#define FAREND_PERF_LPR_FLAG 0x4 /* BIT 2 */ +#define FAREND_PERF_NCD_FLAG 0x8 /* BIT 3 */ +#define FAREND_PERF_LCD_FLAG 0x10 /* BIT 4 */ +#define FAREND_PERF_CRC_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 24, 0, 1, data) +#define FAREND_PERF_CRC_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 24, 1, 1, data) +#define FAREND_PERF_CRC_FLAG 0x20 /* BIT 5 */ +#define FAREND_PERF_RSCORR_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 28, 0, 1, data) +#define FAREND_PERF_RSCORR_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 28, 1, 1, data) +#define FAREND_PERF_RSCORR_FLAG 0x40 /* BIT 6 */ +#define FAREND_PERF_FECS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 32, 0, 1, data) +#define FAREND_PERF_FECS_FLAG 0x80 /* BIT 7 */ +#define FAREND_PERF_ES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 33, 0, 1, data) +#define FAREND_PERF_ES_FLAG 0x100 /* BIT 8 */ +#define FAREND_PERF_SES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 34, 0, 1, data) +#define FAREND_PERF_SES_FLAG 0x200 /* BIT 9 */ +#define FAREND_PERF_LOSS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 35, 0, 1, data) +#define FAREND_PERF_LOSS_FLAG 0x400 /* BIT 10 */ +#define FAREND_PERF_UAS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 36, 0, 1, data) +#define FAREND_PERF_UAS_FLAG 0x800 /* BIT 11 */ +#define FAREND_PERF_HECERR_FLAG_BC0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 37, 0, 2, data) +#define FAREND_PERF_HECERR_FLAG_BC1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 37, 2, 2, data) +#define FAREND_PERF_HECERR_FLAG 0x1000 /* BIT 12 */ +// 603221:tc.chen end +/* TR-69 related additional parameters - defines */ +/* Defines for struct adslATURSubcarrierInfo */ +#define NEAREND_HLINSC 0x1 +#define NEAREND_HLINSC_MAKECMV(mode) makeCMV(mode, INFO, 71, 2, 1, data) +#define NEAREND_HLINPS 0x2 +#define NEAREND_HLINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 73, idx, size, data) +#define NEAREND_HLOGMT 0x4 +#define NEAREND_HLOGMT_MAKECMV(mode) makeCMV(mode, INFO, 80, 0, 1, data) +#define NEAREND_HLOGPS 0x8 +#define NEAREND_HLOGPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 75, idx, size, data) +#define NEAREND_QLNMT 0x10 +#define NEAREND_QLNMT_MAKECMV(mode) makeCMV(mode, INFO, 80, 1, 1, data) +#define NEAREND_QLNPS 0x20 +#define NEAREND_QLNPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 77, idx, size, data) +#define NEAREND_SNRMT 0x40 +#define NEAREND_SNRMT_MAKECMV(mode) makeCMV(mode, INFO, 80, 2, 1, data) +#define NEAREND_SNRPS 0x80 +#define NEAREND_SNRPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 78, idx, size, data) +#define NEAREND_BITPS 0x100 +#define NEAREND_BITPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 22, idx, size, data) +#define NEAREND_GAINPS 0x200 +#define NEAREND_GAINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 24, idx, size, data) + +/* Defines for struct adslATUCSubcarrierInfo */ +#define FAREND_HLINSC 0x1 +#define FAREND_HLINSC_MAKECMV(mode) makeCMV(mode, INFO, 70, 0, 1, data) +#define FAREND_HLINPS 0x2 +#define FAREND_HLINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 72, idx, size, data) +#define FAREND_HLOGMT 0x4 +#define FAREND_HLOGMT_MAKECMV(mode) makeCMV(mode, INFO, 79, 0, 1, data) +#define FAREND_HLOGPS 0x8 +#define FAREND_HLOGPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 74, idx, size, data) +#define FAREND_QLNMT 0x10 +#define FAREND_QLNMT_MAKECMV(mode) makeCMV(mode, INFO, 79, 1, 1, data) +#define FAREND_QLNPS 0x20 +#define FAREND_QLNPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 76, idx, size, data) +#define FAREND_SNRMT 0x40 +#define FAREND_SNRMT_MAKECMV(mode) makeCMV(mode, INFO, 79, 2, 1, data) +#define FAREND_SNRPS 0x80 +#define FAREND_SNRPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 10, idx, size, data) +#define FAREND_BITPS 0x100 +#define FAREND_BITPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 23, idx, size, data) +#define FAREND_GAINPS 0x200 +#define FAREND_GAINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 25, idx, size, data) + + +// GET_ADSL_POWER_SPECTRAL_DENSITY +#define NOMPSD_US_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 0, 1, data) +#define NOMPSD_DS_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 1, 1, data) +#define PCB_US_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 6, 1, data) +#define PCB_DS_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 7, 1, data) +#define RMSGI_US_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 10, 1, data) +#define RMSGI_DS_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 11, 1, data) + + +#endif +/////////////////////////////////////////////////Macro Definitions ? FLAG Setting & Testing + +#define SET_FLAG(flags, flag_val) ((*flags) = ((*flags) | flag_val)) +// -- This macro sets the flags with the flag_val. Here flags is passed as a pointer + +#define IS_FLAG_SET(flags, test_flag) (((*flags) & (test_flag)) == (test_flag)? test_flag:0) +// -- This macro verifies whether test_flag has been set in flags. Here flags is passed as a pointer + + +#define CLR_FLAG(flags, flag_bit) ((*flags) = (*flags) & (~flag_bit)) +// -- This macro resets the specified flag_bit in the flags. Here flags is passed as a pointer + + +////////////////////////////////////////////////DATA STRUCTURES ORGANIZATION + +//Here are the data structures used for accessing mib parameters. The ioctl call includes the third parameter as a void pointer. This parameter has to be type-casted in the driver code to the corresponding structure depending upon the command type. For Ex: consider the ioctl used to get the adslLineCode type, ioctl(fd,GET_ADSL_LINE_CODE,void *struct_adslLineTableEntry). In the driver code we check on the type of the command, i.e GET_ADSL_LINE_CODE and type-cast the void pointer to struct adslLineTableEntry type. + // +#define u32 unsigned int +#define u16 unsigned short +#define s16 short +#define u8 unsigned char + + +typedef u32 AdslPerfTimeElapsed; +typedef u32 AdslPerfPrevDayCount; +typedef u32 PerfCurrentCount; +typedef u32 PerfIntervalCount; +typedef u32 AdslPerfCurrDayCount; + + +//ioctl(int fd, GET_ADSL_LINE_CODE, void *struct_adslLineTableEntry) + +typedef struct adslLineTableEntry { + int ifIndex; + int adslLineCode; + u8 flags; +} adslLineTableEntry; + +#ifdef AMAZON_MEI_MIB_RFC3440 +typedef struct adslLineExtTableEntry { + int ifIndex; + u16 adslLineTransAtucCap; + u16 adslLineTransAtucConfig; + u16 adslLineTransAtucActual; + int adslLineGlitePowerState; + u32 flags; +}adslLineExtTableEntry; +#endif +//ioctl(int fd, GET_ADSL_ATUC_PHY, void *struct_adslAtucPhysEntry) + +typedef struct adslVendorId { + u16 country_code; + u_char provider_id[4]; /* Ascii characters */ + u_char revision_info[2]; +}adslVendorId; + + +typedef struct adslAtucPhysEntry { + int ifIndex; + char serial_no[32]; + union { + char vendor_id[16]; + adslVendorId vendor_info; + } vendor_id; + + char version_no[16]; + u32 status; + int outputPwr; + u32 attainableRate; + u8 flags; +} adslAtucPhysEntry; + + +//ioctl(int fd, GET_ADSL_ATUR_PHY, void *struct_adslAturPhysEntry) + +typedef struct adslAturPhysEntry { + int ifIndex; + char serial_no[32]; + union { + char vendor_id[16]; + adslVendorId vendor_info; + } vendor_id; + char version_no[16]; + int SnrMgn; + u32 Attn; + u32 status; + int outputPwr; + u32 attainableRate; + u8 flags; +} adslAturPhysEntry; + + +//ioctl(int fd, GET_ADSL_ATUC_CHAN_INFO, void *struct_adslAtucChanInfo) + +typedef struct adslAtucChanInfo { + int ifIndex; + u32 interleaveDelay; + u32 currTxRate; + u32 prevTxRate; + u8 flags; +} adslAtucChanInfo; + + +//ioctl(int fd, GET_ADSL_ATUR_CHAN_INFO, void *struct_adslAturChanInfo) + +typedef struct adslAturChanInfo { + int ifIndex; + u32 interleaveDelay; + u32 currTxRate; + u32 prevTxRate; + u32 crcBlkLen; + u8 flags; +} adslAturChanInfo; + + +//ioctl(int fd, GET_ADSL_ATUC_PERF_DATA, void *struct_atucPerfDataEntry) + +typedef struct atucPerfDataEntry +{ + int ifIndex; + u32 adslAtucPerfLofs; + u32 adslAtucPerfLoss; + u32 adslAtucPerfESs; + u32 adslAtucPerfInits; + int adslAtucPerfValidIntervals; + int adslAtucPerfInvalidIntervals; + AdslPerfTimeElapsed adslAtucPerfCurr15MinTimeElapsed; + PerfCurrentCount adslAtucPerfCurr15MinLofs; + PerfCurrentCount adslAtucPerfCurr15MinLoss; + PerfCurrentCount adslAtucPerfCurr15MinESs; + PerfCurrentCount adslAtucPerfCurr15MinInits; + AdslPerfTimeElapsed adslAtucPerfCurr1DayTimeElapsed; + AdslPerfCurrDayCount adslAtucPerfCurr1DayLofs; + AdslPerfCurrDayCount adslAtucPerfCurr1DayLoss; + AdslPerfCurrDayCount adslAtucPerfCurr1DayESs; + AdslPerfCurrDayCount adslAtucPerfCurr1DayInits; + int adslAtucPerfPrev1DayMoniSecs; + AdslPerfPrevDayCount adslAtucPerfPrev1DayLofs; + AdslPerfPrevDayCount adslAtucPerfPrev1DayLoss; + AdslPerfPrevDayCount adslAtucPerfPrev1DayESs; + AdslPerfPrevDayCount adslAtucPerfPrev1DayInits; + u32 flags; +} atucPerfDataEntry; + +#ifdef AMAZON_MEI_MIB_RFC3440 +typedef struct atucPerfDataExtEntry + { + int ifIndex; + u32 adslAtucPerfStatFastR; + u32 adslAtucPerfStatFailedFastR; + u32 adslAtucPerfStatSesL; + u32 adslAtucPerfStatUasL; + u32 adslAtucPerfCurr15MinFastR; + u32 adslAtucPerfCurr15MinFailedFastR; + u32 adslAtucPerfCurr15MinSesL; + u32 adslAtucPerfCurr15MinUasL; + u32 adslAtucPerfCurr1DayFastR; + u32 adslAtucPerfCurr1DayFailedFastR; + u32 adslAtucPerfCurr1DaySesL; + u32 adslAtucPerfCurr1DayUasL; + u32 adslAtucPerfPrev1DayFastR; + u32 adslAtucPerfPrev1DayFailedFastR; + u32 adslAtucPerfPrev1DaySesL; + u32 adslAtucPerfPrev1DayUasL; + u32 flags; +} atucPerfDataExtEntry; + +#endif +//ioctl(int fd, GET_ADSL_ATUR_PERF_DATA, void *struct_aturPerfDataEntry) + +typedef struct aturPerfDataEntry +{ + int ifIndex; + u32 adslAturPerfLofs; + u32 adslAturPerfLoss; + u32 adslAturPerfLprs; + u32 adslAturPerfESs; + int adslAturPerfValidIntervals; + int adslAturPerfInvalidIntervals; + AdslPerfTimeElapsed adslAturPerfCurr15MinTimeElapsed; + PerfCurrentCount adslAturPerfCurr15MinLofs; + PerfCurrentCount adslAturPerfCurr15MinLoss; + PerfCurrentCount adslAturPerfCurr15MinLprs; + PerfCurrentCount adslAturPerfCurr15MinESs; + AdslPerfTimeElapsed adslAturPerfCurr1DayTimeElapsed; + AdslPerfCurrDayCount adslAturPerfCurr1DayLofs; + AdslPerfCurrDayCount adslAturPerfCurr1DayLoss; + AdslPerfCurrDayCount adslAturPerfCurr1DayLprs; + AdslPerfCurrDayCount adslAturPerfCurr1DayESs; + int adslAturPerfPrev1DayMoniSecs; + AdslPerfPrevDayCount adslAturPerfPrev1DayLofs; + AdslPerfPrevDayCount adslAturPerfPrev1DayLoss; + AdslPerfPrevDayCount adslAturPerfPrev1DayLprs; + AdslPerfPrevDayCount adslAturPerfPrev1DayESs; + u32 flags; +} aturPerfDataEntry; + +#ifdef AMAZON_MEI_MIB_RFC3440 +typedef struct aturPerfDataExtEntry + { + int ifIndex; + u32 adslAturPerfStatSesL; + u32 adslAturPerfStatUasL; + u32 adslAturPerfCurr15MinSesL; + u32 adslAturPerfCurr15MinUasL; + u32 adslAturPerfCurr1DaySesL; + u32 adslAturPerfCurr1DayUasL; + u32 adslAturPerfPrev1DaySesL; + u32 adslAturPerfPrev1DayUasL; + u32 flags; +} aturPerfDataExtEntry; +#endif +//ioctl(int fd, GET_ADSL_ATUC_INTVL_INFO, void *struct_adslAtucInvtInfo) + +typedef struct adslAtucIntvlInfo { + int ifIndex; + int IntervalNumber; + PerfIntervalCount intervalLOF; + PerfIntervalCount intervalLOS; + PerfIntervalCount intervalES; + PerfIntervalCount intervalInits; + int intervalValidData; + u8 flags; +} adslAtucIntvlInfo; + +#ifdef AMAZON_MEI_MIB_RFC3440 +typedef struct adslAtucInvtlExtInfo + { + int ifIndex; + int IntervalNumber; + u32 adslAtucIntervalFastR; + u32 adslAtucIntervalFailedFastR; + u32 adslAtucIntervalSesL; + u32 adslAtucIntervalUasL; + u32 flags; +} adslAtucInvtlExtInfo; +#endif +//ioctl(int fd, GET_ADSL_ATUR_INTVL_INFO, void *struct_adslAturInvtlInfo) + +typedef struct adslAturIntvlInfo { + int ifIndex; + int IntervalNumber; + PerfIntervalCount intervalLOF; + PerfIntervalCount intervalLOS; + PerfIntervalCount intervalLPR; + PerfIntervalCount intervalES; + int intervalValidData; + u8 flags; +} adslAturIntvlInfo; + +#ifdef AMAZON_MEI_MIB_RFC3440 +typedef struct adslAturInvtlExtInfo + { + int ifIndex; + int IntervalNumber; + u32 adslAturIntervalSesL; + u32 adslAturIntervalUasL; + u32 flags; +} adslAturInvtlExtInfo; +#endif +//ioctl(int fd, GET_ADSL_ATUC_CHAN_PERF_DATA, void *struct_atucChannelPerfDataEntry) + +typedef struct atucChannelPerfDataEntry +{ + int ifIndex; + u32 adslAtucChanReceivedBlks; + u32 adslAtucChanTransmittedBlks; + u32 adslAtucChanCorrectedBlks; + u32 adslAtucChanUncorrectBlks; + int adslAtucChanPerfValidIntervals; + int adslAtucChanPerfInvalidIntervals; + AdslPerfTimeElapsed adslAtucChanPerfCurr15MinTimeElapsed; + PerfCurrentCount adslAtucChanPerfCurr15MinReceivedBlks; + PerfCurrentCount adslAtucChanPerfCurr15MinTransmittedBlks; + PerfCurrentCount adslAtucChanPerfCurr15MinCorrectedBlks; + PerfCurrentCount adslAtucChanPerfCurr15MinUncorrectBlks; + AdslPerfTimeElapsed adslAtucChanPerfCurr1DayTimeElapsed; + AdslPerfCurrDayCount adslAtucChanPerfCurr1DayReceivedBlks; + AdslPerfCurrDayCount adslAtucChanPerfCurr1DayTransmittedBlks; + AdslPerfCurrDayCount adslAtucChanPerfCurr1DayCorrectedBlks; + AdslPerfCurrDayCount adslAtucChanPerfCurr1DayUncorrectBlks; + int adslAtucChanPerfPrev1DayMoniSecs; + AdslPerfPrevDayCount adslAtucChanPerfPrev1DayReceivedBlks; + AdslPerfPrevDayCount adslAtucChanPerfPrev1DayTransmittedBlks; + AdslPerfPrevDayCount adslAtucChanPerfPrev1DayCorrectedBlks; + AdslPerfPrevDayCount adslAtucChanPerfPrev1DayUncorrectBlks; + u32 flags; +}atucChannelPerfDataEntry; + + +//ioctl(int fd, GET_ADSL_ATUR_CHAN_PERF_DATA, void *struct_aturChannelPerfDataEntry) + +typedef struct aturChannelPerfDataEntry +{ + int ifIndex; + u32 adslAturChanReceivedBlks; + u32 adslAturChanTransmittedBlks; + u32 adslAturChanCorrectedBlks; + u32 adslAturChanUncorrectBlks; + int adslAturChanPerfValidIntervals; + int adslAturChanPerfInvalidIntervals; + AdslPerfTimeElapsed adslAturChanPerfCurr15MinTimeElapsed; + PerfCurrentCount adslAturChanPerfCurr15MinReceivedBlks; + PerfCurrentCount adslAturChanPerfCurr15MinTransmittedBlks; + PerfCurrentCount adslAturChanPerfCurr15MinCorrectedBlks; + PerfCurrentCount adslAturChanPerfCurr15MinUncorrectBlks; + AdslPerfTimeElapsed adslAturChanPerfCurr1DayTimeElapsed; + AdslPerfCurrDayCount adslAturChanPerfCurr1DayReceivedBlks; + AdslPerfCurrDayCount adslAturChanPerfCurr1DayTransmittedBlks; + AdslPerfCurrDayCount adslAturChanPerfCurr1DayCorrectedBlks; + AdslPerfCurrDayCount adslAturChanPerfCurr1DayUncorrectBlks; + int adslAturChanPerfPrev1DayMoniSecs; + AdslPerfPrevDayCount adslAturChanPerfPrev1DayReceivedBlks; + AdslPerfPrevDayCount adslAturChanPerfPrev1DayTransmittedBlks; + AdslPerfPrevDayCount adslAturChanPerfPrev1DayCorrectedBlks; + AdslPerfPrevDayCount adslAturChanPerfPrev1DayUncorrectBlks; + u32 flags; +} aturChannelPerfDataEntry; + + +//ioctl(int fd, GET_ADSL_ATUC_CHAN_INTVL_INFO, void *struct_adslAtucChanIntvlInfo) + +typedef struct adslAtucChanIntvlInfo { + int ifIndex; + int IntervalNumber; + PerfIntervalCount chanIntervalRecvdBlks; + PerfIntervalCount chanIntervalXmitBlks; + PerfIntervalCount chanIntervalCorrectedBlks; + PerfIntervalCount chanIntervalUncorrectBlks; + int intervalValidData; + u8 flags; +} adslAtucChanIntvlInfo; + + +//ioctl(int fd, GET_ADSL_ATUR_CHAN_INTVL_INFO, void *struct_adslAturChanIntvlInfo) + +typedef struct adslAturChanIntvlInfo { + int ifIndex; + int IntervalNumber; + PerfIntervalCount chanIntervalRecvdBlks; + PerfIntervalCount chanIntervalXmitBlks; + PerfIntervalCount chanIntervalCorrectedBlks; + PerfIntervalCount chanIntervalUncorrectBlks; + int intervalValidData; + u8 flags; +} adslAturChanIntvlInfo; + + +//ioctl(int fd, GET_ADSL_ALRM_CONF_PROF, void *struct_adslLineAlarmConfProfileEntry) +//ioctl(int fd, SET_ADSL_ALRM_CONF_PROF, void *struct_adslLineAlarmConfProfileEntry) + +typedef struct adslLineAlarmConfProfileEntry + { + unsigned char adslLineAlarmConfProfileName[32]; + int adslAtucThresh15MinLofs; + int adslAtucThresh15MinLoss; + int adslAtucThresh15MinESs; + u32 adslAtucThreshFastRateUp; + u32 adslAtucThreshInterleaveRateUp; + u32 adslAtucThreshFastRateDown; + u32 adslAtucThreshInterleaveRateDown; + int adslAtucInitFailureTrapEnable; + int adslAturThresh15MinLofs; + int adslAturThresh15MinLoss; + int adslAturThresh15MinLprs; + int adslAturThresh15MinESs; + u32 adslAturThreshFastRateUp; + u32 adslAturThreshInterleaveRateUp; + u32 adslAturThreshFastRateDown; + u32 adslAturThreshInterleaveRateDown; + int adslLineAlarmConfProfileRowStatus; + u32 flags; +} adslLineAlarmConfProfileEntry; + +#ifdef AMAZON_MEI_MIB_RFC3440 +typedef struct adslLineAlarmConfProfileExtEntry + { + u8 adslLineAlarmConfProfileExtName[32]; + u32 adslAtucThreshold15MinFailedFastR; + u32 adslAtucThreshold15MinSesL; + u32 adslAtucThreshold15MinUasL; + u32 adslAturThreshold15MinSesL; + u32 adslAturThreshold15MinUasL; + u32 flags; +} adslLineAlarmConfProfileExtEntry; +#endif +//TRAPS + +// 603221:tc.chen start +/* The following Data Sturctures are added to support the WEB related parameters for ADSL Statistics */ +typedef struct adslLineStatus + { + int adslModemStatus; + u32 adslModeSelected; + int adslAtucThresh15MinESs; + int adslTrellisCodeEnable; + int adslLatency; + u8 flags; + } adslLineStatusInfo; + +typedef struct adslLineRate + { + u32 adslDataRateds; + u32 adslDataRateus; + u32 adslATTNDRds; + u32 adslATTNDRus; + u8 flags; + } adslLineRateInfo; + +typedef struct adslLineInfo + { + u32 adslInterleaveDepthds; + u32 adslInterleaveDepthus; + u32 adslLATNds; + u32 adslLATNus; + u32 adslSATNds; + u32 adslSATNus; + int adslSNRMds; + int adslSNRMus; + int adslACATPds; + int adslACATPus; + u32 flags; + } adslLineInfo; + +typedef struct adslNearEndPerfStats + { + u32 adslSuperFrames; + u32 adslneLOS; + u32 adslneLOF; + u32 adslneLPR; + u32 adslneNCD; + u32 adslneLCD; + u32 adslneCRC; + u32 adslneRSCorr; + u32 adslneFECS; + u32 adslneES; + u32 adslneSES; + u32 adslneLOSS; + u32 adslneUAS; + u32 adslneHECErrors; + u32 flags; + } adslNearEndPerfStats; + +typedef struct adslFarEndPerfStats + { + u32 adslfeLOS; + u32 adslfeLOF; + u32 adslfeLPR; + u32 adslfeNCD; + u32 adslfeLCD; + u32 adslfeCRC; + u32 adslfeRSCorr; + u32 adslfeFECS; + u32 adslfeES; + u32 adslfeSES; + u32 adslfeLOSS; + u32 adslfeUAS; + u32 adslfeHECErrors; + u32 flags; + } adslFarEndPerfStats; +// 603221:tc.chen end + +/* The number of tones (and hence indexes) is dependent on the ADSL mode - G.992.1, G.992.2, G.992.3, * G.992.4 and G.992.5 */ +typedef struct adslATURSubcarrierInfo { + int ifindex; + u16 HLINSCds; + u16 HLINpsds[1024];/* Even index = real part; Odd Index + = imaginary part for each tone */ + u16 HLOGMTds; + u16 HLOGpsds[512]; + u16 QLNMTds; + u16 QLNpsds[512]; + u16 SNRMTds; + u16 SNRpsds[512]; + u16 BITpsds[512]; + u16 GAINpsds[512]; + u16 flags; +}adslATURSubcarrierInfo; + +typedef struct adslATUCSubcarrierInfo { + int ifindex; + u16 HLINSCus; + u16 HLINpsus[128];/* Even index = real part; Odd Index + = imaginary part for each tone */ + u16 HLOGMTus; + u16 HLOGpsus[64]; + u16 QLNMTus; + u16 QLNpsus[64]; + u16 SNRMTus; + u16 SNRpsus[64]; + u16 BITpsus[64]; + u16 GAINpsus[64]; + u16 flags; +}adslATUCSubcarrierInfo; + +#ifndef u_int16 +#define u_int16 u16 +#endif + +typedef struct adslInitStats { + u_int16 FullInitializationCount; + u_int16 FailedFullInitializationCount; + u_int16 LINIT_Errors; + u_int16 Init_Timeouts; +}adslInitStats; + +typedef struct adslPowerSpectralDensity { + int ACTPSDds; + int ACTPSDus; +}adslPowerSpectralDensity; + + +//ioctl(int fd, ADSL_ATUR_TRAPS, void *uint16_flags) +typedef union structpts { + adslLineTableEntry * adslLineTableEntry_pt; + adslAtucPhysEntry * adslAtucPhysEntry_pt; + adslAturPhysEntry * adslAturPhysEntry_pt; + adslAtucChanInfo * adslAtucChanInfo_pt; + adslAturChanInfo * adslAturChanInfo_pt; + atucPerfDataEntry * atucPerfDataEntry_pt; + aturPerfDataEntry * aturPerfDataEntry_pt; + adslAtucIntvlInfo * adslAtucIntvlInfo_pt; + adslAturIntvlInfo * adslAturIntvlInfo_pt; + atucChannelPerfDataEntry * atucChannelPerfDataEntry_pt; + aturChannelPerfDataEntry * aturChannelPerfDataEntry_pt; + adslAtucChanIntvlInfo * adslAtucChanIntvlInfo_pt; + adslAturChanIntvlInfo * adslAturChanIntvlInfo_pt; + adslLineAlarmConfProfileEntry * adslLineAlarmConfProfileEntry_pt; + // RFC 3440 + + #ifdef AMAZON_MEI_MIB_RFC3440 + adslLineExtTableEntry * adslLineExtTableEntry_pt; + atucPerfDataExtEntry * atucPerfDataExtEntry_pt; + adslAtucInvtlExtInfo * adslAtucInvtlExtInfo_pt; + aturPerfDataExtEntry * aturPerfDataExtEntry_pt; + adslAturInvtlExtInfo * adslAturInvtlExtInfo_pt; + adslLineAlarmConfProfileExtEntry * adslLineAlarmConfProfileExtEntry_pt; + #endif +// 603221:tc.chen start + adslLineStatusInfo * adslLineStatusInfo_pt; + adslLineRateInfo * adslLineRateInfo_pt; + adslLineInfo * adslLineInfo_pt; + adslNearEndPerfStats * adslNearEndPerfStats_pt; + adslFarEndPerfStats * adslFarEndPerfStats_pt; +// 603221:tc.chen end + adslATUCSubcarrierInfo * adslATUCSubcarrierInfo_pt; + adslATURSubcarrierInfo * adslATURSubcarrierInfo_pt; + adslPowerSpectralDensity * adslPowerSpectralDensity_pt; +}structpts; + +#endif /* ] __AMAZON_MEI_APP_IOCTL_H */ diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_ioctl.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_ioctl.h new file mode 100644 index 0000000000..02a150eac4 --- /dev/null +++ b/target/linux/amazon/files/include/asm-mips/amazon/amazon_mei_ioctl.h @@ -0,0 +1,757 @@ +//509221:tc.chen 2005/09/22 Reset DFE added when MEI_TO_ARC_CS_DONE not cleared by ARC and Added AMAZON_MEI_DEBUG_MODE ioctl +#ifndef _AMAZON_MEI_IOCTL_H +#define _AMAZON_MEI_IOCTL_H + +///////////////////////////////////////////////////////////////////////////////////////////////////// +#define PCM_BUFF_SIZE 1024 //bytes +// interrupt numbers + +#ifndef _AMAZON_ADSL_APP + +typedef struct pcm_data_struct{ + u16 S; + u16 temp; + u16 LSW; + u16 MSW; + u16 len; + u16 rdindex; + u16 wrindex; + u16 flow; + + int finish; + u8 buff[PCM_BUFF_SIZE]; + int point; +}pcm_data_struct; + +typedef struct amazon_clreoc_pkt{ + struct list_head list; + u8 * command; //point to clreoc command data + int len; //command length +}amazon_clreoc_pkt; + +// Number of intervals +#define INTERVAL_NUM 192 //two days +typedef struct amazon_mei_mib{ + struct list_head list; + struct timeval start_time; //start of current interval + + int AtucPerfLof; + int AtucPerfLos; + int AtucPerfEs; + int AtucPerfInit; + + int AturPerfLof; + int AturPerfLos; + int AturPerfLpr; + int AturPerfEs; + + int AturChanPerfRxBlk; + int AturChanPerfTxBlk; + int AturChanPerfCorrBlk; + int AturChanPerfUncorrBlk; + + //RFC-3440 + int AtucPerfStatFastR; + int AtucPerfStatFailedFastR; + int AtucPerfStatSesL; + int AtucPerfStatUasL; + int AturPerfStatSesL; + int AturPerfStatUasL; +}amazon_mei_mib; + +typedef struct adslChanPrevTxRate{ + u32 adslAtucChanPrevTxRate; + u32 adslAturChanPrevTxRate; +}adslChanPrevTxRate; + +typedef struct adslPhysCurrStatus{ + u32 adslAtucCurrStatus; + u32 adslAturCurrStatus; +}adslPhysCurrStatus; + +typedef struct ChanType{ + int interleave; + int fast; +// 603221:tc.chen start + int bearchannel0; + int bearchannel1; +// 603221:tc.chen end +}ChanType; + +typedef struct mib_previous_read{ + u16 ATUC_PERF_ESS; + u16 ATUR_PERF_ESS; + u32 ATUR_CHAN_RECV_BLK; + u16 ATUR_CHAN_CORR_BLK_INTL; + u16 ATUR_CHAN_CORR_BLK_FAST; + u16 ATUR_CHAN_UNCORR_BLK_INTL; + u16 ATUR_CHAN_UNCORR_BLK_FAST; + u16 ATUC_PERF_STAT_FASTR; + u16 ATUC_PERF_STAT_FAILED_FASTR; + u16 ATUC_PERF_STAT_SESL; + u16 ATUC_PERF_STAT_UASL; + u16 ATUR_PERF_STAT_SESL; +}mib_previous_read; + +typedef struct mib_flags_pretime{ + struct timeval ATUC_PERF_LOSS_PTIME; + struct timeval ATUC_PERF_LOFS_PTIME; + struct timeval ATUR_PERF_LOSS_PTIME; + struct timeval ATUR_PERF_LOFS_PTIME; + struct timeval ATUR_PERF_LPR_PTIME; +}mib_flags_pretime; + + // cmv message structures +#define MP_PAYLOAD_SIZE 12 +typedef struct mpmessage{ + u16 iFunction; + u16 iGroup; + u16 iAddress; + u16 iIndex; + u16 iPayload[MP_PAYLOAD_SIZE]; +}MPMessage; +#endif + + +typedef struct meireg{ + u32 iAddress; + u32 iData; +}meireg; + +#define MEIDEBUG_BUFFER_SIZES 50 +typedef struct meidebug{ + u32 iAddress; + u32 iCount; + u32 buffer[MEIDEBUG_BUFFER_SIZES]; +}meidebug; + +//============================================================================== +// Group definitions +//============================================================================== +#define OPTN 5 +#define CNFG 8 +#define CNTL 1 +#define STAT 2 +#define RATE 6 +#define PLAM 7 +#define INFO 3 +#define TEST 4 +//============================================================================== +// Opcode definitions +//============================================================================== +#define H2D_CMV_READ 0x00 +#define H2D_CMV_WRITE 0x04 +#define H2D_CMV_INDICATE_REPLY 0x10 +#define H2D_ERROR_OPCODE_UNKNOWN 0x20 +#define H2D_ERROR_CMV_UNKNOWN 0x30 + +#define D2H_CMV_READ_REPLY 0x01 +#define D2H_CMV_WRITE_REPLY 0x05 +#define D2H_CMV_INDICATE 0x11 +#define D2H_ERROR_OPCODE_UNKNOWN 0x21 +#define D2H_ERROR_CMV_UNKNOWN 0x31 +#define D2H_ERROR_CMV_READ_NOT_AVAILABLE 0x41 +#define D2H_ERROR_CMV_WRITE_ONLY 0x51 +#define D2H_ERROR_CMV_READ_ONLY 0x61 + +#define H2D_DEBUG_READ_DM 0x02 +#define H2D_DEBUG_READ_PM 0x06 +#define H2D_DEBUG_WRITE_DM 0x0a +#define H2D_DEBUG_WRITE_PM 0x0e + +#define D2H_DEBUG_READ_DM_REPLY 0x03 +#define D2H_DEBUG_READ_FM_REPLY 0x07 +#define D2H_DEBUG_WRITE_DM_REPLY 0x0b +#define D2H_DEBUG_WRITE_FM_REPLY 0x0f +#define D2H_ERROR_ADDR_UNKNOWN 0x33 + +#define D2H_AUTONOMOUS_MODEM_READY_MSG 0xf1 +//============================================================================== +// INFO register address field definitions +//============================================================================== + +#define INFO_TxState 0 +#define INFO_RxState 1 +#define INFO_TxNextState 2 +#define INFO_RxNextState 3 +#define INFO_TxStateJumpFrom 4 +#define INFO_RxStateJumpFrom 5 + +#define INFO_ReverbSnrBuf 8 +#define INFO_ReverbEchoSnrBuf 9 +#define INFO_MedleySnrBuf 10 +#define INFO_RxShowtimeSnrBuf 11 +#define INFO_DECdelay 12 +#define INFO_DECExponent 13 +#define INFO_DECTaps 14 +#define INFO_AECdelay 15 +#define INFO_AECExponent 16 +#define INFO_AECTaps 17 +#define INFO_TDQExponent 18 +#define INFO_TDQTaps 19 +#define INFO_FDQExponent 20 +#define INFO_FDQTaps 21 +#define INFO_USBat 22 +#define INFO_DSBat 23 +#define INFO_USFineGains 24 +#define INFO_DSFineGains 25 +#define INFO_BitloadFirstChannel 26 +#define INFO_BitloadLastChannel 27 +#define INFO_PollEOCData 28 // CO specific +#define INFO_CSNRMargin 29 // CO specific +#define INFO_RCMsgs1 30 +#define INFO_RMsgs1 31 +#define INFO_RMsgRA 32 +#define INFO_RCMsgRA 33 +#define INFO_RMsg2 34 +#define INFO_RCMsg2 35 +#define INFO_BitLoadOK 36 +#define INFO_RCRates1 37 +#define INFO_RRates1Tab 38 +#define INFO_RMsgs1Tab 39 +#define INFO_RMsgRATab 40 +#define INFO_RRatesRA 41 +#define INFO_RCRatesRA 42 +#define INFO_RRates2 43 +#define INFO_RCRates2 44 +#define INFO_PackedRMsg2 45 +#define INFO_RxBitSwapFlag 46 +#define INFO_TxBitSwapFlag 47 +#define INFO_ShowtimeSNRUpdateCount 48 +#define INFO_ShowtimeFDQUpdateCount 49 +#define INFO_ShowtimeDECUpdateCount 50 +#define INFO_CopyRxBuffer 51 +#define INFO_RxToneBuf 52 +#define INFO_TxToneBuf 53 +#define INFO_Version 54 +#define INFO_TimeStamp 55 +#define INFO_feVendorID 56 +#define INFO_feSerialNum 57 +#define INFO_feVersionNum 58 +#define INFO_BulkMemory 59 //Points to start of bulk memory +#define INFO_neVendorID 60 +#define INFO_neVersionNum 61 +#define INFO_neSerialNum 62 + +//============================================================================== +// RATE register address field definitions +//============================================================================== + + +#define RATE_UsRate 0 +#define RATE_DsRate 1 + + +//============================================================================== +// PLAM (Physical Layer Management) register address field definitions +// (See G997.1 for reference) +//============================================================================== + + + // /// + // Failure Flags /// + // /// + +#define PLAM_NearEndFailureFlags 0 +#define PLAM_FarEndFailureFlags 1 + + // /// + // Near End Failure Flags Bit Definitions /// + // /// + +// ADSL Failures /// +#define PLAM_LOS_FailureBit 0x0001 +#define PLAM_LOF_FailureBit 0x0002 +#define PLAM_LPR_FailureBit 0x0004 +#define PLAM_RFI_FailureBit 0x0008 + +// ATM Failures /// +#define PLAM_NCD_LP0_FailureBit 0x0010 +#define PLAM_NCD_LP1_FailureBit 0x0020 +#define PLAM_LCD_LP0_FailureBit 0x0040 +#define PLAM_LCD_LP1_FailureBit 0x0080 + +#define PLAM_NCD_BC0_FailureBit 0x0100 +#define PLAM_NCD_BC1_FailureBit 0x0200 +#define PLAM_LCD_BC0_FailureBit 0x0400 +#define PLAM_LCD_BC1_FailureBit 0x0800 + // /// + // Performance Counts /// + // /// + +#define PLAM_NearEndCrcCnt 2 +#define PLAM_CorrectedRSErrors 3 + +#define PLAM_NearEndECSCnt 6 +#define PLAM_NearEndESCnt 7 +#define PLAM_NearEndSESCnt 8 +#define PLAM_NearEndLOSSCnt 9 +#define PLAM_NearEndUASLCnt 10 + +#define PLAM_NearEndHECErrCnt 11 + +#define PLAM_NearEndHECTotCnt 16 +#define PLAM_NearEndCellTotCnt 18 +#define PLAM_NearEndSfCntLSW 20 +#define PLAM_NearEndSfCntMSW 21 + +#define PLAM_FarEndFebeCnt 24 + +#define PLAM_FarEndFecCnt 28 + +#define PLAM_FarEndFECSCnt 32 +#define PLAM_FarEndESCnt 33 +#define PLAM_FarEndSESCnt 34 +#define PLAM_FarEndLOSSCnt 35 +#define PLAM_FarEndUASLCnt 36 + +#define PLAM_FarEndHECErrCnt 37 + +#define PLAM_FarEndHECTotCnt 41 + +#define PLAM_FarEndCellTotCnt 43 + +#define PLAM_LineAttn 45 +#define PLAM_SNRMargin 46 + + +//============================================================================== +// CNTL register address and bit field definitions +//============================================================================== + + +#define CNTL_ModemControl 0 + +#define CNTL_ModemReset 0x0 +#define CNTL_ModemStart 0x2 + + +//============================================================================== +// STAT register address and bit field definitions +//============================================================================== + +#define STAT_MacroState 0 +#define STAT_Mode 1 +#define STAT_DMTFramingMode 2 +#define STAT_SleepState 3 +#define STAT_Misc 4 +#define STAT_FailureState 5 + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // STAT_OLRStatus provides status of OLR + //16-bit STAT_OLRStatus_DS + // [1:0] : OLR status 00=IDLE, 01=OLR_IN_PROGRESS, 10=OLR_Completed, 11=OLR_Aborted + // [3:2]: Reserved + // [5:4]: OLR_Type (1:bitswap; 2: DRR; 3: SRA) + // [7:6]: Reserved + // [10:8]: >0=Request. 0=not. For DS, # of request transmissions/retransmissions (3 bits). + // [11]: 1=Receive Response, 0=not + // [15:12]: Reserved + ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + /// +#define STAT_OLRStatus_DS 6 + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // STAT_OLRStatus provides status of OLR + // 16-bit STAT_OLRStatus_US CMV + // [1:0] : OLR status 00=IDLE, 01=OLR_IN_PROGRESS, 10=OLR_Completed, 11=OLR_Aborted + // [3:2]: Reserved + // [5:4]: OLR_Type (1:bitswap; 2: DRR; 3: SRA) + // [7:6]: Reserved + // [8]: 1=Request Received. 0=not. + // [10:9]: Reserved + // [11]: 1=Response Sent, 0=not + // [15:12]: Reserved + ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/// +#define STAT_OLRStatus_US 7 + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // STAT_PMStatus provides status of PM + // 16-bit STAT_PMStatus CMV + // [1:0] : PM Status 00=IDLE, 01=PM_IN_PROGRESS, 10=PM_Completed, 11=PM_Aborted + // [2] : 0=ATU_R initiated PM; 1 = ATU_C initiated PM + // [3]: Reserved + // [5:4]: PM_Type (1:Simple Request; 2: L2 request; 3: L2 trim) + // [7:6]: Reserved + // [10:8]: >0=Request. 0=not. # of request transmissions/retransmissions (3 bits). + // [11]: 1=Response, 0=not + // [15:12]: Reserved + ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + /// +#define STAT_PMStatus 8 + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // 16-bit STAT_OLRError_DS, STAT_OLRError_US, STAT_PMError + // [3:0]: OLR/PM response reason code + // [7:4]: OLR/PM Internal error code + // [15:8]: OLR/PM Reserved for future + ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + /// +#define STAT_OLRError_DS 9 +#define STAT_OLRError_US 10 +#define STAT_PMError 11 + + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// STAT_MacroState +// MacroState reflects the high level state of the modem + +#define STAT_InitState 0x0000 +#define STAT_ReadyState 0x0001 +#define STAT_FailState 0x0002 +#define STAT_IdleState 0x0003 +#define STAT_QuietState 0x0004 +#define STAT_GhsState 0x0005 +#define STAT_FullInitState 0x0006 +#define STAT_ShowTimeState 0x0007 +#define STAT_FastRetrainState 0x0008 +#define STAT_LoopDiagMode 0x0009 +#define STAT_ShortInit 0x000A // Bis short initialization /// + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// STAT_Mode +// ConfigurationMode indicates the mode of the current ADSL Link. In general, a modem may use +// G.Hs or some other mechanism to negotiate the specific mode of operation. +// The OPTN_modeControl CMV is used to select a set of desired modes. +// The STAT_Mode CMV indicates which mode was actually selected. + +#define STAT_ConfigMode_T1413 0x0001 +#define STAT_ConfigMode_G992_2_AB 0x0002 +#define STAT_ConfigMode_G992_1_A 0x0004 +#define STAT_ConfigMode_G992_1_B 0x0008 +#define STAT_ConfigMode_G992_1_C 0x0010 +#define STAT_ConfigMode_G992_2_C 0x0020 + +#define STAT_ConfigMode_G992_3_A 0x0100 +#define STAT_ConfigMode_G992_3_B 0x0200 +#define STAT_ConfigMode_G992_3_I 0x0400 +#define STAT_ConfigMode_G992_3_J 0x0800 +#define STAT_ConfigMode_G992_3_L 0x1000 + +#define STAT_ConfigMode_G992_4_A 0x2000 +#define STAT_ConfigMode_G992_4_I 0x4000 + +#define STAT_ConfigMode_G992_5 0x8000 + + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// STAT_DMTFramingMode +// FramingMode indicates the DMT framing mde negotiated during initialization. The framing mode +// status is not applicable in BIS mode and its value is undefined +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#define STAT_FramingModeMask 0x0003 + + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// STAT_Misc +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#define STAT_OverlappedSpectrum 0x0008 +#define STAT_TCM 0x0010 +#define STAT_TDQ_at_1104 0x0020 +#define STAT_T1413_Signal_Detected 0x0040 +#define STAT_AnnexL_US_Mask1_PSD 0x1000 //indicate we actually selected G992.3 AnnexL US PSD mask1 +#define STAT_AnnexL_US_Mask2_PSD 0x2000 //indicate we actually selected G992.3 AnnexL US PSD mask2 + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// STAT_FailureState +// when the MacroSTate indicates the fail state, FailureState provides a failure code +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + + +#define E_CODE_NO_ERROR 0 +#define E_CODE_BAT_TX 1 // TX BAT table is incorrect */ +#define E_CODE_BAT_RX 2 // RX BAT table is incorrect */ +#define E_CODE_PROFILE 3 // profile is not selected in fast retrain */ +#define E_CODE_TX_AOC_FIFO_OVERFLOW 4 +#define E_CODE_TRUNCATE_FR 5 //Fast Retrain truncated due to no stored profiles*/ +#define E_CODE_BITLOAD 6 // bit loading fails */ +#define E_CODE_ST_ERROR 7 // showtime CRC error */ +#define E_CODE_RESERVED 8 // using parameters reserved by the ITU-T */ +#define E_CODE_C_TONES 9 // detected C_TONES */ +#define E_CODE_CODESWAP_ERR 10 // codeswap not finished in time */ +#define E_CODE_FIFO_OVERFLOW 11 // we have run out of fifo space */ +#define E_CODE_C_BG_DECODE_ERR 12 // error in decoding C-BG message */ +#define E_CODE_C_RATES2_DECODE_ERR 13 // error in decoding C-MSGS2 and C-RATES2 */ +#define E_CODE_RCMedleyRx_C_SEGUE2_Failure 14 // Timeout after RCMedleyRx waiting for C_SEGUE2 */ +#define E_CODE_RReverbRATx_C_SEGUE2_Failure 15 // Timeout after RReverbRATx waiting for C_SEGUE2 */ +#define E_CODE_RReverb3Tx_C_SEGUE1_Failure 16 // Timeout after RReverb3Tx waiting for C_SEGUE1 */ +#define E_CODE_RCCRC2Rx_C_RATES1_DECOD_ERR 17 // Received CRC not equal to computed CRC */ +#define E_CODE_RCCRC1Rx_C_RATES1_DECOD_ERR 18 // Received CRC not equal to computed CRC */ +#define E_CODE_RReverb5Tx_C_SEGUE2_Failure 19 // Timeout after RReverb5Tx waiting for C_SEGUE2 */ +#define E_CODE_RReverb6Tx_C_SEGUE3_Failure 20 // Timeout after RReverb6Tx waiting for C_SEGUE3 */ +#define E_CODE_RSegue5Tx_C_SEGUE3_Failure 21 // Timeout after RSegue5Tx waiting for C_SEGUE3 */ +#define E_CODE_RCReverb5Rx_C_SEGUE_Failure 22 // Timeout after RCReverb5Rx waiting for C_SEGUE */ +#define E_CODE_RCReverbRARx_C_SEGUE2_Failure 23 // Timeout after RCReverbRARx waiting for C_SEGUE2 */ +#define E_CODE_RCCRC4Rx_CMSGS2_DECOD_ERR 24 // Received CRC not equal to computed CRC */ +#define E_CODE_RCCRC5Rx_C_BG_DECOD_ERR 25 // Received CRC not equal to computed CRC */ +#define E_CODE_RCCRC3Rx_DECOD_ERR 26 // Received CRC not equal to computed CRC */ +#define E_CODE_RCPilot3_DEC_PATH_DEL_TIMEOUT 27 // DEC Path Delay timeout */ +#define E_CODE_RCPilot3_DEC_TRAINING_TIMEOUT 28 // DEC Training timeout */ +#define E_CODE_RCReverb3Rx_C_SEGUE1_Failure 29 // Timeout after RCReverb3Rx waiting for C_SEGUE1 */ +#define E_CODE_RCReverb2Rx_SignalEnd_Failure 30 // Timeout waiting for the end of RCReverb2Rx signal */ +#define E_CODE_RQuiet2_SignalEnd_Failure 31 // Timeout waiting for the end of RQuiet2 signal */ +#define E_CODE_RCReverbFR1Rx_Failure 32 // Timeout waiting for the end of RCReverbFR1Rx signal */ +#define E_CODE_RCPilotFR1Rx_SignalEnd_Failure 33 // Timeout waiting for the end of RCPilotFR1Rx signal */ +#define E_CODE_RCReverbFR2Rx_C_Segue_Failure 34 // Timeout after RCReverbFR2Rx waiting for C_SEGUE */ +#define E_CODE_RCReverbFR5Rx_SignalEnd_TIMEOUT 35 // Timeout waiting for the end of RCReverbFR5Rx signal */ +#define E_CODE_RCReverbFR6Rx_C_SEGUE_Failure 36 // Timeout after RCReverbFR6Rx waiting for C_SEGUE */ +#define E_CODE_RCReverbFR8Rx_C_SEGUE_FR4_Failure 37 // Timeout after RCReverbFR8Rx waiting for C_SEGUE_FR4 */ +#define E_CODE_RCReverbFR8Rx_No_PROFILE 38 // Timeout since no profile was selected */ +#define E_CODE_RCReverbFR8Rx_SignalEnd_TIMEOUT 39 // Timeout waiting for the end of RCReverbFR8Rx signal */ +#define E_CODE_RCCRCFR1_DECOD_ERR 40 // Received CRC not equal to computed CRC */ +#define E_CODE_RCRecovRx_SingnalEnd_TIMEOUT 41 // Timeout waiting for the end of RCRecovRx signal */ +#define E_CODE_RSegueFR5Tx_TX_Not_Ready_TIMEOUT 42 // Timeout after RSegueFR5Tx waiting for C_SEGUE2 */ +#define E_CODE_RRecovTx_SignalEnd_TIMEOUT 43 // Timeout waiting for the end of RRecovTx signal */ +#define E_CODE_RCMedleyFRRx_C_SEGUE2_Failure 44 // Timeout after RCMedleyFRRx waiting for C_SEGUE2 */ +#define E_CODE_CONFIGURATION_PARAMETERS_ERROR 45 // one of the configuration parameters do not meet the standard */ +#define E_CODE_BAD_MEM_ACCESS 46 +#define E_CODE_BAD_INSTRUCTION_ACCESS 47 +#define E_CODE_TX_EOC_FIFO_OVERFLOW 48 +#define E_CODE_RX_EOC_FIFO_OVERFLOW 49 +#define E_CODE_GHS_CD_FLAG_TIME_OUT 50 // Timeout when transmitting Flag in handshake cleardown */ + + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//STAT_OLRStatus: +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#define STAT_OLRPM_IDLE 0x0000 +#define STAT_OLRPM_IN_PROGRESS 0x0001 +#define STAT_OLRPM_COMPLETE 0x0002 +#define STAT_OLRPM_ABORTED 0x0003 +#define STAT_OLRPM_RESPONSE 0x0800 + +#define STAT_OLR_BITSWAP 0x0010 +#define STAT_OLR_DRR 0x0020 +#define STAT_OLR_SRA 0x0030 + +//STAT_PMStatus_US: +#define STAT_PM_CO_REQ 0x0004 +#define STAT_PM_SIMPLE_REQ 0x0010 +#define STAT_PM_L2_REQ 0x0020 +#define STAT_PM_L2_TRIM_REQ 0x0030 + +// STAT_OLRError_DS, STAT_OLRError_US +//4 bit response reason code: +#define RESP_BUSY 0x01 +#define RESP_INVALID_PARAMETERS 0x02 +#define RESP_NOT_ENABLED 0x03 +#define RESP_NOT_SUPPORTED 0x04 + +//4 bit internal error code (common for OLR and PM) +#define REQ_INVALID_BiGi 0x10 +#define REQ_INVALID_Lp 0x20 +#define REQ_INVALID_Bpn 0x30 +#define REQ_INVALID_FRAMING_CONSTRAINT 0x40 +#define REQ_NOT_IN_L0_STATE 0x50 +#define REQ_NOT_IN_L2_STATE 0x60 +#define REQ_INVALID_PCB 0x70 +#define REQ_VIOLATES_MARGIN 0x80 + +//STAT_PMError +//4 bit response reason code: +#define RESP_STATE_NOT_DESIRED 0x03 +#define RESP_INFEASIBLE_PARAMETERS 0x04 + + + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// OPTN register address and bit field definitions +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#define OPTN_ModeControl 0 +#define OPTN_DMTLnkCtl 1 +// Reserved 2 +#define OPTN_GhsControl 3 +// Reserved 4 +#define OPTN_PwrManControl 5 +#define OPTN_AnnexControl 6 +#define OPTN_ModeControl1 7 +// Reserved 8 +#define OPTN_StateMachineCtrl 9 +// Reserved 10 +// Reserved 11 +#define OPTN_BisLinkControl 12 +#define OPTN_ATMAddrConfig 13 +#define OPTN_ATMNumCellConfig 14 + +// Mode control defines the allowable operating modes of an ADSL link. In general, a modem may /// +// use G.Hs or some other mechanism to negotiate the specific mode of operation. /// +// The OPTN_ModeControl CMV is used to select a set of desired modes /// +// The STAT_ModeControl CMV indicates which mode was actually selected /// + +// OPTN_ModeControl +#define OPTN_ConfigMode_T1413 0x0001 +#define OPTN_ConfigMode_G992_2_AB 0x0002 +#define OPTN_ConfigMode_G992_1_A 0x0004 +#define OPTN_ConfigMode_G992_1_B 0x0008 +#define OPTN_ConfigMode_G992_1_C 0x0010 +#define OPTN_ConfigMode_G992_2_C 0x0020 + +#define OPTN_ConfigMode_G992_3_A 0x0100 +#define OPTN_ConfigMode_G992_3_B 0x0200 +#define OPTN_ConfigMode_G992_3_I 0x0400 +#define OPTN_ConfigMode_G992_3_J 0x0800 +#define OPTN_ConfigMode_G992_3_L 0x1000 + +#define OPTN_ConfigMode_G992_4_A 0x2000 +#define OPTN_ConfigMode_G992_4_I 0x4000 + +#define OPTN_ConfigMode_G992_5 0x8000 + +// OPTN_PwrManControl +#define OPTN_PwrManWakeUpGhs 0x1 +#define OPTN_PwrManWakeUpFR 0x2 + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// OPTN_DMT Link Control +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +#define OPTN_DMT_DualLatency_Dis 0x200 +#define OPTN_DMT_S_Dis 0x100 +#define OPTN_DMT_FRAMINGMODE 0x1 +#define OPTN_DMT_FRAMINGMODE_MASK 0x7 + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// OPTN_BIS Link Control +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +#define OPTN_BisLinkContrl_LineProbeDis 0x1 +#define OPTN_BisLinkContrl_DSBlackBitsEn 0x2 +#define OPTN_BisLinkContrl_DiagnosticModeEn 0x4 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// OPTN_GhsControl +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// +// for OPTN_GhsControl, we will assign 16bit word as follows +// bit 0~3: set the control over which start(initial) message CPE will send: +// +// BIT: 2 1 0 +// 0 0 1 CLR +// 0 1 0 MR +// 0 1 1 MS +// 1 0 0 MP +// +// // bit 4~6: set the control over which message will be sent when we get at lease one CL/CLR exchange +// BIT: 5 4 +// 0 1 MS +// 1 0 MR +// 1 1 MP +// +// // bit 15: RT initiated G.hs sample sessions one through eight. Session one is default. +// BIT: 15 +// 1 means session one +// +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#define OPTN_GHS_ST_GHS 0x8000 +#define OPTN_GHS_INIT_MASK 0x000F +#define OPTN_GHS_RESP_MASK 0x00F0 + +#define OPTN_RTInitTxMsg_CLR 0x0001 +#define OPTN_RTInitTxMsg_MR 0x0002 +#define OPTN_RTInitTxMsg_MS 0x0003 +#define OPTN_RTInitTxMsg_MP 0x0004 + +#define OPTN_RTRespTxMsg_MS 0x0010 +#define OPTN_RTRespTxMsg_MR 0x0020 +#define OPTN_RTRespTxMsg_MP 0x0030 + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// OPTN_AnnexControl +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + + +// G.992.3 Annex A/L1/L2 US PSD Mask preferred + +#define OPTN_G992_3_AnnexA_PreferredModeMask 0x3000 +#define OPTN_G992_3_AnnexA_PreferredModeA 0x0000 // default AnnexA PSD mask /// +#define OPTN_G992_3_AnnexA_PreferredModeL1 0x1000 // AnnexL wide spectrum upstream PSD mask /// +#define OPTN_G992_3_AnnexA_PreferredModeL2 0x2000 // AnnexL narrow spectrum upstream PSD mask /// + + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//OPTN_ATMAddrConfig +// Bits 4:0 are Utopia address for BC1 +// Bits 9:5 are Utopia address for BC0 +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#define OPTN_UTPADDR_BC1 0x001F +#define OPTN_UTPADDR_BC0 0x03E0 + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//OPTN_ATMNumCellConfig +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#define OPTN_BC1_NUM_CELL_PAGES 0x000F // Bits 0:3 /// +#define OPTN_BC0_NUM_CELL_PAGES 0x00F0 // Bits 4:7 /// + + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// CNFG register address field /// +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////// +// these cmvs are used by bis handshake /// +/////////////////////////////////////////// + +// Each of the CNFG_TPS entries points to a structure of type (TPS_TC_BearerChannel_t) +#define CNFG_TPS_TC_DS0 0 +#define CNFG_TPS_TC_DS1 1 +#define CNFG_TPS_TC_US0 2 +#define CNFG_TPS_TC_US1 3 + +#define CNFG_HDLC_Overhead_Requirements 4 + +// Each of the CNFG_PMS entries points to a structure of type (PMS_TC_LatencyPath_t) +#define CNFG_PMS_TC_DS0 5 +#define CNFG_PMS_TC_DS1 6 +#define CNFG_PMS_TC_US0 7 +#define CNFG_PMS_TC_US1 8 + +// CNFG_PMD_PARAMETERS points to a structure of type (PMD_params_t) +#define CNFG_PMD_PARAMETERS 9 + +//////////////////////////////////////////////////////////// +// these cmvs are used by bis training and showtime code /// +//////////////////////////////////////////////////////////// + +//////////////// +// Tx Config /// +//////////////// +#define CNFG_tx_Cnfg_Nbc 10 +#define CNFG_tx_Cnfg_Nlp 11 +#define CNFG_tx_Cnfg_Rp 12 +#define CNFG_tx_Cnfg_Mp 13 +#define CNFG_tx_Cnfg_Lp 14 +#define CNFG_tx_Cnfg_Tp 15 +#define CNFG_tx_Cnfg_Dp 16 +#define CNFG_tx_Cnfg_Bpn 17 +#define CNFG_tx_Cnfg_FramingMode 18 +#define CNFG_tx_Cnfg_MSGLp 19 +#define CNFG_tx_Cnfg_MSGc 20 + + +//////////////// +// Rx Config /// +//////////////// +#define CNFG_rx_Cnfg_Nbc 21 +#define CNFG_rx_Cnfg_Nlp 22 +#define CNFG_rx_Cnfg_Rp 23 +#define CNFG_rx_Cnfg_Mp 24 +#define CNFG_rx_Cnfg_Lp 25 +#define CNFG_rx_Cnfg_Tp 26 +#define CNFG_rx_Cnfg_Dp 27 +#define CNFG_rx_Cnfg_Bpn 28 +#define CNFG_rx_Cnfg_FramingMode 29 +#define CNFG_rx_Cnfg_MSGLp 30 +#define CNFG_rx_Cnfg_MSGc 31 + +#define CNFG_tx_Cnfg_BCnToLPp 32 +#define CNFG_rx_Cnfg_BCnToLPp 33 + + + +#endif + diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_sw.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_sw.h new file mode 100644 index 0000000000..3b73b53892 --- /dev/null +++ b/target/linux/amazon/files/include/asm-mips/amazon/amazon_sw.h @@ -0,0 +1,176 @@ +#ifndef AMAZON_SW_H +#define AMAZON_SW_H +#define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE +#define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1 +#define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2 +#define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3 +#define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4 +#define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5 +#define SET_ETH_REG SIOCDEVPRIVATE+6 +#define VLAN_TOOLS SIOCDEVPRIVATE+7 +#define MAC_TABLE_TOOLS SIOCDEVPRIVATE+8 + + +/*===mac table commands==*/ +#define RESET_MAC_TABLE 0 +#define READ_MAC_ENTRY 1 +#define WRITE_MAC_ENTRY 2 +#define ADD_MAC_ENTRY 3 + +/*====vlan commands===*/ + +#define CHANGE_VLAN_CTRL 0 +#define READ_VLAN_ENTRY 1 +#define UPDATE_VLAN_ENTRY 2 +#define CLEAR_VLAN_ENTRY 3 +#define RESET_VLAN_TABLE 4 +#define ADD_VLAN_ENTRY 5 + +/* +** MDIO constants. +*/ + +#define MDIO_BASE_STATUS_REG 0x1 +#define MDIO_BASE_CONTROL_REG 0x0 +#define MDIO_PHY_ID_HIGH_REG 0x2 +#define MDIO_PHY_ID_LOW_REG 0x3 +#define MDIO_BC_NEGOTIATE 0x0200 +#define MDIO_BC_FULL_DUPLEX_MASK 0x0100 +#define MDIO_BC_AUTO_NEG_MASK 0x1000 +#define MDIO_BC_SPEED_SELECT_MASK 0x2000 +#define MDIO_STATUS_100_FD 0x4000 +#define MDIO_STATUS_100_HD 0x2000 +#define MDIO_STATUS_10_FD 0x1000 +#define MDIO_STATUS_10_HD 0x0800 +#define MDIO_STATUS_SPEED_DUPLEX_MASK 0x7800 +#define MDIO_ADVERTISMENT_REG 0x4 +#define MDIO_ADVERT_100_FD 0x100 +#define MDIO_ADVERT_100_HD 0x080 +#define MDIO_ADVERT_10_FD 0x040 +#define MDIO_ADVERT_10_HD 0x020 +#define MDIO_LINK_UP_MASK 0x4 +#define MDIO_START 0x1 +#define MDIO_READ 0x2 +#define MDIO_WRITE 0x1 +#define MDIO_PREAMBLE 0xfffffffful + +#define PHY_RESET 0x8000 +#define AUTO_NEGOTIATION_ENABLE 0X1000 +#define AUTO_NEGOTIATION_COMPLETE 0x20 +#define RESTART_AUTO_NEGOTIATION 0X200 + + +#define PHY0_ADDR 0 +#define PHY1_ADDR 1 +#define P1M 0 + +#define AMAZON_SW_REG32(reg_num) *((volatile u32*)(reg_num)) + +#define OK 0; + +#ifdef CONFIG_CPU_LITTLE_ENDIAN +typedef struct mac_table_entry{ + u64 mac_address:48; + u64 p0:1; + u64 p1:1; + u64 p2:1; + u64 cr:1; + u64 ma_st:3; + u64 res:9; +}_mac_table_entry; + +typedef struct IFX_Switch_VLanTableEntry{ + u32 vlan_id:12; + u32 mp0:1; + u32 mp1:1; + u32 mp2:1; + u32 v:1; + u32 res:16; +}_IFX_Switch_VLanTableEntry; + +typedef struct mac_table_req{ + int cmd; + int index; + u32 data; + u64 entry_value; +}_mac_table_req; + +#else //not CONFIG_CPU_LITTLE_ENDIAN +typedef struct mac_table_entry{ + u64 mac_address:48; + u64 p0:1; + u64 p1:1; + u64 p2:1; + u64 cr:1; + u64 ma_st:3; + u64 res:9; +}_mac_table_entry; + +typedef struct IFX_Switch_VLanTableEntry{ + u32 vlan_id:12; + u32 mp0:1; + u32 mp1:1; + u32 mp2:1; + u32 v:1; + u32 res:16; +}_IFX_Switch_VLanTableEntry; + + +typedef struct mac_table_req{ + int cmd; + int index; + u32 data; + u64 entry_value; +}_mac_table_req; + +#endif //CONFIG_CPU_LITTLE_ENDIAN + + + +typedef struct vlan_req{ + int cmd; + int index; + u32 data; + u32 entry_value; +}_vlan_req; + +typedef struct data_req{ + int index; + u32 value; +}_data_req; + +enum duplex +{ + half, + full, + autoneg +}; + +struct switch_priv { + struct net_device_stats stats; + int rx_packetlen; + u8 *rx_packetdata; + int rx_status; + int tx_packetlen; +#ifdef CONFIG_NET_HW_FLOWCONTROL + int fc_bit; +#endif //CONFIG_NET_HW_FLOWCONTROL + u8 *tx_packetdata; + int tx_status; + struct dma_device_info *dma_device; + struct sk_buff *skb; + spinlock_t lock; + int mdio_phy_addr; + int current_speed; + int current_speed_selection; + int rx_queue_len; + int full_duplex; + enum duplex current_duplex; +}; + +#endif //AMAZON_SW_H + + + + + diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_tpe.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_tpe.h new file mode 100644 index 0000000000..a64e6f9f80 --- /dev/null +++ b/target/linux/amazon/files/include/asm-mips/amazon/amazon_tpe.h @@ -0,0 +1,258 @@ +#ifndef AMAZON_TPE_H +#define AMAZON_TPE_H +#include <linux/atm.h> +#include <linux/atmdev.h> +#include <linux/netdevice.h> +#include <linux/ioctl.h> + +#ifdef CONFIG_IFX_ATM_MIB +/* For ATM-MIB lists */ +#include <linux/list.h> +#endif +#include <asm/amazon/atm_mib.h> + +/* CBM Queue arranagement + * Q0: free cells pool + * Q1~ Q15: upstream queues + * Q16: QAM downstream + * Q17~Q31: downstream queues + */ +#define AMAZON_ATM_MAX_QUEUE_NUM 32 +#define AMAZON_ATM_PORT_NUM 2 +#define AMAZON_ATM_FREE_CELLS 4000 +#define AMAZON_ATM_MAX_VCC_NUM (AMAZON_ATM_MAX_QUEUE_NUM/2 - 1) +#define AMAZON_AAL0_SDU (ATM_AAL0_SDU+4) //one more word for status +#define CBM_RX_OFFSET 16 //offset from the same q for tx +#define AMAZON_ATM_OAM_Q_ID 16 +#define AMAZON_ATM_RM_Q_ID 16 +#define AMAZON_ATM_OTHER_Q_ID 16 +#define CBM_DEFAULT_Q_OFFSET 1 +#define HTUTIMEOUT 0xffff//timeoutofhtutocbm +#define QSB_WFQ_NONUBR_MAX 0x3f00 +#define QSB_WFQ_UBR_BYPASS 0x3fff +#define QSB_TP_TS_MAX 65472 +#define QSB_TAUS_MAX 64512 +#define QSB_GCR_MIN 18 +#define HTU_RAM_ACCESS_MAX 1024//maxium time for HTU RAM access + +#define SWIE_LOCK 1 +#define PROC_ATM 1 +#define PROC_MIB 2 +#define PROC_VCC 3 +#define PROC_AAL5 4 +#define PROC_CBM 5 +#define PROC_HTU 6 +#define PROC_QSB 7 +#define PROC_SWIE 8 + +/***************** internal data structure ********************/ +typedef int (*push_back_t)(struct atm_vcc *vcc,struct sk_buff *skb,int err) ; +/* Device private data */ +typedef struct{ + u8 padding_byte; + u32 tx_max_sdu; + u32 rx_max_sdu; + u32 cnt_cpy; //no. of packets that need a copy due to alignment +}amazon_aal5_dev_t; + +typedef struct{ + u32 max_q_off; //maxium queues used in real scenario + u32 nrt_thr; + u32 clp0_thr; + u32 clp1_thr; + u32 free_cell_cnt; +#ifdef CONFIG_USE_VENUS + u8 * qd_addr_free; //to work around a bug, bit15 of QDOFF address should be 1 +#endif + u8 * qd_addr; + u8 * mem_addr; + u8 allocated; +}amazon_cbm_dev_t; + +typedef struct{ + +}amazon_htu_dev_t; + +typedef struct{ + u32 tau; //cell delay variation due to concurrency(?) + u32 tstepc; //time step, all legal values are 1,2,4 + u32 sbl; //scheduler burse length (for PHY) +}amazon_qsb_dev_t; + +typedef struct{ + u32 qid; //QID of the current extraction queue + struct semaphore in_sem; // Software-Insertion semaphore + volatile long lock; //lock that avoids race contions between SWIN and SWEX + wait_queue_head_t sleep; //wait queue for SWIE and SWEX + u32 sw; //status word +}amazon_swie_dev_t; + +//AAL5 MIB Counter +typedef struct{ + u32 tx,rx; //number AAL5 CPCS PDU from/to higher-layer + u32 tx_err,rx_err; //ifInErrors and ifOutErros + u32 tx_drop,rx_drop; //discarded received packets due to mm shortage + u32 htu_unp; //number of unknown received cells + u32 rx_cnt_h; //number of octets received, high 32 bits + u32 rx_cnt_l; //number of octets received, low 32 bits + u32 tx_cnt_h; //number of octets transmitted, high 32 bits + u32 tx_cnt_l; //number of octets transmitted, low 32 bits + u32 tx_ppd; //number of cells for AAL5 upstream PPD discards + u64 rx_cells; //number of cells for downstream + u64 tx_cells; //number of cells for upstream + u32 rx_err_cells; //number of cells dropped due to uncorrectable HEC errors +}amazon_mib_counter_t; + + + +typedef enum {QS_PKT,QS_LEN,QS_ERR,QS_HW_DROP,QS_SW_DROP,QS_MAX} qs_t; +//queue statics no. of packet received / sent +//queue statics no. of bytes received / sent +//queue statics no. of packets with error +//queue statics no. of packets dropped by hw +//queue statics no. of packets dropped by sw + +typedef struct{ + push_back_t push; //call back function + struct atm_vcc * vcc; //opened vcc + struct timeval access_time; //time when last F4/F5 user cells arrive + int free; //whether this queue is occupied, 0: occupied, 1: free + u32 aal5VccCrcErrors; //MIB counter + u32 aal5VccOverSizedSDUs; //MIB counter + +#if defined(AMAZON_ATM_DEBUG) || defined (CONFIG_IFX_ATM_MIB) + u32 qs[QS_MAX]; +#endif +}amazon_atm_queue_t; + + +typedef struct{ + int enable; //enable / disable + u32 max_conn; //maximum number of connections per port + u32 tx_max_cr; //Remaining cellrate for this device for tx direction + u32 tx_rem_cr; //Remaining cellrate for this device for tx direction + u32 tx_cur_cr; //Current cellrate for this device for tx direction +}amazon_atm_port_t; + +typedef struct{ + amazon_aal5_dev_t aal5; + amazon_cbm_dev_t cbm; + amazon_htu_dev_t htu; + amazon_qsb_dev_t qsb; + amazon_swie_dev_t swie; + amazon_mib_counter_t mib_counter; + amazon_atm_queue_t queues[AMAZON_ATM_MAX_QUEUE_NUM]; + amazon_atm_port_t ports[AMAZON_ATM_PORT_NUM]; + atomic_t dma_tx_free_0;//TX_CH0 has availabe descriptors +} amazon_atm_dev_t; + +struct oam_last_activity{ + u8 vpi; //vpi for this connection + u16 vci; //vci for t his connection + struct timeval stamp; //time when last F4/F5 user cells arrive + struct oam_last_activity * next;//for link list purpose +}; + +typedef union{ +#ifdef CONFIG_CPU_LITTLE_ENDIAN + struct{ + u32 tprs :16; + u32 twfq :14; + u32 vbr :1; + u32 reserved :1; + }bit; + u32 w0; +#else + struct{ + u32 reserved :1; + u32 vbr :1; + u32 twfq :14; + u32 tprs :16; + }bit; + u32 w0; +#endif + +}qsb_qptl_t; + +typedef union{ +#ifdef CONFIG_CPU_LITTLE_ENDIAN + struct{ + u32 ts :16; + u32 taus :16; + }bit; + u32 w0; +#else + struct{ + u32 taus :16; + u32 ts :16; + }bit; + u32 w0; +#endif +}qsb_qvpt_t; + + + +struct amazon_atm_cell_header { +#ifdef CONFIG_CPU_LITTLE_ENDIAN + struct{ + u32 clp :1; // Cell Loss Priority + u32 pti :3; // Payload Type Identifier + u32 vci :16; // Virtual Channel Identifier + u32 vpi :8; // Vitual Path Identifier + u32 gfc :4; // Generic Flow Control + }bit; +#else + struct{ + u32 gfc :4; // Generic Flow Control + u32 vpi :8; // Vitual Path Identifier + u32 vci :16; // Virtual Channel Identifier + u32 pti :3; // Payload Type Identifier + u32 clp :1; // Cell Loss Priority + }bit; +#endif +}; + + +/************************ Function Declarations **************************/ +amazon_atm_dev_t * amazon_atm_create(void); +int amazon_atm_open(struct atm_vcc *vcc,push_back_t); +int amazon_atm_send(struct atm_vcc *vcc,struct sk_buff *skb); +int amazon_atm_send_oam(struct atm_vcc *vcc,void *cell, int flags); +void amazon_atm_close(struct atm_vcc *vcc); +void amazon_atm_cleanup(void); +const struct oam_last_activity* get_oam_time_stamp(void); + +//mib-related +int amazon_atm_cell_mib(atm_cell_ifEntry_t * to,u32 itf); +int amazon_atm_aal5_mib(atm_aal5_ifEntry_t * to); +int amazon_atm_vcc_mib(struct atm_vcc *vcc,atm_aal5_vcc_t * to); +int amazon_atm_vcc_mib_x(int vpi, int vci,atm_aal5_vcc_t* to); + +#define AMAZON_WRITE_REGISTER_L(data,addr) do{ *((volatile u32*)(addr)) = (u32)(data); wmb();} while (0) +#define AMAZON_READ_REGISTER_L(addr) (*((volatile u32*)(addr))) +/******************************* ioctl stuff****************************************/ +#define NUM(dev) (MINOR(dev) & 0xf) +/* + * Ioctl definitions + */ +/* Use 'o' as magic number */ +#define AMAZON_ATM_IOC_MAGIC 'o' +/* MIB_CELL: get atm cell level mib counter + * MIB_AAL5: get aal5 mib counter + * MIB_VCC: get vcc mib counter + */ +typedef struct{ + int vpi; + int vci; + atm_aal5_vcc_t mib_vcc; +}atm_aal5_vcc_x_t; +#define AMAZON_ATM_MIB_CELL _IOWR(AMAZON_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t) +#define AMAZON_ATM_MIB_AAL5 _IOWR(AMAZON_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t) +#define AMAZON_ATM_MIB_VCC _IOWR(AMAZON_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t) +#define AMAZON_ATM_IOC_MAXNR 3 + +//sockopt +#define SO_AMAZON_ATM_MIB_VCC __SO_ENCODE(SOL_ATM,5,atm_aal5_vcc_t) + +#endif // AMAZON_TPE_H + diff --git a/target/linux/amazon/files/include/asm-mips/amazon/amazon_wdt.h b/target/linux/amazon/files/include/asm-mips/amazon/amazon_wdt.h new file mode 100644 index 0000000000..775dabccfb --- /dev/null +++ b/target/linux/amazon/files/include/asm-mips/amazon/amazon_wdt.h @@ -0,0 +1,23 @@ +#ifndef AMAZON_WDT_H +#define AMAZON_WDT_H +#ifdef __KERNEL__ +typedef struct wdt_dev{ + char name[16]; + int major; + int minor; + + int full; + char buff[10]; +}wdt_dev; +#define AMAZON_WDT_REG32(addr) (*((volatile u32*)(addr))) +#endif //__KERNEL__ + +//AMAZON_WDT_IOC_START: start the WDT timer (must provide a initial timeout value) +//AMAZON_WDT_IOC_STOP: stop the WDT +//AMAZON_WDT_IOC_PING: reload the timer to initial value (must happend after a AMAZON_WDT_IOC_START) +#define AMAZON_WDT_IOC_MAGIC 0xc0 +#define AMAZON_WDT_IOC_START _IOW( AMAZON_WDT_IOC_MAGIC,0, int) +#define AMAZON_WDT_IOC_STOP _IO( AMAZON_WDT_IOC_MAGIC,1) +#define AMAZON_WDT_IOC_PING _IO( AMAZON_WDT_IOC_MAGIC,2) + +#endif //AMAZON_WDT_H diff --git a/target/linux/amazon/files/include/asm-mips/amazon/atm_defines.h b/target/linux/amazon/files/include/asm-mips/amazon/atm_defines.h new file mode 100644 index 0000000000..8adda20051 --- /dev/null +++ b/target/linux/amazon/files/include/asm-mips/amazon/atm_defines.h @@ -0,0 +1,540 @@ +#ifndef ATM_DEFINES_H +#define ATM_DEFINES_H + +//Registers Base Address +#define IO_BASE_ADDR 0xA0000000 +#define AAL5_BASE_ADDRESS 0x10104400+IO_BASE_ADDR +#define CBM_BASE_ADDRESS 0x10104000+IO_BASE_ADDR +#define HTU_BASE_ADDRESS 0x10105100+IO_BASE_ADDR +#define QSB_BASE_ADDRESS 0x10105000+IO_BASE_ADDR +#define SWIE_BASE_ADDRESS 0x10105200+IO_BASE_ADDR + +//AAL5 Registers +#define AAL5_SISR0_ADDR AAL5_BASE_ADDRESS+0x20 +#define AAL5_SIMR0_ADDR AAL5_BASE_ADDRESS+0x24 +#define AAL5_SISR1_ADDR AAL5_BASE_ADDRESS+0x28 +#define AAL5_SIMR1_ADDR AAL5_BASE_ADDRESS+0x2C +#define AAL5_SMFL_ADDR AAL5_BASE_ADDRESS+0x30 +#define AAL5_SATMHD_ADDR AAL5_BASE_ADDRESS+0x34 +#define AAL5_SCON_ADDR AAL5_BASE_ADDRESS+0x38 +#define AAL5_SCMD_ADDR AAL5_BASE_ADDRESS+0x3C +#define AAL5_RISR0_ADDR AAL5_BASE_ADDRESS+0x40 +#define AAL5_RIMR0_ADDR AAL5_BASE_ADDRESS+0x44 +#define AAL5_RISR1_ADDR AAL5_BASE_ADDRESS+0x48 +#define AAL5_RIMR1_ADDR AAL5_BASE_ADDRESS+0x4C +#define AAL5_RMFL_ADDR AAL5_BASE_ADDRESS+0x50 +#define AAL5_RINTINF0_ADDR AAL5_BASE_ADDRESS+0x54 +#define AAL5_RINTINF1_ADDR AAL5_BASE_ADDRESS+0x58 +#define AAL5_RES5C_ADDR AAL5_BASE_ADDRESS+0x5C +#define AAL5_RIOL_ADDR AAL5_BASE_ADDRESS+0x60 +#define AAL5_RIOM_ADDR AAL5_BASE_ADDRESS+0x64 +#define AAL5_SOOL_ADDR AAL5_BASE_ADDRESS+0x68 +#define AAL5_SOOM_ADDR AAL5_BASE_ADDRESS+0x6C +#define AAL5_RES70_ADDR AAL5_BASE_ADDRESS+0x70 +#define AAL5_RES74_ADDR AAL5_BASE_ADDRESS+0x74 +#define AAL5_RES78_ADDR AAL5_BASE_ADDRESS+0x78 +#define AAL5_RES7C_ADDR AAL5_BASE_ADDRESS+0x7C +#define AAL5_RES80_ADDR AAL5_BASE_ADDRESS+0x80 +#define AAL5_RES84_ADDR AAL5_BASE_ADDRESS+0x84 +#define AAL5_RES88_ADDR AAL5_BASE_ADDRESS+0x88 +#define AAL5_RES8C_ADDR AAL5_BASE_ADDRESS+0x8C +#define AAL5_RES90_ADDR AAL5_BASE_ADDRESS+0x90 +#define AAL5_RES94_ADDR AAL5_BASE_ADDRESS+0x94 +#define AAL5_RES98_ADDR AAL5_BASE_ADDRESS+0x98 +#define AAL5_RES9C_ADDR AAL5_BASE_ADDRESS+0x9C +#define AAL5_RESA0_ADDR AAL5_BASE_ADDRESS+0xA0 +#define AAL5_RESA4_ADDR AAL5_BASE_ADDRESS+0xA4 +#define AAL5_RESA8_ADDR AAL5_BASE_ADDRESS+0xA8 +#define AAL5_RESAC_ADDR AAL5_BASE_ADDRESS+0xAC +#define AAL5_RESB0_ADDR AAL5_BASE_ADDRESS+0xB0 +#define AAL5_RESB4_ADDR AAL5_BASE_ADDRESS+0xB4 +#define AAL5_RESB8_ADDR AAL5_BASE_ADDRESS+0xB8 +#define AAL5_RESBC_ADDR AAL5_BASE_ADDRESS+0xBC +#define AAL5_RESC0_ADDR AAL5_BASE_ADDRESS+0xC0 +#define AAL5_RESC4_ADDR AAL5_BASE_ADDRESS+0xC4 +#define AAL5_RESC8_ADDR AAL5_BASE_ADDRESS+0xC8 +#define AAL5_RESCC_ADDR AAL5_BASE_ADDRESS+0xCC +#define AAL5_RESD0_ADDR AAL5_BASE_ADDRESS+0xD0 +#define AAL5_RESD4_ADDR AAL5_BASE_ADDRESS+0xD4 +#define AAL5_RESD8_ADDR AAL5_BASE_ADDRESS+0xD8 +#define AAL5_RESDC_ADDR AAL5_BASE_ADDRESS+0xDC +#define AAL5_RESE0_ADDR AAL5_BASE_ADDRESS+0xE0 +#define AAL5_RESE4_ADDR AAL5_BASE_ADDRESS+0xE4 +#define AAL5_RESE8_ADDR AAL5_BASE_ADDRESS+0xE8 +#define AAL5_RESEC_ADDR AAL5_BASE_ADDRESS+0xEC +#define AAL5_SSRC0_ADDR AAL5_BASE_ADDRESS+0xF0 +#define AAL5_SSRC1_ADDR AAL5_BASE_ADDRESS+0xF4 +#define AAL5_RSRC0_ADDR AAL5_BASE_ADDRESS+0xF8 +#define AAL5_RSRC1_ADDR AAL5_BASE_ADDRESS+0xFC + +#define AAL5S_ISR_QID_MASK 0xFF000000 +#define AAL5S_ISR_SAB 0x00000100 +#define AAL5S_ISR_SE 0x00000080 +#define AAL5S_ISR_MFLE 0x00000040 +#define AAL5S_ISR_SBE0 0x00000020 +#define AAL5S_ISR_SEG0 0x00000010 +#define AAL5S_ISR_TAB 0x00000004 + +#define AAL5_SIMR_MASK 0x000001c7 +#define AAL5_SIMR_SAB 0x00000100 +#define AAL5_SIMR_SE 0x00000080 +#define AAL5_SIMR_MFLE 0x00000040 +#define AAL5_SIMR_TAB 0x00000004 +#define AAL5_SIMR_SBE0 0x00000002 +#define AAL5_SIMR_SEG0 0x00000001 + +#define AAL5_SCMD_SEQCOUNT_MASK 0x0000ff00 +#define AAL5_SCMD_MODE_POLL 0x00000008 +#define AAL5_SCMD_MODE_COUNT 0x00000000 +#define AAL5_SCMD_AS 0x00000004 +#define AAL5_SCMD_SS 0x00000002 +#define AAL5_SCMD_AR 0x00000001 + +#define AAL5R_ISR_CID_MASK 0xFF000000//ConnectionID +#define AAL5R_ISR_DBC_MASK 0x00FF0000//DiscardedByteCounter +#define AAL5R_ISR_END 0x00002000//End +#define AAL5R_ISR_ICID 0x00001000//InvalidConnectionID +#define AAL5R_ISR_CLP 0x00000800//CellLossPriority +#define AAL5R_ISR_CGST 0x00000400//Congestion +#define AAL5R_ISR_UUE 0x00000200//CPCSUUError +#define AAL5R_ISR_CPIE 0x00000100//CPIError +#define AAL5R_ISR_FE 0x00000080//FrameEnd +#define AAL5R_ISR_MFLE 0x00000040//MaximumFrameLengthExceeded +#define AAL5R_ISR_DBCE 0x00000020//DiscardedByteCounterExceeded +#define AAL5R_ISR_CRC 0x00000010//CRCError +#define AAL5R_ISR_ILEN 0x00000008//InvalidLength +#define AAL5R_ISR_RAB 0x00000004//ReceiveAbort + +#define AAL5_RIMR1_MASK 0x00003ffc +#define AAL5_RIMR1_END 0x00002000//End +#define AAL5_RIMR1_ICID 0x00001000//InvalidConnectionID +#define AAL5_RIMR1_CLP 0x00000800//CellLossPriority +#define AAL5_RIMR1_CGST 0x00000400//Congestion +#define AAL5_RIMR1_UUE 0x00000200//CPCSUUError +#define AAL5_RIMR1_CPIE 0x00000100//CPIError +#define AAL5_RIMR1_FE 0x00000080//FrameEnd +#define AAL5_RIMR1_MFLE 0x00000040//MaximumFrameLengthExceeded +#define AAL5_RIMR1_DBCE 0x00000020//DiscardedByteCounterExceeded +#define AAL5_RIMR1_CRC 0x00000010//CRCError +#define AAL5_RIMR1_ILEN 0x00000008//InvalidLength +#define AAL5_RIMR1_RAB 0x00000004//ReceiveAbort + +//AAL5 Reassambly Errors +#define AAL5_STW1_MASK 0x33//Error mask +#define AAL5_STW0_MASK 0x5c//Error mask +#define AAL5_STW0_BE 0x3//padding bytes mask +#define AAL5_STW1_CBM 0x20//Transfer from CBM to A5R abnormally ended +#define AAL5_STW1_CH 0x10//Invalid Channel number error +#define AAL5_STW1_CLP 0x8//CLP value of cells in packet is 1 +#define AAL5_STW1_CG 0x4//Cell in packet expired congestion +#define AAL5_STW1_UU 0x2//CPCS-UU value error +#define AAL5_STW1_CPI 0x1//CPI value error +#define AAL5_STW0_FE 0x80//Frame end +#define AAL5_STW0_MFL 0x40//Maximum frame length error +#define AAL5_STW0_CRC 0x10//CRC error +#define AAL5_STW0_IL 0x8//Invalid length +#define AAL5_STW0_RA 0x4//Received abort + + + +//CBM Registers +#define CBM_NRTTHR_ADDR CBM_BASE_ADDRESS+0x10//NonRealTimeThreshold +#define CBM_CLP0THR_ADDR CBM_BASE_ADDRESS+0x14//CLP0Threshold +#define CBM_CLP1THR_ADDR CBM_BASE_ADDRESS+0x18//CLP1Threshold +#define CBM_QDOFF_ADDR CBM_BASE_ADDRESS+0x1C//QueueDescriptorOffset +#define CBM_CFG_ADDR CBM_BASE_ADDRESS+0x20//Configuration +#define CBM_HWEXPAR0_ADDR CBM_BASE_ADDRESS+0x24//HWExtractParameter0 +#define CBM_RES28_ADDR CBM_BASE_ADDRESS+0x28 +#define CBM_WMSTAT0_ADDR CBM_BASE_ADDRESS+0x2C +#define CBM_HWEXCMD_ADDR CBM_BASE_ADDRESS+0x30//HWExtractCommand0 +#define CBM_RES34_ADDR CBM_BASE_ADDRESS+0x34 +#define CBM_HWEXSTAT0_ADDR CBM_BASE_ADDRESS+0x38//HWExtractStatus0 +#define CBM_RES3C_ADDR CBM_BASE_ADDRESS+0x3C +#define CBM_RES40_ADDR CBM_BASE_ADDRESS+0x40 +#define CBM_CNT_ADDR CBM_BASE_ADDRESS+0x44//CellCount +#define CBM_RES48_ADDR CBM_BASE_ADDRESS+0x48 +#define CBM_LFR_ADDR CBM_BASE_ADDRESS+0x4C//PointertolastCellinfreeCellQueue +#define CBM_FFR_ADDR CBM_BASE_ADDRESS+0x50//PointertofirstCellinfreeCellQueue +#define CBM_RES54_ADDR CBM_BASE_ADDRESS+0x54 +#define CBM_RES58_ADDR CBM_BASE_ADDRESS+0x58 +#define CBM_RES5C_ADDR CBM_BASE_ADDRESS+0x5C +#define CBM_RES60_ADDR CBM_BASE_ADDRESS+0x60 +#define CBM_RES64_ADDR CBM_BASE_ADDRESS+0x64 +#define CBM_RES68_ADDR CBM_BASE_ADDRESS+0x68 +#define CBM_RES6C_ADDR CBM_BASE_ADDRESS+0x6C +#define CBM_RES70_ADDR CBM_BASE_ADDRESS+0x70 +#define CBM_RES74_ADDR CBM_BASE_ADDRESS+0x74 +#define CBM_RES78_ADDR CBM_BASE_ADDRESS+0x78 +#define CBM_RES7C_ADDR CBM_BASE_ADDRESS+0x7C +#define CBM_RES80_ADDR CBM_BASE_ADDRESS+0x80 +#define CBM_RES84_ADDR CBM_BASE_ADDRESS+0x84 +#define CBM_RES88_ADDR CBM_BASE_ADDRESS+0x88 +#define CBM_RES8C_ADDR CBM_BASE_ADDRESS+0x8C +#define CBM_RES90_ADDR CBM_BASE_ADDRESS+0x90 +#define CBM_RES94_ADDR CBM_BASE_ADDRESS+0x94 +#define CBM_RES98_ADDR CBM_BASE_ADDRESS+0x98 +#define CBM_RES9C_ADDR CBM_BASE_ADDRESS+0x9C +#define CBM_RESA0_ADDR CBM_BASE_ADDRESS+0xA0 +#define CBM_RESA4_ADDR CBM_BASE_ADDRESS+0xA4 +#define CBM_RESA8_ADDR CBM_BASE_ADDRESS+0xA8 +#define CBM_RESAC_ADDR CBM_BASE_ADDRESS+0xAC +#define CBM_RESB0_ADDR CBM_BASE_ADDRESS+0xB0 +#define CBM_RESB4_ADDR CBM_BASE_ADDRESS+0xB4 +#define CBM_RESB8_ADDR CBM_BASE_ADDRESS+0xB8 +#define CBM_RESBC_ADDR CBM_BASE_ADDRESS+0xBC +#define CBM_INTINF0_ADDR CBM_BASE_ADDRESS+0xC0//InterruptInfo0 +#define CBM_INTCMD_ADDR CBM_BASE_ADDRESS+0xC4//InterruptCommand0 +#define CBM_IMR0_ADDR CBM_BASE_ADDRESS+0xC8//InterruptMask +#define CBM_SRC0_ADDR CBM_BASE_ADDRESS+0xCC//ServiceRequestControl +#define CBM_RESD0_ADDR CBM_BASE_ADDRESS+0xD0 +#define CBM_RESD4_ADDR CBM_BASE_ADDRESS+0xD4 +#define CBM_RESD8_ADDR CBM_BASE_ADDRESS+0xD8 +#define CBM_RESDC_ADDR CBM_BASE_ADDRESS+0xDC +#define CBM_RESE0_ADDR CBM_BASE_ADDRESS+0xE0 +#define CBM_AAL5IDIS_ADDR CBM_BASE_ADDRESS+0xE4//MIB-No.EPDdiscardedpacketsupstream +#define CBM_AAL5ODIS_ADDR CBM_BASE_ADDRESS+0xE8//MIB-No.PPDdiscardedpacketsupstream +#define CBM_RESEC_ADDR CBM_BASE_ADDRESS+0xEC +#define CBM_RESF0_ADDR CBM_BASE_ADDRESS+0xF0 +#define CBM_RESF4_ADDR CBM_BASE_ADDRESS+0xF4 +#define CBM_RESF8_ADDR CBM_BASE_ADDRESS+0xF8 +#define CBM_RESFC_ADDR CBM_BASE_ADDRESS+0xFC + +//CBMCFG +#define CBM_CFG_INTLCK0EN 0x00000008 +#define CBM_CFG_INT0HLT 0x00000004 +#define CBM_CFG_START 0x00000001 + +#define CBM_HWEXPAR_PN_A5 0x00002000 +#define CBM_HWEXPAR_PN_CM 0x00000000 +#define CBM_HWEXPAR_SUBADD_PORTMASK 0x00000070 +#define CBM_HWEXPAR_SUBADD_ADU 0x00000000 +#define CBM_HWEXPAR_SUBADD_AAL2 0x00000080 +#define CBM_HWEXPAR_SUBADD_SWIE 0x00000100 + +#define CBM_HWEXCMD_SFE2 0x00000100 +#define CBM_HWEXCMD_FE2 0x00000080 +#define CBM_HWEXCMD_SCE2 0x00000040 +#define CBM_HWEXCMD_SFE1 0x00000020 +#define CBM_HWEXCMD_FE1 0x00000010 +#define CBM_HWEXCMD_SCE1 0x00000008 +#define CBM_HWEXCMD_SFE0 0x00000004 +#define CBM_HWEXCMD_FE0 0x00000002 +#define CBM_HWEXCMD_SCE0 0x00000001 + +#define CBM_INTINF0_QID_MASK 0xFF000000 +#define CBM_INTINF0_ORIGIN_MASK 0x00F00000 +#define CBM_INTINF0_EF 0x00004000 +#define CBM_INTINF0_ACA 0x00002000 +#define CBM_INTINF0_ERR 0x00001000 +#define CBM_INTINF0_DISC 0x00000800 +#define CBM_INTINF0_QSBV 0x00000400 +#define CBM_INTINF0_Q0E 0x00000200 +#define CBM_INTINF0_Q0I 0x00000100 +#define CBM_INTINF0_RDE 0x00000080 +#define CBM_INTINF0_OPF 0x00000040 +#define CBM_INTINF0_NFCA 0x00000020 +#define CBM_INTINF0_CLP1TR 0x00000010 +#define CBM_INTINF0_CLP0TR 0x00000008 +#define CBM_INTINF0_NRTTR 0x00000004 +#define CBM_INTINF0_QFD 0x00000002 +#define CBM_INTINF0_QTR 0x00000001 +#define CBM_INTINF0_QID_SHIFT 24 +//CBM QD Word 3 +#define CBM_QD_W3_QOS_0 0x00000000 +#define CBM_QD_W3_QOS_1 0x40000000 +#define CBM_QD_W3_QOS_2 0x80000000 +#define CBM_QD_W3_QOS_3 0xc0000000 + +#define CBM_QD_W3_DIR_UP 0x20000000 +#define CBM_QD_W3_DIR_DOWN 0x00000000 + +#define CBM_QD_W3_CLPt 0x10000000 +#define CBM_QD_W3_RT 0x08000000 +#define CBM_QD_W3_AAL5 0x04000000 + +#define CBM_QD_W3_INT_NOINT 0x00000000 +#define CBM_QD_W3_INT_ACA 0x01000000 +#define CBM_QD_W3_INT_EOF 0x02000000 +#define CBM_QD_W3_INT_BOTH 0x03000000 + +#define CBM_QD_W3_THRESHOLD_MASK 0x00ff0000 +#define CBM_QD_W3_WM_EN 0x00000010 +#define CBM_QD_W3_HCR 0x00000008 +#define CBM_QD_W3_SBID_MASK 0x00000001 + +#define CBM_QD_W3_THRESHOLD_SHIFT 16 + +//WATER MARK STATUS +#define CBM_WM_NRT_MASK 0x00040000 +#define CBM_WM_CLP0_MASK 0x00020000 +#define CBM_WM_CLP1_MASK 0x00010000 + +//CBMNRTTHR, CBMCLP0THR, CBMCLP0THR +#define CBM_NRT_WM_NONE 0x00000000//no water mark +#define CBM_WM_3_1 0x00010000//3/4 to set, 1/4 to release +#define CBM_WM_3_2 0x00020000//3/4 to set, 2/4 to release +#define CBM_WM_2_1 0x00030000//2/4 to set, 1/4 to release +#define CBM_THR_MASK 0x0000FFFF + +#define CBM_IMR_MASK 0x0000fbff +#define CBM_IMR_reserved 0xFFFF0400 +#define CBM_IMR_RFULL 0x00008000//EndofFrame +#define CBM_IMR_EF 0x00004000//EndofFrame +#define CBM_IMR_ACA 0x00002000//AnyCellArrived +#define CBM_IMR_ERR 0x00001000//FPI Error +#define CBM_IMR_DISC 0x00000800//Discard +#define CBM_IMR_reserved1 0x00000400//reserved +#define CBM_IMR_Q0E 0x00000200//Queue0Extract +#define CBM_IMR_Q0I 0x00000100//Queue0Insert +#define CBM_IMR_RDE 0x00000080//ReadEmptyQueue +#define CBM_IMR_OPF 0x00000040//OncePerFrame +#define CBM_IMR_NFCA 0x00000020//NoFreeCellAvailable +#define CBM_IMR_CLP1TR 0x00000010//CLP1ThresholdReached +#define CBM_IMR_CLP0TR 0x00000008//CLP0ThresholdReached +#define CBM_IMR_NRTTR 0x00000004//NonRealTimeThresholdReached +#define CBM_IMR_QFD 0x00000002//QueueFrameDiscard +#define CBM_IMR_QTR 0x00000001//QueueThresholdReached + +#define CBM_EXSTAT_FB 0x00000010 +#define CBM_EXSTAT_SCB 0x00000008 +#define CBM_EXSTAT_Q0 0x00000004 +#define CBM_EXSTAT_RDE 0x00000002 +#define CBM_EXSTAT_QV 0x00000001 + +//HTU Registers +#define HTU_RX0_ADDR HTU_BASE_ADDRESS+0x10 +#define HTU_RX1_ADDR HTU_BASE_ADDRESS+0x14 +#define HTU_RES18_ADDR HTU_BASE_ADDRESS+0x18 +#define HTU_RES1C_ADDR HTU_BASE_ADDRESS+0x1C +#define HTU_RES20_ADDR HTU_BASE_ADDRESS+0x20 +#define HTU_RES24_ADDR HTU_BASE_ADDRESS+0x24 +#define HTU_RES28_ADDR HTU_BASE_ADDRESS+0x28 +#define HTU_RES2C_ADDR HTU_BASE_ADDRESS+0x2C +#define HTU_PCF0PAT_ADDR HTU_BASE_ADDRESS+0x30 +#define HTU_PCF1PAT_ADDR HTU_BASE_ADDRESS+0x34 +#define HTU_RES38_ADDR HTU_BASE_ADDRESS+0x38 +#define HTU_RES3C_ADDR HTU_BASE_ADDRESS+0x3C +#define HTU_RES40_ADDR HTU_BASE_ADDRESS+0x40 +#define HTU_RES44_ADDR HTU_BASE_ADDRESS+0x44 +#define HTU_RES48_ADDR HTU_BASE_ADDRESS+0x48 +#define HTU_RES4C_ADDR HTU_BASE_ADDRESS+0x4C +#define HTU_PCF0MASK_ADDR HTU_BASE_ADDRESS+0x50 +#define HTU_PCF1MASK_ADDR HTU_BASE_ADDRESS+0x54 +#define HTU_RES58_ADDR HTU_BASE_ADDRESS+0x58 +#define HTU_RES5C_ADDR HTU_BASE_ADDRESS+0x5C +#define HTU_RES60_ADDR HTU_BASE_ADDRESS+0x60 +#define HTU_RES64_ADDR HTU_BASE_ADDRESS+0x64 +#define HTU_RES68_ADDR HTU_BASE_ADDRESS+0x68 +#define HTU_RES6C_ADDR HTU_BASE_ADDRESS+0x6C +#define HTU_TIMEOUT_ADDR HTU_BASE_ADDRESS+0x70 +#define HTU_DESTOAM_ADDR HTU_BASE_ADDRESS+0x74 +#define HTU_DESTRM_ADDR HTU_BASE_ADDRESS+0x78 +#define HTU_DESTOTHER_ADDR HTU_BASE_ADDRESS+0x7C +#define HTU_CFG_ADDR HTU_BASE_ADDRESS+0x80 +#define HTU_RES84_ADDR HTU_BASE_ADDRESS+0x84 +#define HTU_RES88_ADDR HTU_BASE_ADDRESS+0x88 +#define HTU_RES8C_ADDR HTU_BASE_ADDRESS+0x8C +#define HTU_INFNOENTRY_ADDR HTU_BASE_ADDRESS+0x90 +#define HTU_INFTIMEOUT_ADDR HTU_BASE_ADDRESS+0x94 +#define HTU_RES98_STAT HTU_BASE_ADDRESS+0x98 +#define HTU_RES9C_ADDR HTU_BASE_ADDRESS+0x9C +#define HTU_MIBCIUP HTU_BASE_ADDRESS+0xA0//MIB Counter In Unknown Protoc Register +#define HTU_CNTTIMEOUT_ADDR HTU_BASE_ADDRESS+0xA4 +#define HTU_RESA8_ADDR HTU_BASE_ADDRESS+0xA8 +#define HTU_RESAC_ADDR HTU_BASE_ADDRESS+0xAC +#define HTU_RAMADDR_ADDR HTU_BASE_ADDRESS+0xB0 +#define HTU_RAMCMD_ADDR HTU_BASE_ADDRESS+0xB4 +#define HTU_RAMSTAT_ADDR HTU_BASE_ADDRESS+0xB8 +#define HTU_RESBC_ADDR HTU_BASE_ADDRESS+0xBC +#define HTU_RAMDAT1_ADDR HTU_BASE_ADDRESS+0xC0 +#define HTU_RAMDAT2_ADDR HTU_BASE_ADDRESS+0xC4 +#define HTU_RESCC_ADDR HTU_BASE_ADDRESS+0xCC +#define HTU_RESD0_ADDR HTU_BASE_ADDRESS+0xD0 +#define HTU_RESD4_ADDR HTU_BASE_ADDRESS+0xD4 +#define HTU_RESD8_ADDR HTU_BASE_ADDRESS+0xD8 +#define HTU_RESDC_ADDR HTU_BASE_ADDRESS+0xDC +#define HTU_RESE0_ADDR HTU_BASE_ADDRESS+0xE0 +#define HTU_RESE4_ADDR HTU_BASE_ADDRESS+0xE4 +#define HTU_IMR0_ADDR HTU_BASE_ADDRESS+0xE8 +#define HTU_RESEC_ADDR HTU_BASE_ADDRESS+0xEC +#define HTU_ISR0_ADDR HTU_BASE_ADDRESS+0xF0 +#define HTU_RESF4_ADDR HTU_BASE_ADDRESS+0xF4 +#define HTU_SRC0_ADDR HTU_BASE_ADDRESS+0xF8 +#define HTU_RESFC_ADDR HTU_BASE_ADDRESS+0xFC + +//HTU_CFG +#define HTU_CFG_START 0x00000001 + +#define HTU_RAMCMD_RMW 0x00000004 +#define HTU_RAMCMD_RD 0x00000002 +#define HTU_RAMCMD_WR 0x00000001 + +#define HTU_RAMDAT1_VCON 0x00000080//validconnection +#define HTU_RAMDAT1_VCT 0x00000040//vcivalueistransparent +#define HTU_RAMDAT1_QIDS 0x00000020//qid selects a cell in cbm +#define HTU_RAMDAT1_VCI3 0x00000010//vci3->oamqueue +#define HTU_RAMDAT1_VCI4 0x00000008//vci4->oamqueue +#define HTU_RAMDAT1_VCI6 0x00000004//vci6->rmqueue +#define HTU_RAMDAT1_PTI4 0x00000002//pti4->oamqueue +#define HTU_RAMDAT1_PTI5 0x00000001//pti5->oamqueue + +#define HTU_RAMDAT2_PTI6 0x00000800 +#define HTU_RAMDAT2_PTI7 0x00000400 +#define HTU_RAMDAT2_F4U 0x00000200 +#define HTU_RAMDAT2_F5U 0x00000100 +#define HTU_RAMDAT2_QID_MASK 0x000000ff + +#define HTU_ISR_NE 0x00000001 +#define HTU_ISR_TORD 0x00000002 +#define HTU_ISR_IT 0x00000008 +#define HTU_ISR_OTOC 0x00000010 +#define HTU_ISR_ONEC 0x00000020 +#define HTU_ISR_PNE 0x00000040 +#define HTU_ISR_PT 0x00000080 +#define HTU_ISR_MASK 0x000000ff + + +//QSB Registers +#define QSB_BIP0_ADDR QSB_BASE_ADDRESS+0x00 +#define QSB_BIP1_ADDR QSB_BASE_ADDRESS+0x04 +#define QSB_BIP2_ADDR QSB_BASE_ADDRESS+0x08 +#define QSB_BIP3_ADDR QSB_BASE_ADDRESS+0x0C +#define QSB_RSVP_ADDR QSB_BASE_ADDRESS+0x10 +#define QSB_TNOW_ADDR QSB_BASE_ADDRESS+0x14 +#define QSB_TNOWCYC_ADDR QSB_BASE_ADDRESS+0x18 +#define QSB_TAU_ADDR QSB_BASE_ADDRESS+0x1C +#define QSB_L1BRS_ADDR QSB_BASE_ADDRESS+0x20 +#define QSB_SBL_ADDR QSB_BASE_ADDRESS+0x24 +#define QSB_CONFIG_ADDR QSB_BASE_ADDRESS+0x28 +#define QSB_RTM_ADDR QSB_BASE_ADDRESS+0x2C +#define QSB_RTD_ADDR QSB_BASE_ADDRESS+0x30 +#define QSB_RAMAC_ADDR QSB_BASE_ADDRESS+0x34 +#define QSB_ISR_ADDR QSB_BASE_ADDRESS+0x38 +#define QSB_IMR_ADDR QSB_BASE_ADDRESS+0x3C +#define QSB_SRC_ADDR QSB_BASE_ADDRESS+0x40 + +#define QSB_TABLESEL_QVPT 8 +#define QSB_TABLESEL_QPT 1 +#define QSB_TABLESEL_SCT 2 +#define QSB_TABLESEL_SPT 3 +#define QSB_TABLESEL_CALENDARWFQ 4/*notusedbyFW*/ +#define QSB_TABLESEL_L2WFQ 5/*notusedbyFW*/ +#define QSB_TABLESEL_CALENDARRS 6/*notusedbyFW*/ +#define QSB_TABLESEL_L2BITMAPRS 7/*notusedbyFW*/ +#define QSB_TABLESEL_SHIFT 24 +#define QSB_TWFQ_MASK 0x3FFF0000 +#define QSB_TPRS_MASK 0x0000FFFF +#define QSB_SBID_MASK 0xF +#define QSB_TWFQ_SHIFT 16 +#define QSB_SCDRATE_MASK 0x00007FFF +#define QSB_SBVALID_MASK 0x80000000 + +#define QSB_ISR_WFQLE 0x00000001 +#define QSB_ISR_WFQBE 0x00000002 +#define QSB_ISR_RSLE 0x00000004 +#define QSB_ISR_RSBE 0x00000008 +#define QSB_ISR_MUXOV 0x00000010 +#define QSB_ISR_CDVOV 0x00000020 +#define QSB_ISR_PARAMI 0x00000040 +#define QSB_ISR_SLOSS 0x00000080 +#define QSB_ISR_IIPS 0x00000100 + +#define QSB_IMR_WFQLE 0x00000001 +#define QSB_IMR_WFQBE 0x00000002 +#define QSB_IMR_RSLE 0x00000004 +#define QSB_IMR_RSBE 0x00000008 +#define QSB_IMR_MUXOV 0x00000010 +#define QSB_IMR_CDVOV 0x00000020 +#define QSB_IMR_PARAMI 0x00000040 +#define QSB_IMR_SLOSS 0x00000080 +#define QSB_IMR_IIPS 0x00000100 + +#define QSB_READ 0x0 +#define QSB_WRITE 0x80000000 +#define QSB_READ_ALL 0xFFFFFFFF + +#if 1 //some bug with QSB access mask +#define QSB_QPT_SET_MASK 0x0 +#define QSB_QVPT_SET_MASK 0x0 +#define QSB_SET_SCT_MASK 0x0 +#define QSB_SET_SPT_MASK 0x0 +#define QSB_SET_SPT_SBVALID_MASK 0x7FFFFFFF +#else //some bug with QSB access mask +#define QSB_QPT_SET_MASK 0x80000000 +#define QSB_QVPT_SET_MASK 0x0 +#define QSB_SET_SCT_MASK 0xFFFFFFE0 +#define QSB_SET_SPT_MASK 0x7FF8C000 +#define QSB_SET_SPT_SBVALID_MASK 0x7FFFFFFF +#endif //some bug with QSB access mask + +#define QSB_SPT_SBVALID 0x80000000 + +#define QSB_RAMAC_REG_LOW 0x0 +#define QSB_RAMAC_REG_HIGH 0x00010000 + +#define SRC_SRE_ENABLE 0x1000 +#define SRC_CLRR 0x4000 //request clear bit + + + +//SWIE Registers +#define SWIE_IQID_ADDR SWIE_BASE_ADDRESS+0x0c//SWIEInsertQueueDescriptor +#define SWIE_ICMD_ADDR SWIE_BASE_ADDRESS+0x10//SWIEInsertCommand +#define SWIE_ISTAT_ADDR SWIE_BASE_ADDRESS+0x14//SWIEInsertStatus +#define SWIE_ESTAT_ADDR SWIE_BASE_ADDRESS+0x18//SWIEExtractStatus +#define SWIE_ISRC_ADDR SWIE_BASE_ADDRESS+0x74//SWIEInsertServiceRequestControl +#define SWIE_ESRC_ADDR SWIE_BASE_ADDRESS+0x78//SWIEExtractServiceRequestControl +#define SWIE_ICELL_ADDR SWIE_BASE_ADDRESS+0x80//SWIEInsertCell(0x80-0xb4) +#define SWIE_ECELL_ADDR SWIE_BASE_ADDRESS+0xc0//SWIEExtractCell(0xc0-0xf4) + +#define SWIE_ISTAT_DONE 0x1 +#define SWIE_ESTAT_DONE 0x1 +#define SWIE_ICMD_START 0x00000001//Startcommandforinsertion +#define SWIE_CBM_SCE0 CBM_HWEXCMD_SCE0//CBMcommandforSingle-Cell-Extract +#define SWIE_CBM_PID_SUBADDR 0x00001000//CBMPortIDandSubAddressforUTOPIA + +//Extracted cell format +//52bytes AAL0 PDU + "Input cell additional data"(14bits) +#define SWIE_ADDITION_DATA_MASK 0x7fff +#define SWIE_EPORT_MASK 0x7000//Source ID (000 AUB0, 001 AUB1) +#define SWIE_EF4USER_MASK 0x800 +#define SWIE_EF5USER_MASK 0x400 +#define SWIE_EOAM_MASK 0x200 +#define SWIE_EAUU_MASK 0x100 +#define SWIE_EVCI3_MASK 0x80 +#define SWIE_EVCI4_MASK 0x40 +#define SWIE_EVCI6_MASK 0x20 +#define SWIE_EPTI4_MASK 0x10 +#define SWIE_EPTI5_MASK 0x8 +#define SWIE_EPTI6_MASK 0x4 +#define SWIE_EPTI7_MASK 0x2 +#define SWIE_ECRC10ERROR_MASK 0x1 + +#define CBM_CELL_SIZE 0x40 +#define CBM_QD_SIZE 0x10 +#define AAL5R_TRAILER_LEN 12 +#define AAL5S_INBOUND_HEADER 8 + +//constants +//TODO: to be finalized by system guys +//DMA QOS defined by ATM QoS Service type +#define DMA_RX_CH0 0 +#define DMA_RX_CH1 1 +#define DMA_TX_CH0 0 +#define DMA_TX_CH1 1 +#define CBR_DMA_QOS CBM_QD_W3_QOS_0 +#define VBR_RT_DMA_QOS CBM_QD_W3_QOS_0 +#define VBR_NRT_DMA_QOS CBM_QD_W3_QOS_0 +#define UBR_PLUS_DMA_QOS CBM_QD_W3_QOS_0 +#define UBR_DMA_QOS CBM_QD_W3_QOS_0 + +#define SRC_TOS_MIPS 0 +#define AAL5R_SRPN 0x00000006//a5rneedshigherprioritythanDR +#define AAL5S_SRPN 0x00000005 +#define CBM_MIPS_SRPN 0x00000004 +#define QSB_SRPN 0x00000023 +#define HTU_SRPN1 0x00000022 +#define HTU_SRPN0 0x00000021 + +#endif //ATM_DEFINES_H + diff --git a/target/linux/amazon/files/include/asm-mips/amazon/atm_mib.h b/target/linux/amazon/files/include/asm-mips/amazon/atm_mib.h new file mode 100644 index 0000000000..f863342580 --- /dev/null +++ b/target/linux/amazon/files/include/asm-mips/amazon/atm_mib.h @@ -0,0 +1,142 @@ +#ifndef AMAZON_ATM_MIB_H +#define AMAZON_ATM_MIB_H + +#ifdef CONFIG_IFX_ATM_MIB +#include <asm/types.h> +#ifdef __KERNEL__ +#include <linux/list.h> +#endif +#endif /* CONFIG_IFX_ATM_MIB */ + +#ifndef __KERNEL__ +#include <atmMIB/local_list.h> +typedef unsigned int __u32; +#endif + +typedef struct{ + __u32 ifHCInOctets_h; + __u32 ifHCInOctets_l; + __u32 ifHCOutOctets_h; + __u32 ifHCOutOctets_l; + __u32 ifInErrors; + __u32 ifInUnknownProtos; + __u32 ifOutErrors; +}atm_cell_ifEntry_t; + +typedef struct{ + __u32 ifHCInOctets_h; + __u32 ifHCInOctets_l; + __u32 ifHCOutOctets_h; + __u32 ifHCOutOctets_l; + __u32 ifInUcastPkts; + __u32 ifOutUcastPkts; + __u32 ifInErrors; + __u32 ifInDiscards; + __u32 ifOutErros; + __u32 ifOutDiscards; +}atm_aal5_ifEntry_t; + +typedef struct{ + __u32 aal5VccCrcErrors; + __u32 aal5VccSarTimeOuts;//no timer support yet + __u32 aal5VccOverSizedSDUs; +}atm_aal5_vcc_t; + +#if defined(CONFIG_IFX_ATM_MIB) || defined(IFX_CONFIG_SNMP_ATM_MIB) +/* ATM-MIB data structures */ +typedef struct atmIfConfEntry { + int ifIndex; + int atmInterfaceMaxVpcs; + int atmInterfaceMaxVccs; + int atmInterfaceConfVpcs; + int atmInterfaceConfVccs; + int atmInterfaceMaxActiveVpiBits; + int atmInterfaceMaxActiveVciBits; + int atmInterfaceIlmiVpi; + int atmInterfaceIlmiVci; + int atmInterfaceAddressType; + char atmInterfaceAdminAddress[40]; + unsigned long atmInterfaceMyNeighborIpAddress; + char atmInterfaceMyNeighborIfName[20]; + int atmInterfaceCurrentMaxVpiBits; + int atmInterfaceCurrentMaxVciBits; + char atmInterfaceSubscrAddress[40]; + int flags; +}atmIfConfEntry; + +typedef struct atmTrafficDescParamEntry { + /* Following three parameters are used to update VCC QoS values */ + int ifIndex; + short atmVclvpi; + int atmVclvci; + + unsigned int atmTrafficParamIndex; + unsigned char traffic_class; + int max_pcr; + /* Subramani: Added min_pcr */ + int min_pcr; + int cdv; + int scr; + int mbs; + int atmTrafficRowStatus; + int atmTrafficFrameDiscard; + struct list_head vpivci_head; + struct list_head list; +}atmTrafficDescParamEntry; + + +typedef struct atmVclEntry { + int ifIndex; + short atmVclvpi; + int atmVclvci; + char vpivci[20]; + int atmVclAdminStatus; + int atmVclOperStatus; + unsigned long atmVclLastChange; + struct atmTrafficDescParamEntry *atmVclRxTrafficPtr; + struct atmTrafficDescParamEntry *atmVclTxTrafficPtr; + unsigned char atmVccAalType; + unsigned int atmVccAal5TxSduSize; + unsigned int atmVccAal5RxSduSize; + int atmVccAal5Encap; + int atmVclRowStatus; + int atmVclCastType; + int atmVclConnKind; + struct list_head list; + int flags; +}atmVclEntry; + + +typedef union union_atmptrs { + struct atmIfConfEntry *atmIfConfEntry_ptr; + struct atmTrafficDescParamEntry *atmTrafficDescParamEntry_ptr; + struct atmVclEntry *atmVclEntry_ptr; +}union_atmptrs; + +/* ATM Character device major number */ +#define ATM_MEI_MAJOR 107 + +/* Protocol Constants */ +#define IFX_PROTO_RAW 0 +#define IFX_PROTO_BR2684 1 +#define IFX_PROTO_PPPOATM 2 +#define IFX_PROTO_CLIP 3 + +/* IOCTL Command Set for ATM-MIB */ +#define GET_ATM_IF_CONF_DATA 0x0AB0 +#define SET_ATM_IF_CONF_DATA 0x0AB1 + +#define SET_ATM_QOS_DATA 0x0BC0 + +#define GET_ATM_VCL_DATA 0x0CD0 +#define SET_ATM_VCL_DATA 0x0CD1 + +#define FIND_VCC_IN_KERNEL 0x0DE0 + +/* User defined flags for VCL Table */ +#define ATMVCCAAL5CPCSTRANSMITSDUSIZE 9 +#define ATMVCCAAL5CPCSRECEIVESDUSIZE 10 + +#endif /* CONFIG_IFX_ATM_MIB || IFX_CONFIG_SNMP_ATM_MIB */ + +#endif //AMAZON_ATM_MIB_H diff --git a/target/linux/amazon/files/include/asm-mips/amazon/ifx_peripheral_definitions.h b/target/linux/amazon/files/include/asm-mips/amazon/ifx_peripheral_definitions.h new file mode 100644 index 0000000000..65f14e405f --- /dev/null +++ b/target/linux/amazon/files/include/asm-mips/amazon/ifx_peripheral_definitions.h @@ -0,0 +1,96 @@ +//************************************************************************* +//* Summary of definitions which are used in each peripheral * +//************************************************************************* + +#ifndef peripheral_definitions_h +#define peripheral_definitions_h + +typedef unsigned char UINT8; +typedef signed char INT8; +typedef unsigned short UINT16; +typedef signed short INT16; +typedef unsigned int UINT32; +typedef signed int INT32; +typedef unsigned long long UINT64; +typedef signed long long INT64; + +#define REG8( addr ) (*(volatile UINT8 *) (addr)) +#define REG16( addr ) (*(volatile UINT16 *)(addr)) +#define REG32( addr ) (*(volatile UINT32 *)(addr)) +#define REG64( addr ) (*(volatile UINT64 *)(addr)) + +/* define routine to set FPI access in Supervisor Mode */ +#define IFX_SUPERVISOR_ON() REG32(FB0_CFG) = 0x01 +/* Supervisor mode ends, following functions will be done in User mode */ +#define IFX_SUPERVISOR_OFF() REG32(FB0_CFG) = 0x00 +/* Supervisor mode ends, following functions will be done in User mode */ +#define IFX_SUPERVISOR_MODE() REG32(FB0_CFG) +/* Supervisor mode ends, following functions will be done in User mode */ +#define IFX_SUPERVISOR_SET(svm) REG32(FB0_CFG) = svm +/* enable all Interrupts in IIU */ +//#define IFX_ENABLE_IRQ(irq_mask, im_base) REG32(im_base | IIU_MASK) = irq_mask +///* get all high priority interrupt bits in IIU */ +//#define IFX_GET_IRQ_MASKED(im_base) REG32(im_base | IIU_IRMASKED) +///* signal ends of interrupt to IIU */ +//#define IFX_CLEAR_DIRECT_IRQ(irq_bit, im_base) REG32(im_base | IIU_IR) = irq_bit +///* force IIU interrupt register */ +//#define IFX_FORCE_IIU_REGISTER(data, im_base) REG32(im_base | IIU_IRDEBUG) = data +///* get all bits of interrupt register */ +//#define IFX_GET_IRQ_UNMASKED(im_base) REG32(im_base | IIU_IR) +/* insert a NOP instruction */ +#define NOP _nop() +/* CPU goes to power down mode until interrupt occurs */ +#define IFX_CPU_SLEEP _sleep() +/* enable all interrupts to CPU */ +#define IFX_CPU_ENABLE_ALL_INTERRUPT sys_enable_int() +/* get all low priority interrupt bits in peripheral */ +#define IFX_GET_LOW_PRIO_IRQ(int_reg) REG32(int_reg) +/* clear low priority interrupt bit in peripheral */ +#define IFX_CLEAR_LOW_PRIO_IRQ(irq_bit, int_reg) REG32(int_reg) = irq_bit +/* write FPI bus */ +#define WRITE_FPI_BYTE(data, addr) REG8(addr) = data +#define WRITE_FPI_16BIT(data, addr) REG16(addr) = data +#define WRITE_FPI_32BIT(data, addr) REG32(addr) = data +/* read FPI bus */ +#define READ_FPI_BYTE(addr) REG8(addr) +#define READ_FPI_16BIT(addr) REG16(addr) +#define READ_FPI_32BIT(addr) REG32(addr) +/* write peripheral register */ +#define WRITE_PERIPHERAL_REGISTER(data, addr) REG32(addr) = data + +#ifdef CONFIG_CPU_LITTLE_ENDIAN +#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr) = data +#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr) = data +#else //not CONFIG_CPU_LITTLE_ENDIAN +#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr+2) = data +#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr+3) = data +#endif //CONFIG_CPU_LITTLE_ENDIAN + +/* read peripheral register */ +#define READ_PERIPHERAL_REGISTER(addr) REG32(addr) + +/* read/modify(or)/write peripheral register */ +#define RMW_OR_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) | data +/* read/modify(and)/write peripheral register */ +#define RMW_AND_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) & (UINT32)data + +/* CPU-independent mnemonic constants */ +/* CLC register bits */ +#define IFX_CLC_ENABLE 0x00000000 +#define IFX_CLC_DISABLE 0x00000001 +#define IFX_CLC_DISABLE_STATUS 0x00000002 +#define IFX_CLC_SUSPEND_ENABLE 0x00000004 +#define IFX_CLC_CLOCK_OFF_DISABLE 0x00000008 +#define IFX_CLC_OVERWRITE_SPEN_FSOE 0x00000010 +#define IFX_CLC_FAST_CLOCK_SWITCH_OFF 0x00000020 +#define IFX_CLC_RUN_DIVIDER_MASK 0x0000FF00 +#define IFX_CLC_RUN_DIVIDER_OFFSET 8 +#define IFX_CLC_SLEEP_DIVIDER_MASK 0x00FF0000 +#define IFX_CLC_SLEEP_DIVIDER_OFFSET 16 +#define IFX_CLC_SPECIFIC_DIVIDER_MASK 0x00FF0000 +#define IFX_CLC_SPECIFIC_DIVIDER_OFFSET 24 + +/* number of cycles to wait for interrupt service routine to be called */ +#define WAIT_CYCLES 50 + +#endif /* PERIPHERAL_DEFINITIONS_H not yet defined */ diff --git a/target/linux/amazon/files/include/asm-mips/amazon/ifx_ssc.h b/target/linux/amazon/files/include/asm-mips/amazon/ifx_ssc.h new file mode 100644 index 0000000000..e5d73ad4ec --- /dev/null +++ b/target/linux/amazon/files/include/asm-mips/amazon/ifx_ssc.h @@ -0,0 +1,263 @@ +/* + * ifx_ssc.h defines some data sructures used in ifx_ssc.c + * + * Copyright (C) 2004 Michael Schoenenborn (IFX COM TI BT) + * + * + */ + +#ifndef __IFX_SSC_H +#define __IFX_SSC_H +#ifdef __KERNEL__ +#include <asm/amazon/ifx_ssc_defines.h> +#endif //__KERNEL__ + +#define PORT_CNT 1 // assume default value + +/* symbolic constants to be used in SSC routines */ + +// ### TO DO: bad performance +#define IFX_SSC_TXFIFO_ITL 1 +#define IFX_SSC_RXFIFO_ITL 1 + + + +struct ifx_ssc_statistics{ + unsigned int abortErr; /* abort error */ + unsigned int modeErr; /* master/slave mode error */ + unsigned int txOvErr; /* TX Overflow error */ + unsigned int txUnErr; /* TX Underrun error */ + unsigned int rxOvErr; /* RX Overflow error */ + unsigned int rxUnErr; /* RX Underrun error */ + unsigned int rxBytes; + unsigned int txBytes; +}; + + +struct ifx_ssc_hwopts { + unsigned int AbortErrDetect :1; /* Abort Error detection (in slave mode) */ + unsigned int rxOvErrDetect :1; /* Receive Overflow Error detection */ + unsigned int rxUndErrDetect :1; /* Receive Underflow Error detection */ + unsigned int txOvErrDetect :1; /* Transmit Overflow Error detection */ + unsigned int txUndErrDetect :1; /* Transmit Underflow Error detection */ + unsigned int echoMode :1; /* Echo mode */ + unsigned int loopBack :1; /* Loopback mode */ + unsigned int idleValue :1; /* Idle value */ + unsigned int clockPolarity :1; /* Idle clock is high or low */ + unsigned int clockPhase :1; /* Tx on trailing or leading edge*/ + unsigned int headingControl :1; /* LSB first or MSB first */ + unsigned int dataWidth :6; /* from 2 up to 32 bits */ + unsigned int masterSelect :1; /* Master or Slave mode */ + unsigned int modeRxTx :2; /* rx/tx mode */ + unsigned int gpoCs :8; /* choose outputs to use for chip select */ + unsigned int gpoInv :8; /* invert GPO outputs */ +}; + + +struct ifx_ssc_frm_opts { + bool FrameEnable; // SFCON.SFEN + unsigned int DataLength; // SFCON.DLEN + unsigned int PauseLength; // SFCON.PLEN + unsigned int IdleData; // SFCON.IDAT + unsigned int IdleClock; // SFCON.ICLK + bool StopAfterPause; // SFCON.STOP +}; + +struct ifx_ssc_frm_status { + bool DataBusy; // SFSTAT.DBSY + bool PauseBusy; // SFSTAT.PBSY + unsigned int DataCount; // SFSTAT.DCNT + unsigned int PauseCount; // SFSTAT.PCNT + bool EnIntAfterData; // SFCON.IBEN + bool EnIntAfterPause;// SFCON.IAEN +}; + +typedef struct { + char *buf; + size_t len; +} ifx_ssc_buf_item_t; + + +// data structures for batch execution +typedef union { + struct { + bool save_options; + } init; + ifx_ssc_buf_item_t read; + ifx_ssc_buf_item_t write; + ifx_ssc_buf_item_t rd_wr; + unsigned int set_baudrate; + struct ifx_ssc_frm_opts set_frm; + unsigned int set_gpo; + struct ifx_ssc_hwopts set_hwopts; +}ifx_ssc_batch_cmd_param; + +struct ifx_ssc_batch_list { + unsigned int cmd; + ifx_ssc_batch_cmd_param cmd_param; + struct ifx_ssc_batch_list *next; +}; + +#ifdef __KERNEL__ +#define IFX_SSC_IS_MASTER(p) ((p)->opts.masterSelect == SSC_MASTER_MODE) + + +struct ifx_ssc_port{ + unsigned long mapbase; + struct ifx_ssc_hwopts opts; + struct ifx_ssc_statistics stats; + struct ifx_ssc_frm_status frm_status; + struct ifx_ssc_frm_opts frm_opts; + /* wait queue for ifx_ssc_read() */ + wait_queue_head_t rwait, pwait; + int port_nr; + char port_is_open; /* exclusive open - boolean */ +// int no_of_bits; /* number of _valid_ bits */ +// int elem_size; /* shift for element (no of bytes)*/ + /* buffer and pointers to the read/write position */ + char *rxbuf; /* buffer for RX */ + char *rxbuf_end; /* buffer end pointer for RX */ + volatile char *rxbuf_ptr; /* buffer write pointer for RX */ + char *txbuf; /* buffer for TX */ + char *txbuf_end; /* buffer end pointer for TX */ + volatile char *txbuf_ptr; /* buffer read pointer for TX */ + unsigned int baud; + /* each channel has its own interrupts */ + /* (transmit/receive/error/frame) */ + unsigned int txirq, rxirq, errirq, frmirq; +}; +/* default values for SSC configuration */ +// values of CON +#define IFX_SSC_DEF_IDLE_DATA 1 /* enable */ +#define IFX_SSC_DEF_BYTE_VALID_CTL 1 /* enable */ +#define IFX_SSC_DEF_DATA_WIDTH 32 /* bits */ +#define IFX_SSC_DEF_ABRT_ERR_DETECT 0 /* disable */ +#define IFX_SSC_DEF_RO_ERR_DETECT 1 /* enable */ +#define IFX_SSC_DEF_RU_ERR_DETECT 0 /* disable */ +#define IFX_SSC_DEF_TO_ERR_DETECT 0 /* disable */ +#define IFX_SSC_DEF_TU_ERR_DETECT 0 /* disable */ +#define IFX_SSC_DEF_LOOP_BACK 0 /* disable */ +#define IFX_SSC_DEF_ECHO_MODE 0 /* disable */ +#define IFX_SSC_DEF_CLOCK_POLARITY 0 /* low */ +#define IFX_SSC_DEF_CLOCK_PHASE 1 /* 0: shift on leading edge, latch on trailling edge, 1, otherwise */ +#define IFX_SSC_DEF_HEADING_CONTROL IFX_SSC_MSB_FIRST +#define IFX_SSC_DEF_MODE_RXTX IFX_SSC_MODE_RXTX +// other values +#define IFX_SSC_DEF_MASTERSLAVE IFX_SSC_MASTER_MODE /* master */ +#define IFX_SSC_DEF_BAUDRATE 1000000 +#define IFX_SSC_DEF_RMC 0x10 + +#define IFX_SSC_DEF_TXFIFO_FL 8 +#define IFX_SSC_DEF_RXFIFO_FL 1 + +#if 1 //TODO +#define IFX_SSC_DEF_GPO_CS 2 /* no chip select */ +#define IFX_SSC_DEF_GPO_INV 0 /* no chip select */ +#else +#error "what is ur Chip Select???" +#endif +#define IFX_SSC_DEF_SFCON 0 /* no serial framing */ +#if 0 +#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\ + IFX_SSC_R_BIT | IFX_SSC_E_BIT | IFX_SSC_F_BIT +#endif +#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\ + IFX_SSC_R_BIT | IFX_SSC_E_BIT +#endif /* __KERNEL__ */ + +// batch execution commands +#define IFX_SSC_BATCH_CMD_INIT 1 +#define IFX_SSC_BATCH_CMD_READ 2 +#define IFX_SSC_BATCH_CMD_WRITE 3 +#define IFX_SSC_BATCH_CMD_RD_WR 4 +#define IFX_SSC_BATCH_CMD_SET_BAUDRATE 5 +#define IFX_SSC_BATCH_CMD_SET_HWOPTS 6 +#define IFX_SSC_BATCH_CMD_SET_FRM 7 +#define IFX_SSC_BATCH_CMD_SET_GPO 8 +#define IFX_SSC_BATCH_CMD_FIFO_FLUSH 9 +//#define IFX_SSC_BATCH_CMD_ +//#define IFX_SSC_BATCH_CMD_ +#define IFX_SSC_BATCH_CMD_END_EXEC 0 + +/* Macros to configure SSC hardware */ +/* headingControl: */ +#define IFX_SSC_LSB_FIRST 0 +#define IFX_SSC_MSB_FIRST 1 +/* dataWidth: */ +#define IFX_SSC_MIN_DATA_WIDTH 2 +#define IFX_SSC_MAX_DATA_WIDTH 32 +/* master/slave mode select */ +#define IFX_SSC_MASTER_MODE 1 +#define IFX_SSC_SLAVE_MODE 0 +/* rx/tx mode */ +// ### TO DO: !!! ATTENTION! Hardware dependency => move to ifx_ssc_defines.h +#define IFX_SSC_MODE_RXTX 0 +#define IFX_SSC_MODE_RX 1 +#define IFX_SSC_MODE_TX 2 +#define IFX_SSC_MODE_OFF 3 +#define IFX_SSC_MODE_MASK IFX_SSC_MODE_RX | IFX_SSC_MODE_TX + +/* GPO values */ +#define IFX_SSC_MAX_GPO_OUT 7 + +#define IFX_SSC_RXREQ_BLOCK_SIZE 32768 + +/***********************/ +/* defines for ioctl's */ +/***********************/ +#define IFX_SSC_IOCTL_MAGIC 'S' +/* read out the statistics */ +#define IFX_SSC_STATS_READ _IOR(IFX_SSC_IOCTL_MAGIC, 1, struct ifx_ssc_statistics) +/* clear the statistics */ +#define IFX_SSC_STATS_RESET _IO(IFX_SSC_IOCTL_MAGIC, 2) +/* set the baudrate */ +#define IFX_SSC_BAUD_SET _IOW(IFX_SSC_IOCTL_MAGIC, 3, unsigned int) +/* get the current baudrate */ +#define IFX_SSC_BAUD_GET _IOR(IFX_SSC_IOCTL_MAGIC, 4, unsigned int) +/* set hardware options */ +#define IFX_SSC_HWOPTS_SET _IOW(IFX_SSC_IOCTL_MAGIC, 5, struct ifx_ssc_hwopts) +/* get the current hardware options */ +#define IFX_SSC_HWOPTS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 6, struct ifx_ssc_hwopts) +/* set transmission mode */ +#define IFX_SSC_RXTX_MODE_SET _IOW(IFX_SSC_IOCTL_MAGIC, 7, unsigned int) +/* get the current transmission mode */ +#define IFX_SSC_RXTX_MODE_GET _IOR(IFX_SSC_IOCTL_MAGIC, 8, unsigned int) +/* abort transmission */ +#define IFX_SSC_ABORT _IO(IFX_SSC_IOCTL_MAGIC, 9) +#define IFX_SSC_FIFO_FLUSH _IO(IFX_SSC_IOCTL_MAGIC, 9) + +/* set general purpose outputs */ +#define IFX_SSC_GPO_OUT_SET _IOW(IFX_SSC_IOCTL_MAGIC, 32, unsigned int) +/* clear general purpose outputs */ +#define IFX_SSC_GPO_OUT_CLR _IOW(IFX_SSC_IOCTL_MAGIC, 33, unsigned int) +/* get general purpose outputs */ +#define IFX_SSC_GPO_OUT_GET _IOR(IFX_SSC_IOCTL_MAGIC, 34, unsigned int) + +/*** serial framing ***/ +/* get status of serial framing */ +#define IFX_SSC_FRM_STATUS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 48, struct ifx_ssc_frm_status) +/* get counter reload values and control bits */ +#define IFX_SSC_FRM_CONTROL_GET _IOR(IFX_SSC_IOCTL_MAGIC, 49, struct ifx_ssc_frm_opts) +/* set counter reload values and control bits */ +#define IFX_SSC_FRM_CONTROL_SET _IOW(IFX_SSC_IOCTL_MAGIC, 50, struct ifx_ssc_frm_opts) + + +/*** batch execution ***/ +/* do batch execution */ +#define IFX_SSC_BATCH_EXEC _IOW(IFX_SSC_IOCTL_MAGIC, 64, struct ifx_ssc_batch_list) + + +#ifdef __KERNEL__ +// routines from ifx_ssc.c +// ### TO DO +/* kernel interface for read and write */ +ssize_t ifx_ssc_kread(int, char *, size_t); +ssize_t ifx_ssc_kwrite(int, const char *, size_t); + +#ifdef CONFIG_IFX_VP_KERNEL_TEST +void ifx_ssc_tc(void); +#endif // CONFIG_IFX_VP_KERNEL_TEST + +#endif //__KERNEL__ +#endif // __IFX_SSC_H + diff --git a/target/linux/amazon/files/include/asm-mips/amazon/ifx_ssc_defines.h b/target/linux/amazon/files/include/asm-mips/amazon/ifx_ssc_defines.h new file mode 100644 index 0000000000..46157dcbd6 --- /dev/null +++ b/target/linux/amazon/files/include/asm-mips/amazon/ifx_ssc_defines.h @@ -0,0 +1,552 @@ +#ifndef IFX_SSC_DEFINES_H +#define IFX_SSC_DEFINES_H + +#include "ifx_peripheral_definitions.h" + +/* maximum SSC FIFO size */ +#define IFX_SSC_MAX_FIFO_SIZE 32 + +/* register map of SSC */ + +/* address of the Clock Control Register of the SSC */ +#define IFX_SSC_CLC 0x00000000 +/* IFX_SSC_CLC register is significant in bits 23 downto 8 and in bits 5, 3, 2, 0 + bit 1 is hardware modified*/ +#define IFX_SSC_CLC_readmask 0x00FFFFEF +#define IFX_SSC_CLC_writemask 0x00FFFF3D +#define IFX_SSC_CLC_hwmask 0x00000002 +#define IFX_SSC_CLC_dontcare (IFX_SSC_CLC_readmask & IFX_SSC_CLC_writemask & ~IFX_SSC_CLC_hwmask) + +/* address of Port Input Select Register of the SSC */ +#define IFX_SSC_PISEL 0x00000004 +/* IFX_SSC_PISEL register is significant in lowest three bits only */ +#define IFX_SSC_PISEL_readmask 0x00000007 +#define IFX_SSC_PISEL_writemask 0x00000007 +#define IFX_SSC_PISEL_hwmask 0x00000000 +#define IFX_SSC_PISEL_dontcare (IFX_SSC_PISEL_readmask & IFX_SSC_PISEL_writemask & ~IFX_SSC_PISEL_hwmask) + +/* address of Identification Register of the SSC */ +#define IFX_SSC_ID 0x00000008 +/* IFX_SSC_ID register is significant in no bit */ +#define IFX_SSC_ID_readmask 0x0000FF3F +#define IFX_SSC_ID_writemask 0x00000000 +#define IFX_SSC_ID_hwmask 0x00000000 +#define IFX_SSC_ID_dontcare (IFX_SSC_ID_readmask & IFX_SSC_ID_writemask & ~IFX_SSC_ID_hwmask) + +/* address of the Control Register of the SSC */ +#define IFX_SSC_CON 0x00000010 +/* IFX_SSC_CON register is significant in bits 23:22, 20:16 and 12:0 */ +#define IFX_SSC_CON_readmask 0x01DF1FFF +#define IFX_SSC_CON_writemask 0x01DF1FFF +#define IFX_SSC_CON_hwmask 0x00000000 +#define IFX_SSC_CON_dontcare (IFX_SSC_CON_readmask & IFX_SSC_CON_writemask & ~IFX_SSC_CON_hwmask) + + +/* address of the Status Register of the SSC */ +#define IFX_SSC_STATE 0x00000014 +/* IFX_SSC_STATE register is readable in bits 30:28, 26:24, 20:16, 12:7 and 2:0 + all bits except 1:0 are hardware modified */ +#define IFX_SSC_STATE_readmask 0x771F3F87 +#define IFX_SSC_STATE_writemask 0x00000000 +#define IFX_SSC_STATE_hwmask 0x771F3F84 +#define IFX_SSC_STATE_dontcare (IFX_SSC_STATE_readmask & IFX_SSC_STATE_writemask & ~IFX_SSC_STATE_hwmask) + +/* address of the Write Hardware Modified Control Register Bits of the SSC */ +#define IFX_SSC_WHBSTATE 0x00000018 +/* IFX_SSC_WHBSTATE register is write only */ +#define IFX_SSC_WHBSTATE_readmask 0x00000000 +#define IFX_SSC_WHBSTATE_writemask 0x0000FFFF +#define IFX_SSC_WHBSTATE_hwmask 0x00000000 +#define IFX_SSC_WHBSTATE_dontcare (IFX_SSC_WHBSTATE_readmask & IFX_SSC_WHBSTATE_writemask & ~IFX_SSC_WHBSTATE_hwmask) + +/* address of the Baudrate Timer Reload Register of the SSC */ +#define IFX_SSC_BR 0x00000040 +/* IFX_SSC_BR register is significant in bit 15 downto 0*/ +#define IFX_SSC_BR_readmask 0x0000FFFF +#define IFX_SSC_BR_writemask 0x0000FFFF +#define IFX_SSC_BR_hwmask 0x00000000 +#define IFX_SSC_BR_dontcare (IFX_SSC_BR_readmask & IFX_SSC_BR_writemask & ~IFX_SSC_BR_hwmask) + +/* address of the Baudrate Timer Status Register of the SSC */ +#define IFX_SSC_BRSTAT 0x00000044 +/* IFX_SSC_BRSTAT register is significant in bit 15 downto 0*/ +#define IFX_SSC_BRSTAT_readmask 0x0000FFFF +#define IFX_SSC_BRSTAT_writemask 0x00000000 +#define IFX_SSC_BRSTAT_hwmask 0x0000FFFF +#define IFX_SSC_BRSTAT_dontcare (IFX_SSC_BRSTAT_readmask & IFX_SSC_BRSTAT_writemask & ~IFX_SSC_BRSTAT_hwmask) + +/* address of the Transmitter Buffer Register of the SSC */ +#define IFX_SSC_TB 0x00000020 +/* IFX_SSC_TB register is significant in bit 31 downto 0*/ +#define IFX_SSC_TB_readmask 0xFFFFFFFF +#define IFX_SSC_TB_writemask 0xFFFFFFFF +#define IFX_SSC_TB_hwmask 0x00000000 +#define IFX_SSC_TB_dontcare (IFX_SSC_TB_readmask & IFX_SSC_TB_writemask & ~IFX_SSC_TB_hwmask) + +/* address of the Reciver Buffer Register of the SSC */ +#define IFX_SSC_RB 0x00000024 +/* IFX_SSC_RB register is significant in no bits*/ +#define IFX_SSC_RB_readmask 0xFFFFFFFF +#define IFX_SSC_RB_writemask 0x00000000 +#define IFX_SSC_RB_hwmask 0xFFFFFFFF +#define IFX_SSC_RB_dontcare (IFX_SSC_RB_readmask & IFX_SSC_RB_writemask & ~IFX_SSC_RB_hwmask) + +/* address of the Receive FIFO Control Register of the SSC */ +#define IFX_SSC_RXFCON 0x00000030 +/* IFX_SSC_RXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */ +#define IFX_SSC_RXFCON_readmask 0x00003F03 +#define IFX_SSC_RXFCON_writemask 0x00003F03 +#define IFX_SSC_RXFCON_hwmask 0x00000000 +#define IFX_SSC_RXFCON_dontcare (IFX_SSC_RXFCON_readmask & IFX_SSC_RXFCON_writemask & ~IFX_SSC_RXFCON_hwmask) + +/* address of the Transmit FIFO Control Register of the SSC */ +#define IFX_SSC_TXFCON 0x00000034 +/* IFX_SSC_TXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */ +#define IFX_SSC_TXFCON_readmask 0x00003F03 +#define IFX_SSC_TXFCON_writemask 0x00003F03 +#define IFX_SSC_TXFCON_hwmask 0x00000000 +#define IFX_SSC_TXFCON_dontcare (IFX_SSC_TXFCON_readmask & IFX_SSC_TXFCON_writemask & ~IFX_SSC_TXFCON_hwmask) + +/* address of the FIFO Status Register of the SSC */ +#define IFX_SSC_FSTAT 0x00000038 +/* IFX_SSC_FSTAT register is significant in no bit*/ +#define IFX_SSC_FSTAT_readmask 0x00003F3F +#define IFX_SSC_FSTAT_writemask 0x00000000 +#define IFX_SSC_FSTAT_hwmask 0x00003F3F +#define IFX_SSC_FSTAT_dontcare (IFX_SSC_FSTAT_readmask & IFX_SSC_FSTAT_writemask & ~IFX_SSC_FSTAT_hwmask) + +/* address of the Data Frame Control register of the SSC */ +#define IFX_SSC_SFCON 0x00000060 +#define IFX_SSC_SFCON_readmask 0xFFDFFFFD +#define IFX_SSC_SFCON_writemask 0xFFDFFFFD +#define IFX_SSC_SFCON_hwmask 0x00000000 +#define IFX_SSC_SFCON_dontcare (IFX_SSC_SFCON_readmask & IFX_SSC_SFCON_writemask & ~IFX_SSC_SFCON_hwmask) + +/* address of the Data Frame Status register of the SSC */ +#define IFX_SSC_SFSTAT 0x00000064 +#define IFX_SSC_SFSTAT_readmask 0xFFC0FFF3 +#define IFX_SSC_SFSTAT_writemask 0x00000000 +#define IFX_SSC_SFSTAT_hwmask 0xFFC0FFF3 +#define IFX_SSC_SFSTAT_dontcare (IFX_SSC_SFSTAT_readmask & IFX_SSC_SFSTAT_writemask & ~IFX_SSC_SFSTAT_hwmask) + +/* address of the General Purpose Output Control register of the SSC */ +#define IFX_SSC_GPOCON 0x00000070 +#define IFX_SSC_GPOCON_readmask 0x0000FFFF +#define IFX_SSC_GPOCON_writemask 0x0000FFFF +#define IFX_SSC_GPOCON_hwmask 0x00000000 +#define IFX_SSC_GPOCON_dontcare (IFX_SSC_GPOCON_readmask & IFX_SSC_GPOCON_writemask & ~IFX_SSC_GPOCON_hwmask) + +/* address of the General Purpose Output Status register of the SSC */ +#define IFX_SSC_GPOSTAT 0x00000074 +#define IFX_SSC_GPOSTAT_readmask 0x000000FF +#define IFX_SSC_GPOSTAT_writemask 0x00000000 +#define IFX_SSC_GPOSTAT_hwmask 0x00000000 +#define IFX_SSC_GPOSTAT_dontcare (IFX_SSC_GPOSTAT_readmask & IFX_SSC_GPOSTAT_writemask & ~IFX_SSC_GPOSTAT_hwmask) + +/* address of the Force GPO Status register of the SSC */ +#define IFX_SSC_WHBGPOSTAT 0x00000078 +#define IFX_SSC_WHBGPOSTAT_readmask 0x00000000 +#define IFX_SSC_WHBGPOSTAT_writemask 0x0000FFFF +#define IFX_SSC_WHBGPOSTAT_hwmask 0x00000000 +#define IFX_SSC_WHBGPOSTAT_dontcare (IFX_SSC_WHBGPOSTAT_readmask & IFX_SSC_WHBGPOSTAT_writemask & ~IFX_SSC_WHBGPOSTAT_hwmask) + +/* address of the Receive Request Register of the SSC */ +#define IFX_SSC_RXREQ 0x00000080 +#define IFX_SSC_RXREQ_readmask 0x0000FFFF +#define IFX_SSC_RXREQ_writemask 0x0000FFFF +#define IFX_SSC_RXREQ_hwmask 0x00000000 +#define IFX_SSC_RXREQ_dontcare (IFX_SSC_RXREQ_readmask & IFX_SSC_RXREQ_writemask & ~IFX_SSC_RXREQ_hwmask) + +/* address of the Receive Count Register of the SSC */ +#define IFX_SSC_RXCNT 0x00000084 +#define IFX_SSC_RXCNT_readmask 0x0000FFFF +#define IFX_SSC_RXCNT_writemask 0x00000000 +#define IFX_SSC_RXCNT_hwmask 0x0000FFFF +#define IFX_SSC_RXCNT_dontcare (IFX_SSC_RXCNT_readmask & IFX_SSC_RXCNT_writemask & ~IFX_SSC_RXCNT_hwmask) + +/* address of the DMA Configuration Register of the SSC */ +#define IFX_SSC_DMACON 0x000000EC +#define IFX_SSC_DMACON_readmask 0x0000FFFF +#define IFX_SSC_DMACON_writemask 0x00000000 +#define IFX_SSC_DMACON_hwmask 0x0000FFFF +#define IFX_SSC_DMACON_dontcare (IFX_SSC_DMACON_readmask & IFX_SSC_DMACON_writemask & ~IFX_SSC_DMACON_hwmask) + +//------------------------------------------------------ +// interrupt register for enabling interrupts, mask register of irq_reg +#define IFX_SSC_IRN_EN 0xF4 +// read/write +#define IFX_SSC_IRN_EN_readmask 0x0000000F +#define IFX_SSC_IRN_EN_writemask 0x0000000F +#define IFX_SSC_IRN_EN_hwmask 0x00000000 +#define IFX_SSC_IRN_EN_dontcare (IFX_SSC_IRN_EN_readmask & IFX_SSC_IRN_EN_writemask & ~IFX_SSC_IRN_EN_hwmask) + +// interrupt register for accessing interrupts +#define IFX_SSC_IRN_CR 0xF8 +// read/write +#define IFX_SSC_IRN_CR_readmask 0x0000000F +#define IFX_SSC_IRN_CR_writemask 0x0000000F +#define IFX_SSC_IRN_CR_hwmask 0x0000000F +#define IFX_SSC_IRN_CR_dontcare (IFX_SSC_IRN_CR_readmask & IFX_SSC_IRN_CR_writemask & ~IFX_SSC_IRN_CR_hwmask) + +// interrupt register for stimulating interrupts +#define IFX_SSC_IRN_ICR 0xFC +// read/write +#define IFX_SSC_IRN_ICR_readmask 0x0000000F +#define IFX_SSC_IRN_ICR_writemask 0x0000000F +#define IFX_SSC_IRN_ICR_hwmask 0x00000000 +#define IFX_SSC_IRN_ICR_dontcare (IFX_SSC_IRN_ICR_readmask & IFX_SSC_IRN_ICR_writemask & ~IFX_SSC_IRN_ICR_hwmask) + +//--------------------------------------------------------------------- +// Number of IRQs and bitposition of IRQ +#define IFX_SSC_NUM_IRQ 4 +#define IFX_SSC_T_BIT 0x00000001 +#define IFX_SSC_R_BIT 0x00000002 +#define IFX_SSC_E_BIT 0x00000004 +#define IFX_SSC_F_BIT 0x00000008 + +/* bit masks for SSC registers */ + +/* ID register */ +#define IFX_SSC_PERID_REV_MASK 0x0000001F +#define IFX_SSC_PERID_CFG_MASK 0x00000020 +#define IFX_SSC_PERID_ID_MASK 0x0000FF00 +#define IFX_SSC_PERID_REV_OFFSET 0 +#define IFX_SSC_PERID_CFG_OFFSET 5 +#define IFX_SSC_PERID_ID_OFFSET 8 +#define IFX_SSC_PERID_ID 0x45 +#define IFX_SSC_PERID_DMA_ON 0x00000020 +#define IFX_SSC_PERID_RXFS_MASK 0x003F0000 +#define IFX_SSC_PERID_RXFS_OFFSET 16 +#define IFX_SSC_PERID_TXFS_MASK 0x3F000000 +#define IFX_SSC_PERID_TXFS_OFFSET 24 + +/* PISEL register */ +#define IFX_SSC_PISEL_MASTER_IN_A 0x0000 +#define IFX_SSC_PISEL_MASTER_IN_B 0x0001 +#define IFX_SSC_PISEL_SLAVE_IN_A 0x0000 +#define IFX_SSC_PISEL_SLAVE_IN_B 0x0002 +#define IFX_SSC_PISEL_CLOCK_IN_A 0x0000 +#define IFX_SSC_PISEL_CLOCK_IN_B 0x0004 + + +/* IFX_SSC_CON register */ +#define IFX_SSC_CON_ECHO_MODE_ON 0x01000000 +#define IFX_SSC_CON_ECHO_MODE_OFF 0x00000000 +#define IFX_SSC_CON_IDLE_HIGH 0x00800000 +#define IFX_SSC_CON_IDLE_LOW 0x00000000 +#define IFX_SSC_CON_ENABLE_BYTE_VALID 0x00400000 +#define IFX_SSC_CON_DISABLE_BYTE_VALID 0x00000000 +#define IFX_SSC_CON_DATA_WIDTH_OFFSET 16 +#define IFX_SSC_CON_DATA_WIDTH_MASK 0x001F0000 +#define IFX_SSC_ENCODE_DATA_WIDTH(width) (((width - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET) & IFX_SSC_CON_DATA_WIDTH_MASK) + +#define IFX_SSC_CON_RESET_ON_BAUDERR 0x00002000 +#define IFX_SSC_CON_GO_ON_ON_BAUDERR 0x00000000 + +#define IFX_SSC_CON_RX_UFL_CHECK 0x00001000 +#define IFX_SSC_CON_RX_UFL_IGNORE 0x00000000 +#define IFX_SSC_CON_TX_UFL_CHECK 0x00000800 +#define IFX_SSC_CON_TX_UFL_IGNORE 0x00000000 +#define IFX_SSC_CON_ABORT_ERR_CHECK 0x00000400 +#define IFX_SSC_CON_ABORT_ERR_IGNORE 0x00000000 +#define IFX_SSC_CON_RX_OFL_CHECK 0x00000200 +#define IFX_SSC_CON_RX_OFL_IGNORE 0x00000000 +#define IFX_SSC_CON_TX_OFL_CHECK 0x00000100 +#define IFX_SSC_CON_TX_OFL_IGNORE 0x00000000 +#define IFX_SSC_CON_ALL_ERR_CHECK 0x00001F00 +#define IFX_SSC_CON_ALL_ERR_IGNORE 0x00000000 + +#define IFX_SSC_CON_LOOPBACK_MODE 0x00000080 +#define IFX_SSC_CON_NO_LOOPBACK 0x00000000 +#define IFX_SSC_CON_HALF_DUPLEX 0x00000080 +#define IFX_SSC_CON_FULL_DUPLEX 0x00000000 +#define IFX_SSC_CON_CLOCK_FALL 0x00000040 +#define IFX_SSC_CON_CLOCK_RISE 0x00000000 +#define IFX_SSC_CON_SHIFT_THEN_LATCH 0x00000000 +#define IFX_SSC_CON_LATCH_THEN_SHIFT 0x00000020 +#define IFX_SSC_CON_MSB_FIRST 0x00000010 +#define IFX_SSC_CON_LSB_FIRST 0x00000000 +#define IFX_SSC_CON_ENABLE_CSB 0x00000008 +#define IFX_SSC_CON_DISABLE_CSB 0x00000000 +#define IFX_SSC_CON_INVERT_CSB 0x00000004 +#define IFX_SSC_CON_TRUE_CSB 0x00000000 +#define IFX_SSC_CON_RX_OFF 0x00000002 +#define IFX_SSC_CON_RX_ON 0x00000000 +#define IFX_SSC_CON_TX_OFF 0x00000001 +#define IFX_SSC_CON_TX_ON 0x00000000 + + +/* IFX_SSC_STATE register */ +#define IFX_SSC_STATE_RX_BYTE_VALID_OFFSET 28 +#define IFX_SSC_STATE_RX_BYTE_VALID_MASK 0x70000000 +#define IFX_SSC_DECODE_RX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET) +#define IFX_SSC_STATE_TX_BYTE_VALID_OFFSET 24 +#define IFX_SSC_STATE_TX_BYTE_VALID_MASK 0x07000000 +#define IFX_SSC_DECODE_TX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_TX_BYTE_VALID_MASK) >> IFX_SSC_STATE_TX_BYTE_VALID_OFFSET) +#define IFX_SSC_STATE_BIT_COUNT_OFFSET 16 +#define IFX_SSC_STATE_BIT_COUNT_MASK 0x001F0000 +#define IFX_SSC_DECODE_DATA_WIDTH(con_state) (((con_state & IFX_SSC_STATE_BIT_COUNT_MASK) >> IFX_SSC_STATE_BIT_COUNT_OFFSET) + 1) +#define IFX_SSC_STATE_BUSY 0x00002000 +#define IFX_SSC_STATE_RX_UFL 0x00001000 +#define IFX_SSC_STATE_TX_UFL 0x00000800 +#define IFX_SSC_STATE_ABORT_ERR 0x00000400 +#define IFX_SSC_STATE_RX_OFL 0x00000200 +#define IFX_SSC_STATE_TX_OFL 0x00000100 +#define IFX_SSC_STATE_MODE_ERR 0x00000080 +#define IFX_SSC_STATE_SLAVE_IS_SELECTED 0x00000004 +#define IFX_SSC_STATE_IS_MASTER 0x00000002 +#define IFX_SSC_STATE_IS_ENABLED 0x00000001 + +/* WHBSTATE register */ +#define IFX_SSC_WHBSTATE_DISABLE_SSC 0x0001 +#define IFX_SSC_WHBSTATE_CONFIGURATION_MODE 0x0001 +#define IFX_SSC_WHBSTATE_CLR_ENABLE 0x0001 + +#define IFX_SSC_WHBSTATE_ENABLE_SSC 0x0002 +#define IFX_SSC_WHBSTATE_RUN_MODE 0x0002 +#define IFX_SSC_WHBSTATE_SET_ENABLE 0x0002 + +#define IFX_SSC_WHBSTATE_SLAVE_MODE 0x0004 +#define IFX_SSC_WHBSTATE_CLR_MASTER_SELECT 0x0004 + +#define IFX_SSC_WHBSTATE_MASTER_MODE 0x0008 +#define IFX_SSC_WHBSTATE_SET_MASTER_SELECT 0x0008 + +#define IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR 0x0010 +#define IFX_SSC_WHBSTATE_SET_RX_UFL_ERROR 0x0020 + +#define IFX_SSC_WHBSTATE_CLR_MODE_ERROR 0x0040 +#define IFX_SSC_WHBSTATE_SET_MODE_ERROR 0x0080 + +#define IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR 0x0100 +#define IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR 0x0200 +#define IFX_SSC_WHBSTATE_CLR_ABORT_ERROR 0x0400 +#define IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR 0x0800 +#define IFX_SSC_WHBSTATE_SET_TX_OFL_ERROR 0x1000 +#define IFX_SSC_WHBSTATE_SET_RX_OFL_ERROR 0x2000 +#define IFX_SSC_WHBSTATE_SET_ABORT_ERROR 0x4000 +#define IFX_SSC_WHBSTATE_SET_TX_UFL_ERROR 0x8000 +#define IFX_SSC_WHBSTATE_CLR_ALL_ERROR 0x0F50 +#define IFX_SSC_WHBSTATE_SET_ALL_ERROR 0xF0A0 + +/* BR register */ +#define IFX_SSC_BR_BAUDRATE_OFFSET 0 +#define IFX_SSC_BR_BAUDRATE_MASK 0xFFFF + +/* BR_STAT register */ +#define IFX_SSC_BRSTAT_BAUDTIMER_OFFSET 0 +#define IFX_SSC_BRSTAT_BAUDTIMER_MASK 0xFFFF + +/* TB register */ +#define IFX_SSC_TB_DATA_OFFSET 0 +#define IFX_SSC_TB_DATA_MASK 0xFFFFFFFF + +/* RB register */ +#define IFX_SSC_RB_DATA_OFFSET 0 +#define IFX_SSC_RB_DATA_MASK 0xFFFFFFFF + + +/* RXFCON and TXFCON registers */ +#define IFX_SSC_XFCON_FIFO_DISABLE 0x0000 +#define IFX_SSC_XFCON_FIFO_ENABLE 0x0001 +#define IFX_SSC_XFCON_FIFO_FLUSH 0x0002 +#define IFX_SSC_XFCON_ITL_MASK 0x00003F00 +#define IFX_SSC_XFCON_ITL_OFFSET 8 + +/* FSTAT register */ +#define IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET 0 +#define IFX_SSC_FSTAT_RECEIVED_WORDS_MASK 0x003F +#define IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET 8 +#define IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK 0x3F00 + +/* GPOCON register */ +#define IFX_SSC_GPOCON_INVOUT0_POS 0 +#define IFX_SSC_GPOCON_INV_OUT0 0x00000001 +#define IFX_SSC_GPOCON_TRUE_OUT0 0x00000000 +#define IFX_SSC_GPOCON_INVOUT1_POS 1 +#define IFX_SSC_GPOCON_INV_OUT1 0x00000002 +#define IFX_SSC_GPOCON_TRUE_OUT1 0x00000000 +#define IFX_SSC_GPOCON_INVOUT2_POS 2 +#define IFX_SSC_GPOCON_INV_OUT2 0x00000003 +#define IFX_SSC_GPOCON_TRUE_OUT2 0x00000000 +#define IFX_SSC_GPOCON_INVOUT3_POS 3 +#define IFX_SSC_GPOCON_INV_OUT3 0x00000008 +#define IFX_SSC_GPOCON_TRUE_OUT3 0x00000000 +#define IFX_SSC_GPOCON_INVOUT4_POS 4 +#define IFX_SSC_GPOCON_INV_OUT4 0x00000010 +#define IFX_SSC_GPOCON_TRUE_OUT4 0x00000000 +#define IFX_SSC_GPOCON_INVOUT5_POS 5 +#define IFX_SSC_GPOCON_INV_OUT5 0x00000020 +#define IFX_SSC_GPOCON_TRUE_OUT5 0x00000000 +#define IFX_SSC_GPOCON_INVOUT6_POS 6 +#define IFX_SSC_GPOCON_INV_OUT6 0x00000040 +#define IFX_SSC_GPOCON_TRUE_OUT6 0x00000000 +#define IFX_SSC_GPOCON_INVOUT7_POS 7 +#define IFX_SSC_GPOCON_INV_OUT7 0x00000080 +#define IFX_SSC_GPOCON_TRUE_OUT7 0x00000000 +#define IFX_SSC_GPOCON_INV_OUT_ALL 0x000000FF +#define IFX_SSC_GPOCON_TRUE_OUT_ALL 0x00000000 + +#define IFX_SSC_GPOCON_ISCSB0_POS 8 +#define IFX_SSC_GPOCON_IS_CSB0 0x00000100 +#define IFX_SSC_GPOCON_IS_GPO0 0x00000000 +#define IFX_SSC_GPOCON_ISCSB1_POS 9 +#define IFX_SSC_GPOCON_IS_CSB1 0x00000200 +#define IFX_SSC_GPOCON_IS_GPO1 0x00000000 +#define IFX_SSC_GPOCON_ISCSB2_POS 10 +#define IFX_SSC_GPOCON_IS_CSB2 0x00000400 +#define IFX_SSC_GPOCON_IS_GPO2 0x00000000 +#define IFX_SSC_GPOCON_ISCSB3_POS 11 +#define IFX_SSC_GPOCON_IS_CSB3 0x00000800 +#define IFX_SSC_GPOCON_IS_GPO3 0x00000000 +#define IFX_SSC_GPOCON_ISCSB4_POS 12 +#define IFX_SSC_GPOCON_IS_CSB4 0x00001000 +#define IFX_SSC_GPOCON_IS_GPO4 0x00000000 +#define IFX_SSC_GPOCON_ISCSB5_POS 13 +#define IFX_SSC_GPOCON_IS_CSB5 0x00002000 +#define IFX_SSC_GPOCON_IS_GPO5 0x00000000 +#define IFX_SSC_GPOCON_ISCSB6_POS 14 +#define IFX_SSC_GPOCON_IS_CSB6 0x00004000 +#define IFX_SSC_GPOCON_IS_GPO6 0x00000000 +#define IFX_SSC_GPOCON_ISCSB7_POS 15 +#define IFX_SSC_GPOCON_IS_CSB7 0x00008000 +#define IFX_SSC_GPOCON_IS_GPO7 0x00000000 +#define IFX_SSC_GPOCON_IS_CSB_ALL 0x0000FF00 +#define IFX_SSC_GPOCON_IS_GPO_ALL 0x00000000 + +/* GPOSTAT register */ +#define IFX_SSC_GPOSTAT_OUT0 0x00000001 +#define IFX_SSC_GPOSTAT_OUT1 0x00000002 +#define IFX_SSC_GPOSTAT_OUT2 0x00000004 +#define IFX_SSC_GPOSTAT_OUT3 0x00000008 +#define IFX_SSC_GPOSTAT_OUT4 0x00000010 +#define IFX_SSC_GPOSTAT_OUT5 0x00000020 +#define IFX_SSC_GPOSTAT_OUT6 0x00000040 +#define IFX_SSC_GPOSTAT_OUT7 0x00000080 +#define IFX_SSC_GPOSTAT_OUT_ALL 0x000000FF + +/* WHBGPOSTAT register */ +#define IFX_SSC_WHBGPOSTAT_CLROUT0_POS 0 +#define IFX_SSC_WHBGPOSTAT_CLR_OUT0 0x00000001 +#define IFX_SSC_WHBGPOSTAT_CLROUT1_POS 1 +#define IFX_SSC_WHBGPOSTAT_CLR_OUT1 0x00000002 +#define IFX_SSC_WHBGPOSTAT_CLROUT2_POS 2 +#define IFX_SSC_WHBGPOSTAT_CLR_OUT2 0x00000004 +#define IFX_SSC_WHBGPOSTAT_CLROUT3_POS 3 +#define IFX_SSC_WHBGPOSTAT_CLR_OUT3 0x00000008 +#define IFX_SSC_WHBGPOSTAT_CLROUT4_POS 4 +#define IFX_SSC_WHBGPOSTAT_CLR_OUT4 0x00000010 +#define IFX_SSC_WHBGPOSTAT_CLROUT5_POS 5 +#define IFX_SSC_WHBGPOSTAT_CLR_OUT5 0x00000020 +#define IFX_SSC_WHBGPOSTAT_CLROUT6_POS 6 +#define IFX_SSC_WHBGPOSTAT_CLR_OUT6 0x00000040 +#define IFX_SSC_WHBGPOSTAT_CLROUT7_POS 7 +#define IFX_SSC_WHBGPOSTAT_CLR_OUT7 0x00000080 +#define IFX_SSC_WHBGPOSTAT_CLR_OUT_ALL 0x000000FF + +#define IFX_SSC_WHBGPOSTAT_OUT0_POS 0 +#define IFX_SSC_WHBGPOSTAT_OUT1_POS 1 +#define IFX_SSC_WHBGPOSTAT_OUT2_POS 2 +#define IFX_SSC_WHBGPOSTAT_OUT3_POS 3 +#define IFX_SSC_WHBGPOSTAT_OUT4_POS 4 +#define IFX_SSC_WHBGPOSTAT_OUT5_POS 5 +#define IFX_SSC_WHBGPOSTAT_OUT6_POS 6 +#define IFX_SSC_WHBGPOSTAT_OUT7_POS 7 + + +#define IFX_SSC_WHBGPOSTAT_SETOUT0_POS 8 +#define IFX_SSC_WHBGPOSTAT_SET_OUT0 0x00000100 +#define IFX_SSC_WHBGPOSTAT_SETOUT1_POS 9 +#define IFX_SSC_WHBGPOSTAT_SET_OUT1 0x00000200 +#define IFX_SSC_WHBGPOSTAT_SETOUT2_POS 10 +#define IFX_SSC_WHBGPOSTAT_SET_OUT2 0x00000400 +#define IFX_SSC_WHBGPOSTAT_SETOUT3_POS 11 +#define IFX_SSC_WHBGPOSTAT_SET_OUT3 0x00000800 +#define IFX_SSC_WHBGPOSTAT_SETOUT4_POS 12 +#define IFX_SSC_WHBGPOSTAT_SET_OUT4 0x00001000 +#define IFX_SSC_WHBGPOSTAT_SETOUT5_POS 13 +#define IFX_SSC_WHBGPOSTAT_SET_OUT5 0x00002000 +#define IFX_SSC_WHBGPOSTAT_SETOUT6_POS 14 +#define IFX_SSC_WHBGPOSTAT_SET_OUT6 0x00004000 +#define IFX_SSC_WHBGPOSTAT_SETOUT7_POS 15 +#define IFX_SSC_WHBGPOSTAT_SET_OUT7 0x00008000 +#define IFX_SSC_WHBGPOSTAT_SET_OUT_ALL 0x0000FF00 + +/* SFCON register */ +#define IFX_SSC_SFCON_SF_ENABLE 0x00000001 +#define IFX_SSC_SFCON_SF_DISABLE 0x00000000 +#define IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE 0x00000004 +#define IFX_SSC_SFCON_FIR_DISABLE_BEFORE_PAUSE 0x00000000 +#define IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE 0x00000008 +#define IFX_SSC_SFCON_FIR_DISABLE_AFTER_PAUSE 0x00000000 +#define IFX_SSC_SFCON_DATA_LENGTH_MASK 0x0000FFF0 +#define IFX_SSC_SFCON_DATA_LENGTH_OFFSET 4 +#define IFX_SSC_SFCON_PAUSE_DATA_MASK 0x00030000 +#define IFX_SSC_SFCON_PAUSE_DATA_OFFSET 16 +#define IFX_SSC_SFCON_PAUSE_DATA_0 0x00000000 +#define IFX_SSC_SFCON_PAUSE_DATA_1 0x00010000 +#define IFX_SSC_SFCON_PAUSE_DATA_IDLE 0x00020000 +#define IFX_SSC_SFCON_PAUSE_CLOCK_MASK 0x000C0000 +#define IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET 18 +#define IFX_SSC_SFCON_PAUSE_CLOCK_0 0x00000000 +#define IFX_SSC_SFCON_PAUSE_CLOCK_1 0x00040000 +#define IFX_SSC_SFCON_PAUSE_CLOCK_IDLE 0x00080000 +#define IFX_SSC_SFCON_PAUSE_CLOCK_RUN 0x000C0000 +#define IFX_SSC_SFCON_STOP_AFTER_PAUSE 0x00100000 +#define IFX_SSC_SFCON_CONTINUE_AFTER_PAUSE 0x00000000 +#define IFX_SSC_SFCON_PAUSE_LENGTH_MASK 0xFFC00000 +#define IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET 22 +#define IFX_SSC_SFCON_DATA_LENGTH_MAX 4096 +#define IFX_SSC_SFCON_PAUSE_LENGTH_MAX 1024 + +#define IFX_SSC_SFCON_EXTRACT_DATA_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET) +#define IFX_SSC_SFCON_EXTRACT_PAUSE_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET) +#define IFX_SSC_SFCON_SET_DATA_LENGTH(value) ((value << IFX_SSC_SFCON_DATA_LENGTH_OFFSET) & IFX_SSC_SFCON_DATA_LENGTH_MASK) +#define IFX_SSC_SFCON_SET_PAUSE_LENGTH(value) ((value << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET) & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) + +/* SFSTAT register */ +#define IFX_SSC_SFSTAT_IN_DATA 0x00000001 +#define IFX_SSC_SFSTAT_IN_PAUSE 0x00000002 +#define IFX_SSC_SFSTAT_DATA_COUNT_MASK 0x0000FFF0 +#define IFX_SSC_SFSTAT_DATA_COUNT_OFFSET 4 +#define IFX_SSC_SFSTAT_PAUSE_COUNT_MASK 0xFFF00000 +#define IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET 20 + +#define IFX_SSC_SFSTAT_EXTRACT_DATA_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET) +#define IFX_SSC_SFSTAT_EXTRACT_PAUSE_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET) + +/* RXREQ register */ +#define IFX_SSC_RXREQ_RXCOUNT_MASK 0x0000FFFF +#define IFX_SSC_RXREQ_RXCOUNT_OFFSET 0 + +/* RXCNT register */ +#define IFX_SSC_RXCNT_TODO_MASK 0x0000FFFF +#define IFX_SSC_RXCNT_TODO_OFFSET 0 + +/* DMACON register */ +#define IFX_SSC_DMACON_RXON 0x00000001 +#define IFX_SSC_DMACON_RXOFF 0x00000000 +#define IFX_SSC_DMACON_TXON 0x00000002 +#define IFX_SSC_DMACON_TXOFF 0x00000000 +#define IFX_SSC_DMACON_DMAON 0x00000003 +#define IFX_SSC_DMACON_DMAOFF 0x00000000 +#define IFX_SSC_DMACON_CLASS_MASK 0x0000000C +#define IFX_SSC_DMACON_CLASS_OFFSET 2 + +/* register access macros */ +#define ifx_ssc_fstat_received_words(status) (status & 0x003F) +#define ifx_ssc_fstat_words_to_transmit(status) ((status & 0x3F00) >> 8) + +#define ifx_ssc_change_status(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_WHBSTATE)) +#define ifx_ssc_set_config(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_CON)) +#define ifx_ssc_get_config(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_CON)) +#define ifx_ssc_get_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_STATE)) +#define ifx_ssc_receive(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_RB)) +#define ifx_ssc_transmit(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_TB)) +#define ifx_ssc_fifo_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_FSTAT)) +#define ifx_ssc_set_baudrate(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_BR)) + +#define ifx_ssc_extract_rx_fifo_size(id) ((id & IFX_SSC_PERID_RXFS_MASK) >> IFX_SSC_PERID_RXFS_OFFSET) +#define ifx_ssc_extract_tx_fifo_size(id) ((id & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET) + +#endif diff --git a/target/linux/amazon/files/include/asm-mips/amazon/irq.h b/target/linux/amazon/files/include/asm-mips/amazon/irq.h new file mode 100644 index 0000000000..c575dd64b2 --- /dev/null +++ b/target/linux/amazon/files/include/asm-mips/amazon/irq.h @@ -0,0 +1,200 @@ +/* irq.h - AMAZON interrupts */ + +#ifndef __AMAZON_IRQ +#define __AMAZON_IRQ + +/************************************************************************ + * Interrupt information +*************************************************************************/ + +/* these vectors are to handle the interrupts from the internal AMAZON + interrupt controller. THe INT_NUM values are really just indices into + an array and are set up so that we can use the INT_NUM as a shift + to calculate a mask value. */ +#define INT_NUM_IRQ0 8 +#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) +#define INT_NUM_IM0_IRL1 (INT_NUM_IRQ0 + 1) +#define INT_NUM_IM0_IRL2 (INT_NUM_IRQ0 + 2) +#define INT_NUM_IM0_IRL3 (INT_NUM_IRQ0 + 3) +#define INT_NUM_IM0_IRL4 (INT_NUM_IRQ0 + 4) +#define INT_NUM_IM0_IRL5 (INT_NUM_IRQ0 + 5) +#define INT_NUM_IM0_IRL6 (INT_NUM_IRQ0 + 6) +#define INT_NUM_IM0_IRL7 (INT_NUM_IRQ0 + 7) +#define INT_NUM_IM0_IRL8 (INT_NUM_IRQ0 + 8) +#define INT_NUM_IM0_IRL9 (INT_NUM_IRQ0 + 9) +#define INT_NUM_IM0_IRL10 (INT_NUM_IRQ0 + 10) +#define INT_NUM_IM0_IRL11 (INT_NUM_IRQ0 + 11) +#define INT_NUM_IM0_IRL12 (INT_NUM_IRQ0 + 12) +#define INT_NUM_IM0_IRL13 (INT_NUM_IRQ0 + 13) +#define INT_NUM_IM0_IRL14 (INT_NUM_IRQ0 + 14) +#define INT_NUM_IM0_IRL15 (INT_NUM_IRQ0 + 15) +#define INT_NUM_IM0_IRL16 (INT_NUM_IRQ0 + 16) +#define INT_NUM_IM0_IRL17 (INT_NUM_IRQ0 + 17) +#define INT_NUM_IM0_IRL18 (INT_NUM_IRQ0 + 18) +#define INT_NUM_IM0_IRL19 (INT_NUM_IRQ0 + 19) +#define INT_NUM_IM0_IRL20 (INT_NUM_IRQ0 + 20) +#define INT_NUM_IM0_IRL21 (INT_NUM_IRQ0 + 21) +#define INT_NUM_IM0_IRL22 (INT_NUM_IRQ0 + 22) +#define INT_NUM_IM0_IRL23 (INT_NUM_IRQ0 + 23) +#define INT_NUM_IM0_IRL24 (INT_NUM_IRQ0 + 24) +#define INT_NUM_IM0_IRL25 (INT_NUM_IRQ0 + 25) +#define INT_NUM_IM0_IRL26 (INT_NUM_IRQ0 + 26) +#define INT_NUM_IM0_IRL27 (INT_NUM_IRQ0 + 27) +#define INT_NUM_IM0_IRL28 (INT_NUM_IRQ0 + 28) +#define INT_NUM_IM0_IRL29 (INT_NUM_IRQ0 + 29) +#define INT_NUM_IM0_IRL30 (INT_NUM_IRQ0 + 30) +#define INT_NUM_IM0_IRL31 (INT_NUM_IRQ0 + 31) + +#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32) +#define INT_NUM_IM1_IRL1 (INT_NUM_IM1_IRL0 + 1) +#define INT_NUM_IM1_IRL2 (INT_NUM_IM1_IRL0 + 2) +#define INT_NUM_IM1_IRL3 (INT_NUM_IM1_IRL0 + 3) +#define INT_NUM_IM1_IRL4 (INT_NUM_IM1_IRL0 + 4) +#define INT_NUM_IM1_IRL5 (INT_NUM_IM1_IRL0 + 5) +#define INT_NUM_IM1_IRL6 (INT_NUM_IM1_IRL0 + 6) +#define INT_NUM_IM1_IRL7 (INT_NUM_IM1_IRL0 + 7) +#define INT_NUM_IM1_IRL8 (INT_NUM_IM1_IRL0 + 8) +#define INT_NUM_IM1_IRL9 (INT_NUM_IM1_IRL0 + 9) +#define INT_NUM_IM1_IRL10 (INT_NUM_IM1_IRL0 + 10) +#define INT_NUM_IM1_IRL11 (INT_NUM_IM1_IRL0 + 11) +#define INT_NUM_IM1_IRL12 (INT_NUM_IM1_IRL0 + 12) +#define INT_NUM_IM1_IRL13 (INT_NUM_IM1_IRL0 + 13) +#define INT_NUM_IM1_IRL14 (INT_NUM_IM1_IRL0 + 14) +#define INT_NUM_IM1_IRL15 (INT_NUM_IM1_IRL0 + 15) +#define INT_NUM_IM1_IRL16 (INT_NUM_IM1_IRL0 + 16) +#define INT_NUM_IM1_IRL17 (INT_NUM_IM1_IRL0 + 17) +#define INT_NUM_IM1_IRL18 (INT_NUM_IM1_IRL0 + 18) +#define INT_NUM_IM1_IRL19 (INT_NUM_IM1_IRL0 + 19) +#define INT_NUM_IM1_IRL20 (INT_NUM_IM1_IRL0 + 20) +#define INT_NUM_IM1_IRL21 (INT_NUM_IM1_IRL0 + 21) +#define INT_NUM_IM1_IRL22 (INT_NUM_IM1_IRL0 + 22) +#define INT_NUM_IM1_IRL23 (INT_NUM_IM1_IRL0 + 23) +#define INT_NUM_IM1_IRL24 (INT_NUM_IM1_IRL0 + 24) +#define INT_NUM_IM1_IRL25 (INT_NUM_IM1_IRL0 + 25) +#define INT_NUM_IM1_IRL26 (INT_NUM_IM1_IRL0 + 26) +#define INT_NUM_IM1_IRL27 (INT_NUM_IM1_IRL0 + 27) +#define INT_NUM_IM1_IRL28 (INT_NUM_IM1_IRL0 + 28) +#define INT_NUM_IM1_IRL29 (INT_NUM_IM1_IRL0 + 29) +#define INT_NUM_IM1_IRL30 (INT_NUM_IM1_IRL0 + 30) +#define INT_NUM_IM1_IRL31 (INT_NUM_IM1_IRL0 + 31) + +#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64) +#define INT_NUM_IM2_IRL1 (INT_NUM_IM2_IRL0 + 1) +#define INT_NUM_IM2_IRL2 (INT_NUM_IM2_IRL0 + 2) +#define INT_NUM_IM2_IRL3 (INT_NUM_IM2_IRL0 + 3) +#define INT_NUM_IM2_IRL4 (INT_NUM_IM2_IRL0 + 4) +#define INT_NUM_IM2_IRL5 (INT_NUM_IM2_IRL0 + 5) +#define INT_NUM_IM2_IRL6 (INT_NUM_IM2_IRL0 + 6) +#define INT_NUM_IM2_IRL7 (INT_NUM_IM2_IRL0 + 7) +#define INT_NUM_IM2_IRL8 (INT_NUM_IM2_IRL0 + 8) +#define INT_NUM_IM2_IRL9 (INT_NUM_IM2_IRL0 + 9) +#define INT_NUM_IM2_IRL10 (INT_NUM_IM2_IRL0 + 10) +#define INT_NUM_IM2_IRL11 (INT_NUM_IM2_IRL0 + 11) +#define INT_NUM_IM2_IRL12 (INT_NUM_IM2_IRL0 + 12) +#define INT_NUM_IM2_IRL13 (INT_NUM_IM2_IRL0 + 13) +#define INT_NUM_IM2_IRL14 (INT_NUM_IM2_IRL0 + 14) +#define INT_NUM_IM2_IRL15 (INT_NUM_IM2_IRL0 + 15) +#define INT_NUM_IM2_IRL16 (INT_NUM_IM2_IRL0 + 16) +#define INT_NUM_IM2_IRL17 (INT_NUM_IM2_IRL0 + 17) +#define INT_NUM_IM2_IRL18 (INT_NUM_IM2_IRL0 + 18) +#define INT_NUM_IM2_IRL19 (INT_NUM_IM2_IRL0 + 19) +#define INT_NUM_IM2_IRL20 (INT_NUM_IM2_IRL0 + 20) +#define INT_NUM_IM2_IRL21 (INT_NUM_IM2_IRL0 + 21) +#define INT_NUM_IM2_IRL22 (INT_NUM_IM2_IRL0 + 22) +#define INT_NUM_IM2_IRL23 (INT_NUM_IM2_IRL0 + 23) +#define INT_NUM_IM2_IRL24 (INT_NUM_IM2_IRL0 + 24) +#define INT_NUM_IM2_IRL25 (INT_NUM_IM2_IRL0 + 25) +#define INT_NUM_IM2_IRL26 (INT_NUM_IM2_IRL0 + 26) +#define INT_NUM_IM2_IRL27 (INT_NUM_IM2_IRL0 + 27) +#define INT_NUM_IM2_IRL28 (INT_NUM_IM2_IRL0 + 28) +#define INT_NUM_IM2_IRL29 (INT_NUM_IM2_IRL0 + 29) +#define INT_NUM_IM2_IRL30 (INT_NUM_IM2_IRL0 + 30) +#define INT_NUM_IM2_IRL31 (INT_NUM_IM2_IRL0 + 31) + +#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96) +#define INT_NUM_IM3_IRL1 (INT_NUM_IM3_IRL0 + 1) +#define INT_NUM_IM3_IRL2 (INT_NUM_IM3_IRL0 + 2) +#define INT_NUM_IM3_IRL3 (INT_NUM_IM3_IRL0 + 3) +#define INT_NUM_IM3_IRL4 (INT_NUM_IM3_IRL0 + 4) +#define INT_NUM_IM3_IRL5 (INT_NUM_IM3_IRL0 + 5) +#define INT_NUM_IM3_IRL6 (INT_NUM_IM3_IRL0 + 6) +#define INT_NUM_IM3_IRL7 (INT_NUM_IM3_IRL0 + 7) +#define INT_NUM_IM3_IRL8 (INT_NUM_IM3_IRL0 + 8) +#define INT_NUM_IM3_IRL9 (INT_NUM_IM3_IRL0 + 9) +#define INT_NUM_IM3_IRL10 (INT_NUM_IM3_IRL0 + 10) +#define INT_NUM_IM3_IRL11 (INT_NUM_IM3_IRL0 + 11) +#define INT_NUM_IM3_IRL12 (INT_NUM_IM3_IRL0 + 12) +#define INT_NUM_IM3_IRL13 (INT_NUM_IM3_IRL0 + 13) +#define INT_NUM_IM3_IRL14 (INT_NUM_IM3_IRL0 + 14) +#define INT_NUM_IM3_IRL15 (INT_NUM_IM3_IRL0 + 15) +#define INT_NUM_IM3_IRL16 (INT_NUM_IM3_IRL0 + 16) +#define INT_NUM_IM3_IRL17 (INT_NUM_IM3_IRL0 + 17) +#define INT_NUM_IM3_IRL18 (INT_NUM_IM3_IRL0 + 18) +#define INT_NUM_IM3_IRL19 (INT_NUM_IM3_IRL0 + 19) +#define INT_NUM_IM3_IRL20 (INT_NUM_IM3_IRL0 + 20) +#define INT_NUM_IM3_IRL21 (INT_NUM_IM3_IRL0 + 21) +#define INT_NUM_IM3_IRL22 (INT_NUM_IM3_IRL0 + 22) +#define INT_NUM_IM3_IRL23 (INT_NUM_IM3_IRL0 + 23) +#define INT_NUM_IM3_IRL24 (INT_NUM_IM3_IRL0 + 24) +#define INT_NUM_IM3_IRL25 (INT_NUM_IM3_IRL0 + 25) +#define INT_NUM_IM3_IRL26 (INT_NUM_IM3_IRL0 + 26) +#define INT_NUM_IM3_IRL27 (INT_NUM_IM3_IRL0 + 27) +#define INT_NUM_IM3_IRL28 (INT_NUM_IM3_IRL0 + 28) +#define INT_NUM_IM3_IRL29 (INT_NUM_IM3_IRL0 + 29) +#define INT_NUM_IM3_IRL30 (INT_NUM_IM3_IRL0 + 30) +#define INT_NUM_IM3_IRL31 (INT_NUM_IM3_IRL0 + 31) + +#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128) +#define INT_NUM_IM4_IRL1 (INT_NUM_IM4_IRL0 + 1) +#define INT_NUM_IM4_IRL2 (INT_NUM_IM4_IRL0 + 2) +#define INT_NUM_IM4_IRL3 (INT_NUM_IM4_IRL0 + 3) +#define INT_NUM_IM4_IRL4 (INT_NUM_IM4_IRL0 + 4) +#define INT_NUM_IM4_IRL5 (INT_NUM_IM4_IRL0 + 5) +#define INT_NUM_IM4_IRL6 (INT_NUM_IM4_IRL0 + 6) +#define INT_NUM_IM4_IRL7 (INT_NUM_IM4_IRL0 + 7) +#define INT_NUM_IM4_IRL8 (INT_NUM_IM4_IRL0 + 8) +#define INT_NUM_IM4_IRL9 (INT_NUM_IM4_IRL0 + 9) +#define INT_NUM_IM4_IRL10 (INT_NUM_IM4_IRL0 + 10) +#define INT_NUM_IM4_IRL11 (INT_NUM_IM4_IRL0 + 11) +#define INT_NUM_IM4_IRL12 (INT_NUM_IM4_IRL0 + 12) +#define INT_NUM_IM4_IRL13 (INT_NUM_IM4_IRL0 + 13) +#define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14) +#define INT_NUM_IM4_IRL15 (INT_NUM_IM4_IRL0 + 15) +#define INT_NUM_IM4_IRL16 (INT_NUM_IM4_IRL0 + 16) +#define INT_NUM_IM4_IRL17 (INT_NUM_IM4_IRL0 + 17) +#define INT_NUM_IM4_IRL18 (INT_NUM_IM4_IRL0 + 18) +#define INT_NUM_IM4_IRL19 (INT_NUM_IM4_IRL0 + 19) +#define INT_NUM_IM4_IRL20 (INT_NUM_IM4_IRL0 + 20) +#define INT_NUM_IM4_IRL21 (INT_NUM_IM4_IRL0 + 21) +#define INT_NUM_IM4_IRL22 (INT_NUM_IM4_IRL0 + 22) +#define INT_NUM_IM4_IRL23 (INT_NUM_IM4_IRL0 + 23) +#define INT_NUM_IM4_IRL24 (INT_NUM_IM4_IRL0 + 24) +#define INT_NUM_IM4_IRL25 (INT_NUM_IM4_IRL0 + 25) +#define INT_NUM_IM4_IRL26 (INT_NUM_IM4_IRL0 + 26) +#define INT_NUM_IM4_IRL27 (INT_NUM_IM4_IRL0 + 27) +#define INT_NUM_IM4_IRL28 (INT_NUM_IM4_IRL0 + 28) +#define INT_NUM_IM4_IRL29 (INT_NUM_IM4_IRL0 + 29) +#define INT_NUM_IM4_IRL30 (INT_NUM_IM4_IRL0 + 30) +#define INT_NUM_IM4_IRL31 (INT_NUM_IM4_IRL0 + 31) + +/****** Interrupt Assigments ***********/ +#define AMAZON_DMA_INT INT_NUM_IM0_IRL0 +#define IFX_SSC_TIR INT_NUM_IM0_IRL29 +#define IFX_SSC_RIR INT_NUM_IM0_IRL30 +#define IFX_SSC_EIR INT_NUM_IM0_IRL31 + +#define AMAZON_MEI_INT INT_NUM_IM2_IRL8 + +#define AMAZONASC_TIR INT_NUM_IM4_IRL15/* TX interrupt */ +#define AMAZONASC_RIR INT_NUM_IM4_IRL16/* RX interrupt */ +#define AMAZONASC_EIR INT_NUM_IM4_IRL17/* ERROR interrupt */ + +#define AMAZON_TIMER6_INT INT_NUM_IM1_IRL23 + +#define AMAZON_SWIE_INT INT_NUM_IM3_IRL8 +#define AMAZON_CBM_INT INT_NUM_IM3_IRL9 +#define AMAZON_AAL5_INT INT_NUM_IM3_IRL10 +#define AMAZON_HTU_INT INT_NUM_IM3_IRL11 +#define AMAZON_QSB_INT INT_NUM_IM3_IRL12 +#define MIPS_CPU_TIMER_IRQ 7 +#endif /* __AMAZON_IRQ */ diff --git a/target/linux/amazon/files/include/asm-mips/amazon/model.h b/target/linux/amazon/files/include/asm-mips/amazon/model.h new file mode 100644 index 0000000000..4e43ab5f19 --- /dev/null +++ b/target/linux/amazon/files/include/asm-mips/amazon/model.h @@ -0,0 +1,29 @@ +#ifndef AMAZON_MODEL_H +#define AMAZON_MODEL_H +/****************************************************************************** + Copyright (c) 2002, Infineon Technologies. All rights reserved. + + No Warranty + Because the program is licensed free of charge, there is no warranty for + the program, to the extent permitted by applicable law. Except when + otherwise stated in writing the copyright holders and/or other parties + provide the program "as is" without warranty of any kind, either + expressed or implied, including, but not limited to, the implied + warranties of merchantability and fitness for a particular purpose. The + entire risk as to the quality and performance of the program is with + you. should the program prove defective, you assume the cost of all + necessary servicing, repair or correction. + + In no event unless required by applicable law or agreed to in writing + will any copyright holder, or any other party who may modify and/or + redistribute the program as permitted above, be liable to you for + damages, including any general, special, incidental or consequential + damages arising out of the use or inability to use the program + (including but not limited to loss of data or data being rendered + inaccurate or losses sustained by you or third parties or a failure of + the program to operate with any other programs), even if such holder or + other party has been advised of the possibility of such damages. +******************************************************************************/ +#define BOARD_SYSTEM_TYPE "AMAZON" +#define SYSTEM_MODEL_NAME "Amazon Gateway Package 3.2 Version" +#endif diff --git a/target/linux/amazon/files/include/asm-mips/amazon/port.h b/target/linux/amazon/files/include/asm-mips/amazon/port.h new file mode 100644 index 0000000000..21825794c5 --- /dev/null +++ b/target/linux/amazon/files/include/asm-mips/amazon/port.h @@ -0,0 +1,72 @@ +/* + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * port.h + * + * Global Amazon port driver header file + * + */ + +/* Modification history */ +/* 21Jun2004 btxu Generate from Inca_IP project */ + + +#ifndef PORT_H +#define PORT_H + +struct amazon_port_ioctl_parm { + int port; + int pin; + int value; +}; +#define AMAZON_PORT_IOC_MAGIC 0xbf +#define AMAZON_PORT_IOCOD _IOW( AMAZON_PORT_IOC_MAGIC,0,struct amazon_port_ioctl_parm) +#define AMAZON_PORT_IOCPUDSEL _IOW( AMAZON_PORT_IOC_MAGIC,1,struct amazon_port_ioctl_parm) +#define AMAZON_PORT_IOCPUDEN _IOW( AMAZON_PORT_IOC_MAGIC,2,struct amazon_port_ioctl_parm) +#define AMAZON_PORT_IOCSTOFF _IOW( AMAZON_PORT_IOC_MAGIC,3,struct amazon_port_ioctl_parm) +#define AMAZON_PORT_IOCDIR _IOW( AMAZON_PORT_IOC_MAGIC,4,struct amazon_port_ioctl_parm) +#define AMAZON_PORT_IOCOUTPUT _IOW( AMAZON_PORT_IOC_MAGIC,5,struct amazon_port_ioctl_parm) +#define AMAZON_PORT_IOCINPUT _IOWR(AMAZON_PORT_IOC_MAGIC,6,struct amazon_port_ioctl_parm) +#define AMAZON_PORT_IOCALTSEL0 _IOW( AMAZON_PORT_IOC_MAGIC,7,struct amazon_port_ioctl_parm) +#define AMAZON_PORT_IOCALTSEL1 _IOW( AMAZON_PORT_IOC_MAGIC,8,struct amazon_port_ioctl_parm) + +int amazon_port_reserve_pin(int port, int pin, int module_id); +int amazon_port_free_pin(int port, int pin, int module_id); +int amazon_port_set_open_drain(int port, int pin, int module_id); +int amazon_port_clear_open_drain(int port, int pin, int module_id); +int amazon_port_set_pudsel(int port, int pin, int module_id); +int amazon_port_clear_pudsel(int port, int pin, int module_id); +int amazon_port_set_puden(int port, int pin, int module_id); +int amazon_port_clear_puden(int port, int pin, int module_id); +int amazon_port_set_stoff(int port, int pin, int module_id); +int amazon_port_clear_stoff(int port, int pin, int module_id); +int amazon_port_set_dir_out(int port, int pin, int module_id); +int amazon_port_set_dir_in(int port, int pin, int module_id); +int amazon_port_set_output(int port, int pin, int module_id); +int amazon_port_clear_output(int port, int pin, int module_id); +int amazon_port_get_input(int port, int pin, int module_id); + +int amazon_port_set_altsel0(int port, int pin, int module_id); +int amazon_port_clear_altsel0(int port, int pin, int module_id); +int amazon_port_set_altsel1(int port, int pin, int module_id); +int amazon_port_clear_altsel1(int port, int pin, int module_id); + + +#endif /* PORT_H */ + + diff --git a/target/linux/amazon/files/include/asm-mips/amazon/serial.h b/target/linux/amazon/files/include/asm-mips/amazon/serial.h new file mode 100644 index 0000000000..3ff3efc28d --- /dev/null +++ b/target/linux/amazon/files/include/asm-mips/amazon/serial.h @@ -0,0 +1,146 @@ +/* incaAscSio.h - (AMAZON) ASC UART tty driver header */ + +#ifndef __AMAZON_ASC_H +#define __AMAZON_ASC_H + +/* channel operating modes */ +#define ASCOPT_CSIZE 0x00000003 +#define ASCOPT_CS7 0x00000001 +#define ASCOPT_CS8 0x00000002 +#define ASCOPT_PARENB 0x00000004 +#define ASCOPT_STOPB 0x00000008 +#define ASCOPT_PARODD 0x00000010 +#define ASCOPT_CREAD 0x00000020 + +#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8) + +/* ASC input select (0 or 1) */ +#define CONSOLE_TTY 0 + +/* use fractional divider for baudrate settings */ +#define AMAZONASC_USE_FDV + +#ifdef AMAZONASC_USE_FDV + #define AMAZONASC_FDV_LOW_BAUDRATE 71 +#ifdef CONFIG_USE_IKOS + #define AMAZONASC_FDV_HIGH_BAUDRATE 443 +#else + #define AMAZONASC_FDV_HIGH_BAUDRATE 498 +#endif //CONFIG_USE_IKOS +#endif /*AMAZONASC_USE_FDV*/ + + +#define AMAZONASC_TXFIFO_FL 1 +#define AMAZONASC_RXFIFO_FL 1 +#define AMAZONASC_TXFIFO_FULL 16 + +/* interrupt lines masks for the ASC device interrupts*/ +/* change these macroses if it's necessary */ +#define AMAZONASC_IRQ_LINE_ALL 0x000F0000 /* all IRQs */ + +#define AMAZONASC_IRQ_LINE_TIR 0x00010000 /* TIR - Tx */ +#define AMAZONASC_IRQ_LINE_RIR 0x00020000 /* RIR - Rx */ +#define AMAZONASC_IRQ_LINE_EIR 0x00040000 /* EIR - Err */ +#define AMAZONASC_IRQ_LINE_TBIR 0x00080000 /* TBIR - Tx Buf*/ + +/* CLC register's bits and bitfields */ +#define ASCCLC_DISR 0x00000001 +#define ASCCLC_DISS 0x00000002 +#define ASCCLC_RMCMASK 0x0000FF00 +#define ASCCLC_RMCOFFSET 8 + +/* CON register's bits and bitfields */ +#define ASCCON_MODEMASK 0x0007 + #define ASCCON_M_8SYNC 0x0 + #define ASCCON_M_8ASYNC 0x1 + #define ASCCON_M_8IRDAASYNC 0x2 + #define ASCCON_M_7ASYNCPAR 0x3 + #define ASCCON_M_9ASYNC 0x4 + #define ASCCON_M_8WAKEUPASYNC 0x5 + #define ASCCON_M_8ASYNCPAR 0x7 +#define ASCCON_STP 0x0008 +#define ASCCON_REN 0x0010 +#define ASCCON_PEN 0x0020 +#define ASCCON_FEN 0x0040 +#define ASCCON_OEN 0x0080 +#define ASCCON_PE 0x0100 +#define ASCCON_FE 0x0200 +#define ASCCON_OE 0x0400 +#define ASCCON_FDE 0x0800 +#define ASCCON_ODD 0x1000 +#define ASCCON_BRS 0x2000 +#define ASCCON_LB 0x4000 +#define ASCCON_R 0x8000 +#define ASCCON_ANY (ASCCON_PE|ASCCON_FE|ASCCON_OE) + +/* WHBCON register's bits and bitfields */ +#define ASCWHBCON_CLRREN 0x0010 +#define ASCWHBCON_SETREN 0x0020 +#define ASCWHBCON_CLRPE 0x0100 +#define ASCWHBCON_CLRFE 0x0200 +#define ASCWHBCON_CLROE 0x0400 +#define ASCWHBCON_SETPE 0x0800 +#define ASCWHBCON_SETFE 0x1000 +#define ASCWHBCON_SETOE 0x2000 + +/* ABCON register's bits and bitfields */ +#define ASCABCON_ABEN 0x0001 +#define ASCABCON_AUREN 0x0002 +#define ASCABCON_ABSTEN 0x0004 +#define ASCABCON_ABDETEN 0x0008 +#define ASCABCON_FCDETEN 0x0010 +#define ASCABCON_EMMASK 0x0300 + #define ASCABCON_EMOFF 8 + #define ASCABCON_EM_DISAB 0x0 + #define ASCABCON_EM_DURAB 0x1 + #define ASCABCON_EM_ALWAYS 0x2 +#define ASCABCON_TXINV 0x0400 +#define ASCABCON_RXINV 0x0800 + +/* FDV register mask, offset and bitfields*/ +#define ASCFDV_VALUE_MASK 0x000001FF + +/* WHBABCON register's bits and bitfields */ +#define ASCWHBABCON_SETABEN 0x0001 +#define ASCWHBABCON_CLRABEN 0x0002 + +/* ABSTAT register's bits and bitfields */ +#define ASCABSTAT_FCSDET 0x0001 +#define ASCABSTAT_FCCDET 0x0002 +#define ASCABSTAT_SCSDET 0x0004 +#define ASCABSTAT_SCCDET 0x0008 +#define ASCABSTAT_DETWAIT 0x0010 + +/* WHBABSTAT register's bits and bitfields */ +#define ASCWHBABSTAT_CLRFCSDET 0x0001 +#define ASCWHBABSTAT_SETFCSDET 0x0002 +#define ASCWHBABSTAT_CLRFCCDET 0x0004 +#define ASCWHBABSTAT_SETFCCDET 0x0008 +#define ASCWHBABSTAT_CLRSCSDET 0x0010 +#define ASCWHBABSTAT_SETSCSDET 0x0020 +#define ASCWHBABSTAT_SETSCCDET 0x0040 +#define ASCWHBABSTAT_CLRSCCDET 0x0080 +#define ASCWHBABSTAT_CLRDETWAIT 0x0100 +#define ASCWHBABSTAT_SETDETWAIT 0x0200 + +/* TXFCON register's bits and bitfields */ +#define ASCTXFCON_TXFEN 0x0001 +#define ASCTXFCON_TXFFLU 0x0002 +#define ASCTXFCON_TXTMEN 0x0004 +#define ASCTXFCON_TXFITLMASK 0x3F00 +#define ASCTXFCON_TXFITLOFF 8 + +/* RXFCON register's bits and bitfields */ +#define ASCRXFCON_RXFEN 0x0001 +#define ASCRXFCON_RXFFLU 0x0002 +#define ASCRXFCON_RXTMEN 0x0004 +#define ASCRXFCON_RXFITLMASK 0x3F00 +#define ASCRXFCON_RXFITLOFF 8 + +/* FSTAT register's bits and bitfields */ +#define ASCFSTAT_RXFFLMASK 0x003F +#define ASCFSTAT_TXFFLMASK 0x3F00 +#define ASCFSTAT_TXFFLOFF 8 + +#endif /* __AMAZON_ASC_H */ + diff --git a/target/linux/amazon/files/include/asm-mips/mach-amazon/irq.h b/target/linux/amazon/files/include/asm-mips/mach-amazon/irq.h new file mode 100644 index 0000000000..e72b7d5c11 --- /dev/null +++ b/target/linux/amazon/files/include/asm-mips/mach-amazon/irq.h @@ -0,0 +1,7 @@ +#ifndef __AMAZON_IRQ_H +#define __AMAZON_IRQ_H + +#define NR_IRQS 256 +#include_next <irq.h> + +#endif diff --git a/target/linux/amazon/files/include/asm-mips/mach-amazon/mangle-port.h b/target/linux/amazon/files/include/asm-mips/mach-amazon/mangle-port.h new file mode 100644 index 0000000000..9aefebbe63 --- /dev/null +++ b/target/linux/amazon/files/include/asm-mips/mach-amazon/mangle-port.h @@ -0,0 +1,52 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003, 2004 Ralf Baechle + */ +#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H +#define __ASM_MACH_GENERIC_MANGLE_PORT_H + +#define __swizzle_addr_b(port) (port) +#define __swizzle_addr_w(port) ((port) ^ 2) +#define __swizzle_addr_l(port) (port) +#define __swizzle_addr_q(port) (port) + +/* + * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware; + * less sane hardware forces software to fiddle with this... + * + * Regardless, if the host bus endianness mismatches that of PCI/ISA, then + * you can't have the numerical value of data and byte addresses within + * multibyte quantities both preserved at the same time. Hence two + * variations of functions: non-prefixed ones that preserve the value + * and prefixed ones that preserve byte addresses. The latters are + * typically used for moving raw data between a peripheral and memory (cf. + * string I/O functions), hence the "__mem_" prefix. + */ +#if defined(CONFIG_SWAP_IO_SPACE) + +# define ioswabb(a,x) (x) +# define __mem_ioswabb(a,x) (x) +# define ioswabw(a,x) le16_to_cpu(x) +# define __mem_ioswabw(a,x) (x) +# define ioswabl(a,x) le32_to_cpu(x) +# define __mem_ioswabl(a,x) (x) +# define ioswabq(a,x) le64_to_cpu(x) +# define __mem_ioswabq(a,x) (x) + +#else + +# define ioswabb(a,x) (x) +# define __mem_ioswabb(a,x) (x) +# define ioswabw(a,x) (x) +# define __mem_ioswabw(a,x) cpu_to_le16(x) +# define ioswabl(a,x) (x) +# define __mem_ioswabl(a,x) cpu_to_le32(x) +# define ioswabq(a,x) (x) +# define __mem_ioswabq(a,x) cpu_to_le32(x) + +#endif + +#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */ |