ath9k: clean up / fix some initval related code

SVN-Revision: 32656

1 files changed, 1169 insertions, 0 deletions

diff --git a/package/mac80211/patches/566-ath9k_fix_initval_array.patch b/package/mac80211/patches/566-ath9k_fix_initval_array.patch
new file mode 100644
index 0000000000..0a5eb8bb7c
--- /dev/null
+++ b/package/mac80211/patches/566-ath9k_fix_initval_array.patch
@@ -0,0 +1,1169 @@
+--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
++++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+@@ -26,101 +26,70 @@
+ static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
+ {
+ 	if (AR_SREV_9271(ah)) {
+-		INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
+-			       ARRAY_SIZE(ar9271Modes_9271), 5);
+-		INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
+-			       ARRAY_SIZE(ar9271Common_9271), 2);
+-		INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
+-			       ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 5);
++		INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271);
++		INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271);
++		INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg);
+ 		return;
+ 	}
+ 
+ 	if (ah->config.pcie_clock_req)
+ 		INIT_INI_ARRAY(&ah->iniPcieSerdes,
+-			   ar9280PciePhy_clkreq_off_L1_9280,
+-			   ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2);
++			   ar9280PciePhy_clkreq_off_L1_9280);
+ 	else
+ 		INIT_INI_ARRAY(&ah->iniPcieSerdes,
+-			   ar9280PciePhy_clkreq_always_on_L1_9280,
+-			   ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
++			   ar9280PciePhy_clkreq_always_on_L1_9280);
+ 
+ 	if (AR_SREV_9287_11_OR_LATER(ah)) {
+-		INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
+-				ARRAY_SIZE(ar9287Modes_9287_1_1), 5);
+-		INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
+-				ARRAY_SIZE(ar9287Common_9287_1_1), 2);
++		INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1);
++		INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1);
+ 	} else if (AR_SREV_9285_12_OR_LATER(ah)) {
+-		INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
+-			       ARRAY_SIZE(ar9285Modes_9285_1_2), 5);
+-		INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
+-			       ARRAY_SIZE(ar9285Common_9285_1_2), 2);
++		INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2);
++		INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2);
+ 	} else if (AR_SREV_9280_20_OR_LATER(ah)) {
+-		INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
+-			       ARRAY_SIZE(ar9280Modes_9280_2), 5);
+-		INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
+-			       ARRAY_SIZE(ar9280Common_9280_2), 2);
++		INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2);
++		INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2);
+ 
+ 		INIT_INI_ARRAY(&ah->iniModesFastClock,
+-			       ar9280Modes_fast_clock_9280_2,
+-			       ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
++			       ar9280Modes_fast_clock_9280_2);
+ 	} else if (AR_SREV_9160_10_OR_LATER(ah)) {
+-		INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
+-			       ARRAY_SIZE(ar5416Modes_9160), 5);
+-		INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
+-			       ARRAY_SIZE(ar5416Common_9160), 2);
++		INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160);
++		INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160);
+ 		if (AR_SREV_9160_11(ah)) {
+ 			INIT_INI_ARRAY(&ah->iniAddac,
+-				       ar5416Addac_9160_1_1,
+-				       ARRAY_SIZE(ar5416Addac_9160_1_1), 2);
++				       ar5416Addac_9160_1_1);
+ 		} else {
+-			INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
+-				       ARRAY_SIZE(ar5416Addac_9160), 2);
++			INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160);
+ 		}
+ 	} else if (AR_SREV_9100_OR_LATER(ah)) {
+-		INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
+-			       ARRAY_SIZE(ar5416Modes_9100), 5);
+-		INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
+-			       ARRAY_SIZE(ar5416Common_9100), 2);
+-		INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
+-			       ARRAY_SIZE(ar5416Bank6_9100), 3);
+-		INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
+-			       ARRAY_SIZE(ar5416Addac_9100), 2);
++		INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100);
++		INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100);
++		INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100);
++		INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100);
+ 	} else {
+-		INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
+-			       ARRAY_SIZE(ar5416Modes), 5);
+-		INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
+-			       ARRAY_SIZE(ar5416Common), 2);
+-		INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
+-			       ARRAY_SIZE(ar5416Bank6TPC), 3);
+-		INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
+-			       ARRAY_SIZE(ar5416Addac), 2);
++		INIT_INI_ARRAY(&ah->iniModes, ar5416Modes);
++		INIT_INI_ARRAY(&ah->iniCommon, ar5416Common);
++		INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC);
++		INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac);
+ 	}
+ 
+ 	if (!AR_SREV_9280_20_OR_LATER(ah)) {
+ 		/* Common for AR5416, AR913x, AR9160 */
+-		INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
+-			       ARRAY_SIZE(ar5416BB_RfGain), 3);
++		INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain);
+ 
+-		INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
+-			       ARRAY_SIZE(ar5416Bank0), 2);
+-		INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
+-			       ARRAY_SIZE(ar5416Bank1), 2);
+-		INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
+-			       ARRAY_SIZE(ar5416Bank2), 2);
+-		INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
+-			       ARRAY_SIZE(ar5416Bank3), 3);
+-		INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
+-			       ARRAY_SIZE(ar5416Bank7), 2);
++		INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0);
++		INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1);
++		INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2);
++		INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3);
++		INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7);
+ 
+ 		/* Common for AR5416, AR9160 */
+ 		if (!AR_SREV_9100(ah))
+-			INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
+-				       ARRAY_SIZE(ar5416Bank6), 3);
++			INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6);
+ 
+ 		/* Common for AR913x, AR9160 */
+ 		if (!AR_SREV_5416(ah))
+-			INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
+-				       ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
++			INIT_INI_ARRAY(&ah->iniBank6TPC,
++				      ar5416Bank6TPC_9100);
+ 	}
+ 
+ 	/* iniAddac needs to be modified for these chips */
+@@ -143,13 +112,9 @@ static void ar9002_hw_init_mode_regs(str
+ 	}
+ 	if (AR_SREV_9287_11_OR_LATER(ah)) {
+ 		INIT_INI_ARRAY(&ah->iniCckfirNormal,
+-		       ar9287Common_normal_cck_fir_coeff_9287_1_1,
+-		       ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_9287_1_1),
+-		       2);
++		       ar9287Common_normal_cck_fir_coeff_9287_1_1);
+ 		INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
+-		       ar9287Common_japan_2484_cck_fir_coeff_9287_1_1,
+-		       ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_9287_1_1),
+-		       2);
++		       ar9287Common_japan_2484_cck_fir_coeff_9287_1_1);
+ 	}
+ }
+ 
+@@ -163,20 +128,16 @@ static void ar9280_20_hw_init_rxgain_ini
+ 
+ 		if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
+ 			INIT_INI_ARRAY(&ah->iniModesRxGain,
+-			ar9280Modes_backoff_13db_rxgain_9280_2,
+-			ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 5);
++				       ar9280Modes_backoff_13db_rxgain_9280_2);
+ 		else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
+ 			INIT_INI_ARRAY(&ah->iniModesRxGain,
+-			ar9280Modes_backoff_23db_rxgain_9280_2,
+-			ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 5);
++				       ar9280Modes_backoff_23db_rxgain_9280_2);
+ 		else
+ 			INIT_INI_ARRAY(&ah->iniModesRxGain,
+-			ar9280Modes_original_rxgain_9280_2,
+-			ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 5);
++				       ar9280Modes_original_rxgain_9280_2);
+ 	} else {
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-			ar9280Modes_original_rxgain_9280_2,
+-			ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 5);
++			       ar9280Modes_original_rxgain_9280_2);
+ 	}
+ }
+ 
+@@ -186,16 +147,13 @@ static void ar9280_20_hw_init_txgain_ini
+ 	    AR5416_EEP_MINOR_VER_19) {
+ 		if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
+ 			INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9280Modes_high_power_tx_gain_9280_2,
+-			ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 5);
++				       ar9280Modes_high_power_tx_gain_9280_2);
+ 		else
+ 			INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9280Modes_original_tx_gain_9280_2,
+-			ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 5);
++				       ar9280Modes_original_tx_gain_9280_2);
+ 	} else {
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-		ar9280Modes_original_tx_gain_9280_2,
+-		ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 5);
++			       ar9280Modes_original_tx_gain_9280_2);
+ 	}
+ }
+ 
+@@ -203,12 +161,10 @@ static void ar9271_hw_init_txgain_ini(st
+ {
+ 	if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			       ar9271Modes_high_power_tx_gain_9271,
+-			       ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 5);
++			       ar9271Modes_high_power_tx_gain_9271);
+ 	else
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			       ar9271Modes_normal_power_tx_gain_9271,
+-			       ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 5);
++			       ar9271Modes_normal_power_tx_gain_9271);
+ }
+ 
+ static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
+@@ -217,8 +173,7 @@ static void ar9002_hw_init_mode_gain_reg
+ 
+ 	if (AR_SREV_9287_11_OR_LATER(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-		ar9287Modes_rx_gain_9287_1_1,
+-		ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 5);
++			       ar9287Modes_rx_gain_9287_1_1);
+ 	else if (AR_SREV_9280_20(ah))
+ 		ar9280_20_hw_init_rxgain_ini(ah);
+ 
+@@ -226,8 +181,7 @@ static void ar9002_hw_init_mode_gain_reg
+ 		ar9271_hw_init_txgain_ini(ah, txgain_type);
+ 	} else if (AR_SREV_9287_11_OR_LATER(ah)) {
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-		ar9287Modes_tx_gain_9287_1_1,
+-		ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 5);
++			       ar9287Modes_tx_gain_9287_1_1);
+ 	} else if (AR_SREV_9280_20(ah)) {
+ 		ar9280_20_hw_init_txgain_ini(ah, txgain_type);
+ 	} else if (AR_SREV_9285_12_OR_LATER(ah)) {
+@@ -235,26 +189,18 @@ static void ar9002_hw_init_mode_gain_reg
+ 		if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
+ 			if (AR_SREV_9285E_20(ah)) {
+ 				INIT_INI_ARRAY(&ah->iniModesTxGain,
+-				ar9285Modes_XE2_0_high_power,
+-				ARRAY_SIZE(
+-				  ar9285Modes_XE2_0_high_power), 5);
++					       ar9285Modes_XE2_0_high_power);
+ 			} else {
+ 				INIT_INI_ARRAY(&ah->iniModesTxGain,
+-				ar9285Modes_high_power_tx_gain_9285_1_2,
+-				ARRAY_SIZE(
+-				  ar9285Modes_high_power_tx_gain_9285_1_2), 5);
++					ar9285Modes_high_power_tx_gain_9285_1_2);
+ 			}
+ 		} else {
+ 			if (AR_SREV_9285E_20(ah)) {
+ 				INIT_INI_ARRAY(&ah->iniModesTxGain,
+-				ar9285Modes_XE2_0_normal_power,
+-				ARRAY_SIZE(
+-				  ar9285Modes_XE2_0_normal_power), 5);
++					       ar9285Modes_XE2_0_normal_power);
+ 			} else {
+ 				INIT_INI_ARRAY(&ah->iniModesTxGain,
+-				ar9285Modes_original_tx_gain_9285_1_2,
+-				ARRAY_SIZE(
+-				  ar9285Modes_original_tx_gain_9285_1_2), 5);
++					ar9285Modes_original_tx_gain_9285_1_2);
+ 			}
+ 		}
+ 	}
+--- a/drivers/net/wireless/ath/ath9k/calib.h
++++ b/drivers/net/wireless/ath/ath9k/calib.h
+@@ -30,10 +30,10 @@ struct ar5416IniArray {
+ 	u32 ia_columns;
+ };
+ 
+-#define INIT_INI_ARRAY(iniarray, array, rows, columns) do {	\
++#define INIT_INI_ARRAY(iniarray, array) do {	\
+ 		(iniarray)->ia_array = (u32 *)(array);		\
+-		(iniarray)->ia_rows = (rows);			\
+-		(iniarray)->ia_columns = (columns);		\
++		(iniarray)->ia_rows = ARRAY_SIZE(array);	\
++		(iniarray)->ia_columns = ARRAY_SIZE(array[0]);	\
+ 	} while (0)
+ 
+ #define INI_RA(iniarray, row, column) \
+--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+@@ -44,462 +44,310 @@ static void ar9003_hw_init_mode_regs(str
+ 		ar9462_2p0_baseband_core_txfir_coeff_japan_2484
+ 	if (AR_SREV_9330_11(ah)) {
+ 		/* mac */
+-		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ 		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+-				ar9331_1p1_mac_core,
+-				ARRAY_SIZE(ar9331_1p1_mac_core), 2);
++				ar9331_1p1_mac_core);
+ 		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+-				ar9331_1p1_mac_postamble,
+-				ARRAY_SIZE(ar9331_1p1_mac_postamble), 5);
++				ar9331_1p1_mac_postamble);
+ 
+ 		/* bb */
+-		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+ 		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+-				ar9331_1p1_baseband_core,
+-				ARRAY_SIZE(ar9331_1p1_baseband_core), 2);
++				ar9331_1p1_baseband_core);
+ 		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+-				ar9331_1p1_baseband_postamble,
+-				ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5);
++				ar9331_1p1_baseband_postamble);
+ 
+ 		/* radio */
+-		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ 		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+-				ar9331_1p1_radio_core,
+-				ARRAY_SIZE(ar9331_1p1_radio_core), 2);
+-		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
++				ar9331_1p1_radio_core);
+ 
+ 		/* soc */
+ 		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+-				ar9331_1p1_soc_preamble,
+-				ARRAY_SIZE(ar9331_1p1_soc_preamble), 2);
+-		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
++				ar9331_1p1_soc_preamble);
+ 		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+-				ar9331_1p1_soc_postamble,
+-				ARRAY_SIZE(ar9331_1p1_soc_postamble), 2);
++				ar9331_1p1_soc_postamble);
+ 
+ 		/* rx/tx gain */
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-				ar9331_common_rx_gain_1p1,
+-				ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2);
++				ar9331_common_rx_gain_1p1);
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9331_modes_lowest_ob_db_tx_gain_1p1,
+-			ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
+-			5);
++				ar9331_modes_lowest_ob_db_tx_gain_1p1);
+ 
+ 		/* additional clock settings */
+ 		if (ah->is_clk_25mhz)
+ 			INIT_INI_ARRAY(&ah->iniAdditional,
+-					ar9331_1p1_xtal_25M,
+-					ARRAY_SIZE(ar9331_1p1_xtal_25M), 2);
++					ar9331_1p1_xtal_25M);
+ 		else
+ 			INIT_INI_ARRAY(&ah->iniAdditional,
+-					ar9331_1p1_xtal_40M,
+-					ARRAY_SIZE(ar9331_1p1_xtal_40M), 2);
++					ar9331_1p1_xtal_40M);
+ 	} else if (AR_SREV_9330_12(ah)) {
+ 		/* mac */
+-		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ 		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+-				ar9331_1p2_mac_core,
+-				ARRAY_SIZE(ar9331_1p2_mac_core), 2);
++				ar9331_1p2_mac_core);
+ 		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+-				ar9331_1p2_mac_postamble,
+-				ARRAY_SIZE(ar9331_1p2_mac_postamble), 5);
++				ar9331_1p2_mac_postamble);
+ 
+ 		/* bb */
+-		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+ 		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+-				ar9331_1p2_baseband_core,
+-				ARRAY_SIZE(ar9331_1p2_baseband_core), 2);
++				ar9331_1p2_baseband_core);
+ 		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+-				ar9331_1p2_baseband_postamble,
+-				ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5);
++				ar9331_1p2_baseband_postamble);
+ 
+ 		/* radio */
+-		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ 		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+-				ar9331_1p2_radio_core,
+-				ARRAY_SIZE(ar9331_1p2_radio_core), 2);
+-		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
++				ar9331_1p2_radio_core);
+ 
+ 		/* soc */
+ 		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+-				ar9331_1p2_soc_preamble,
+-				ARRAY_SIZE(ar9331_1p2_soc_preamble), 2);
+-		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
++				ar9331_1p2_soc_preamble);
+ 		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+-				ar9331_1p2_soc_postamble,
+-				ARRAY_SIZE(ar9331_1p2_soc_postamble), 2);
++				ar9331_1p2_soc_postamble);
+ 
+ 		/* rx/tx gain */
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-				ar9331_common_rx_gain_1p2,
+-				ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2);
++				ar9331_common_rx_gain_1p2);
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9331_modes_lowest_ob_db_tx_gain_1p2,
+-			ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
+-			5);
++				ar9331_modes_lowest_ob_db_tx_gain_1p2);
+ 
+ 		/* additional clock settings */
+ 		if (ah->is_clk_25mhz)
+ 			INIT_INI_ARRAY(&ah->iniAdditional,
+-					ar9331_1p2_xtal_25M,
+-					ARRAY_SIZE(ar9331_1p2_xtal_25M), 2);
++					ar9331_1p2_xtal_25M);
+ 		else
+ 			INIT_INI_ARRAY(&ah->iniAdditional,
+-					ar9331_1p2_xtal_40M,
+-					ARRAY_SIZE(ar9331_1p2_xtal_40M), 2);
++					ar9331_1p2_xtal_40M);
+ 	} else if (AR_SREV_9340(ah)) {
+ 		/* mac */
+-		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ 		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+-				ar9340_1p0_mac_core,
+-				ARRAY_SIZE(ar9340_1p0_mac_core), 2);
++				ar9340_1p0_mac_core);
+ 		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+-				ar9340_1p0_mac_postamble,
+-				ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
++				ar9340_1p0_mac_postamble);
+ 
+ 		/* bb */
+-		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+ 		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+-				ar9340_1p0_baseband_core,
+-				ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
++				ar9340_1p0_baseband_core);
+ 		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+-				ar9340_1p0_baseband_postamble,
+-				ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
++				ar9340_1p0_baseband_postamble);
+ 
+ 		/* radio */
+-		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ 		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+-				ar9340_1p0_radio_core,
+-				ARRAY_SIZE(ar9340_1p0_radio_core), 2);
++				ar9340_1p0_radio_core);
+ 		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+-				ar9340_1p0_radio_postamble,
+-				ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
++				ar9340_1p0_radio_postamble);
+ 
+ 		/* soc */
+ 		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+-				ar9340_1p0_soc_preamble,
+-				ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
+-		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
++				ar9340_1p0_soc_preamble);
+ 		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+-				ar9340_1p0_soc_postamble,
+-				ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
++				ar9340_1p0_soc_postamble);
+ 
+ 		/* rx/tx gain */
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-				ar9340Common_wo_xlna_rx_gain_table_1p0,
+-				ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
+-				5);
+-		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-				ar9340Modes_high_ob_db_tx_gain_table_1p0,
+-				ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
+-				5);
++				ar9340Common_wo_xlna_rx_gain_table_1p0);
++		INIT_INI_ARRAY(&ah->iniModesTxGain,
++				ar9340Modes_high_ob_db_tx_gain_table_1p0);
+ 
+ 		INIT_INI_ARRAY(&ah->iniModesFastClock,
+-				ar9340Modes_fast_clock_1p0,
+-				ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
+-				3);
++				ar9340Modes_fast_clock_1p0);
+ 
+ 		if (!ah->is_clk_25mhz)
+ 			INIT_INI_ARRAY(&ah->iniAdditional,
+-				       ar9340_1p0_radio_core_40M,
+-				       ARRAY_SIZE(ar9340_1p0_radio_core_40M),
+-				       2);
++				       ar9340_1p0_radio_core_40M);
+ 	} else if (AR_SREV_9485_11(ah)) {
+ 		/* mac */
+-		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ 		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+-				ar9485_1_1_mac_core,
+-				ARRAY_SIZE(ar9485_1_1_mac_core), 2);
++				ar9485_1_1_mac_core);
+ 		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+-				ar9485_1_1_mac_postamble,
+-				ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);
++				ar9485_1_1_mac_postamble);
+ 
+ 		/* bb */
+-		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1,
+-				ARRAY_SIZE(ar9485_1_1), 2);
++		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1);
+ 		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+-				ar9485_1_1_baseband_core,
+-				ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
++				ar9485_1_1_baseband_core);
+ 		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+-				ar9485_1_1_baseband_postamble,
+-				ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);
++				ar9485_1_1_baseband_postamble);
+ 
+ 		/* radio */
+-		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ 		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+-				ar9485_1_1_radio_core,
+-				ARRAY_SIZE(ar9485_1_1_radio_core), 2);
++				ar9485_1_1_radio_core);
+ 		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+-				ar9485_1_1_radio_postamble,
+-				ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);
++				ar9485_1_1_radio_postamble);
+ 
+ 		/* soc */
+ 		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+-				ar9485_1_1_soc_preamble,
+-				ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
+-		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
+-		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
++				ar9485_1_1_soc_preamble);
+ 
+ 		/* rx/tx gain */
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-				ar9485Common_wo_xlna_rx_gain_1_1,
+-				ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
++				ar9485Common_wo_xlna_rx_gain_1_1);
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-				ar9485_modes_lowest_ob_db_tx_gain_1_1,
+-				ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
+-				5);
++				ar9485_modes_lowest_ob_db_tx_gain_1_1);
+ 
+ 		/* Load PCIE SERDES settings from INI */
+ 
+ 		/* Awake Setting */
+ 
+ 		INIT_INI_ARRAY(&ah->iniPcieSerdes,
+-				ar9485_1_1_pcie_phy_clkreq_disable_L1,
+-				ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
+-				2);
++				ar9485_1_1_pcie_phy_clkreq_disable_L1);
+ 
+ 		/* Sleep Setting */
+ 
+ 		INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
+-				ar9485_1_1_pcie_phy_clkreq_disable_L1,
+-				ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
+-				2);
++				ar9485_1_1_pcie_phy_clkreq_disable_L1);
+ 	} else if (AR_SREV_9462_20(ah)) {
+ 
+-		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+-		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core,
+-				ARRAY_SIZE(ar9462_2p0_mac_core), 2);
++		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
+ 		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+-				ar9462_2p0_mac_postamble,
+-				ARRAY_SIZE(ar9462_2p0_mac_postamble), 5);
++				ar9462_2p0_mac_postamble);
+ 
+-		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+ 		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+-				ar9462_2p0_baseband_core,
+-				ARRAY_SIZE(ar9462_2p0_baseband_core), 2);
++				ar9462_2p0_baseband_core);
+ 		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+-				ar9462_2p0_baseband_postamble,
+-				ARRAY_SIZE(ar9462_2p0_baseband_postamble), 5);
++				ar9462_2p0_baseband_postamble);
+ 
+-		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ 		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+-				ar9462_2p0_radio_core,
+-				ARRAY_SIZE(ar9462_2p0_radio_core), 2);
++				ar9462_2p0_radio_core);
+ 		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+-				ar9462_2p0_radio_postamble,
+-				ARRAY_SIZE(ar9462_2p0_radio_postamble), 5);
++				ar9462_2p0_radio_postamble);
+ 		INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
+-				ar9462_2p0_radio_postamble_sys2ant,
+-				ARRAY_SIZE(ar9462_2p0_radio_postamble_sys2ant),
+-				5);
++				ar9462_2p0_radio_postamble_sys2ant);
+ 
+ 		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+-				ar9462_2p0_soc_preamble,
+-				ARRAY_SIZE(ar9462_2p0_soc_preamble), 2);
+-		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
++				ar9462_2p0_soc_preamble);
+ 		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+-				ar9462_2p0_soc_postamble,
+-				ARRAY_SIZE(ar9462_2p0_soc_postamble), 5);
++				ar9462_2p0_soc_postamble);
+ 
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-				ar9462_common_rx_gain_table_2p0,
+-				ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 2);
++				ar9462_common_rx_gain_table_2p0);
+ 
+ 		/* Awake -> Sleep Setting */
+ 		INIT_INI_ARRAY(&ah->iniPcieSerdes,
+-				PCIE_PLL_ON_CREQ_DIS_L1_2P0,
+-				ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
+-				2);
++				PCIE_PLL_ON_CREQ_DIS_L1_2P0);
+ 		/* Sleep -> Awake Setting */
+ 		INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
+-				PCIE_PLL_ON_CREQ_DIS_L1_2P0,
+-				ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
+-				2);
++				PCIE_PLL_ON_CREQ_DIS_L1_2P0);
+ 
+ 		/* Fast clock modal settings */
+ 		INIT_INI_ARRAY(&ah->iniModesFastClock,
+-				ar9462_modes_fast_clock_2p0,
+-				ARRAY_SIZE(ar9462_modes_fast_clock_2p0), 3);
++				ar9462_modes_fast_clock_2p0);
+ 
+ 		INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
+-				AR9462_BB_CTX_COEFJ(2p0),
+-				ARRAY_SIZE(AR9462_BB_CTX_COEFJ(2p0)), 2);
++				AR9462_BB_CTX_COEFJ(2p0));
+ 
+-		INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,
+-				ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
++		INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ);
+ 	} else if (AR_SREV_9550(ah)) {
+ 		/* mac */
+-		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ 		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+-				ar955x_1p0_mac_core,
+-				ARRAY_SIZE(ar955x_1p0_mac_core), 2);
++				ar955x_1p0_mac_core);
+ 		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+-				ar955x_1p0_mac_postamble,
+-				ARRAY_SIZE(ar955x_1p0_mac_postamble), 5);
++				ar955x_1p0_mac_postamble);
+ 
+ 		/* bb */
+-		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+ 		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+-				ar955x_1p0_baseband_core,
+-				ARRAY_SIZE(ar955x_1p0_baseband_core), 2);
++				ar955x_1p0_baseband_core);
+ 		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+-				ar955x_1p0_baseband_postamble,
+-				ARRAY_SIZE(ar955x_1p0_baseband_postamble), 5);
++				ar955x_1p0_baseband_postamble);
+ 
+ 		/* radio */
+-		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ 		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+-				ar955x_1p0_radio_core,
+-				ARRAY_SIZE(ar955x_1p0_radio_core), 2);
++				ar955x_1p0_radio_core);
+ 		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+-				ar955x_1p0_radio_postamble,
+-				ARRAY_SIZE(ar955x_1p0_radio_postamble), 5);
++				ar955x_1p0_radio_postamble);
+ 
+ 		/* soc */
+ 		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+-				ar955x_1p0_soc_preamble,
+-				ARRAY_SIZE(ar955x_1p0_soc_preamble), 2);
+-		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
++				ar955x_1p0_soc_preamble);
+ 		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+-				ar955x_1p0_soc_postamble,
+-				ARRAY_SIZE(ar955x_1p0_soc_postamble), 5);
++				ar955x_1p0_soc_postamble);
+ 
+ 		/* rx/tx gain */
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-			ar955x_1p0_common_wo_xlna_rx_gain_table,
+-			ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
+-			2);
++			ar955x_1p0_common_wo_xlna_rx_gain_table);
+ 		INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
+-			ar955x_1p0_common_wo_xlna_rx_gain_bounds,
+-			ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
+-			5);
+-		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-				ar955x_1p0_modes_xpa_tx_gain_table,
+-				ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
+-				9);
++			ar955x_1p0_common_wo_xlna_rx_gain_bounds);
++		INIT_INI_ARRAY(&ah->iniModesTxGain,
++				ar955x_1p0_modes_xpa_tx_gain_table);
+ 
+ 		/* Fast clock modal settings */
+ 		INIT_INI_ARRAY(&ah->iniModesFastClock,
+-				ar955x_1p0_modes_fast_clock,
+-				ARRAY_SIZE(ar955x_1p0_modes_fast_clock), 3);
++				ar955x_1p0_modes_fast_clock);
+ 	} else if (AR_SREV_9580(ah)) {
+ 		/* mac */
+-		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ 		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+-				ar9580_1p0_mac_core,
+-				ARRAY_SIZE(ar9580_1p0_mac_core), 2);
++				ar9580_1p0_mac_core);
+ 		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+-				ar9580_1p0_mac_postamble,
+-				ARRAY_SIZE(ar9580_1p0_mac_postamble), 5);
++				ar9580_1p0_mac_postamble);
+ 
+ 		/* bb */
+-		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+ 		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+-				ar9580_1p0_baseband_core,
+-				ARRAY_SIZE(ar9580_1p0_baseband_core), 2);
++				ar9580_1p0_baseband_core);
+ 		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+-				ar9580_1p0_baseband_postamble,
+-				ARRAY_SIZE(ar9580_1p0_baseband_postamble), 5);
++				ar9580_1p0_baseband_postamble);
+ 
+ 		/* radio */
+-		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ 		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+-				ar9580_1p0_radio_core,
+-				ARRAY_SIZE(ar9580_1p0_radio_core), 2);
++				ar9580_1p0_radio_core);
+ 		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+-				ar9580_1p0_radio_postamble,
+-				ARRAY_SIZE(ar9580_1p0_radio_postamble), 5);
++				ar9580_1p0_radio_postamble);
+ 
+ 		/* soc */
+ 		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+-				ar9580_1p0_soc_preamble,
+-				ARRAY_SIZE(ar9580_1p0_soc_preamble), 2);
+-		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
++				ar9580_1p0_soc_preamble);
+ 		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+-				ar9580_1p0_soc_postamble,
+-				ARRAY_SIZE(ar9580_1p0_soc_postamble), 5);
++				ar9580_1p0_soc_postamble);
+ 
+ 		/* rx/tx gain */
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-				ar9580_1p0_rx_gain_table,
+-				ARRAY_SIZE(ar9580_1p0_rx_gain_table), 2);
++				ar9580_1p0_rx_gain_table);
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-				ar9580_1p0_low_ob_db_tx_gain_table,
+-				ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
+-				5);
++				ar9580_1p0_low_ob_db_tx_gain_table);
+ 
+ 		INIT_INI_ARRAY(&ah->iniModesFastClock,
+-				ar9580_1p0_modes_fast_clock,
+-				ARRAY_SIZE(ar9580_1p0_modes_fast_clock),
+-				3);
++				ar9580_1p0_modes_fast_clock);
+ 	} else {
+ 		/* mac */
+-		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ 		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+-				ar9300_2p2_mac_core,
+-				ARRAY_SIZE(ar9300_2p2_mac_core), 2);
++				ar9300_2p2_mac_core);
+ 		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+-				ar9300_2p2_mac_postamble,
+-				ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
++				ar9300_2p2_mac_postamble);
+ 
+ 		/* bb */
+-		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+ 		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+-				ar9300_2p2_baseband_core,
+-				ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
++				ar9300_2p2_baseband_core);
+ 		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+-				ar9300_2p2_baseband_postamble,
+-				ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
++				ar9300_2p2_baseband_postamble);
+ 
+ 		/* radio */
+-		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ 		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+-				ar9300_2p2_radio_core,
+-				ARRAY_SIZE(ar9300_2p2_radio_core), 2);
++				ar9300_2p2_radio_core);
+ 		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+-				ar9300_2p2_radio_postamble,
+-				ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
++				ar9300_2p2_radio_postamble);
+ 
+ 		/* soc */
+ 		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+-				ar9300_2p2_soc_preamble,
+-				ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
+-		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
++				ar9300_2p2_soc_preamble);
+ 		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+-				ar9300_2p2_soc_postamble,
+-				ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
++				ar9300_2p2_soc_postamble);
+ 
+ 		/* rx/tx gain */
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-				ar9300Common_rx_gain_table_2p2,
+-				ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
++				ar9300Common_rx_gain_table_2p2);
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-				ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
+-				ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
+-				5);
++				ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
+ 
+ 		/* Load PCIE SERDES settings from INI */
+ 
+ 		/* Awake Setting */
+ 
+ 		INIT_INI_ARRAY(&ah->iniPcieSerdes,
+-				ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
+-				ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
+-				2);
++				ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
+ 
+ 		/* Sleep Setting */
+ 
+ 		INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
+-				ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
+-				ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
+-				2);
++				ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
+ 
+ 		/* Fast clock modal settings */
+ 		INIT_INI_ARRAY(&ah->iniModesFastClock,
+-				ar9300Modes_fast_clock_2p2,
+-				ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
+-				3);
++				ar9300Modes_fast_clock_2p2);
+ 	}
+ }
+ 
+@@ -507,170 +355,110 @@ static void ar9003_tx_gain_table_mode0(s
+ {
+ 	if (AR_SREV_9330_12(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9331_modes_lowest_ob_db_tx_gain_1p2,
+-			ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
+-			5);
++			ar9331_modes_lowest_ob_db_tx_gain_1p2);
+ 	else if (AR_SREV_9330_11(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9331_modes_lowest_ob_db_tx_gain_1p1,
+-			ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
+-			5);
++			ar9331_modes_lowest_ob_db_tx_gain_1p1);
+ 	else if (AR_SREV_9340(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
+-			ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
+-			5);
++			ar9340Modes_lowest_ob_db_tx_gain_table_1p0);
+ 	else if (AR_SREV_9485_11(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9485_modes_lowest_ob_db_tx_gain_1_1,
+-			ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
+-			5);
++			ar9485_modes_lowest_ob_db_tx_gain_1_1);
+ 	else if (AR_SREV_9550(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar955x_1p0_modes_xpa_tx_gain_table,
+-			ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
+-			9);
++			ar955x_1p0_modes_xpa_tx_gain_table);
+ 	else if (AR_SREV_9580(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9580_1p0_lowest_ob_db_tx_gain_table,
+-			ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),
+-			5);
++			ar9580_1p0_lowest_ob_db_tx_gain_table);
+ 	else if (AR_SREV_9462_20(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9462_modes_low_ob_db_tx_gain_table_2p0,
+-			ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_2p0),
+-			5);
++			ar9462_modes_low_ob_db_tx_gain_table_2p0);
+ 	else
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
+-			ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
+-			5);
++			ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
+ }
+ 
+ static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
+ {
+ 	if (AR_SREV_9330_12(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9331_modes_high_ob_db_tx_gain_1p2,
+-			ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2),
+-			5);
++			ar9331_modes_high_ob_db_tx_gain_1p2);
+ 	else if (AR_SREV_9330_11(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9331_modes_high_ob_db_tx_gain_1p1,
+-			ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1),
+-			5);
++			ar9331_modes_high_ob_db_tx_gain_1p1);
+ 	else if (AR_SREV_9340(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9340Modes_high_ob_db_tx_gain_table_1p0,
+-			ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
+-			5);
++			ar9340Modes_high_ob_db_tx_gain_table_1p0);
+ 	else if (AR_SREV_9485_11(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9485Modes_high_ob_db_tx_gain_1_1,
+-			ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
+-			5);
++			ar9485Modes_high_ob_db_tx_gain_1_1);
+ 	else if (AR_SREV_9580(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9580_1p0_high_ob_db_tx_gain_table,
+-			ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
+-			5);
++			ar9580_1p0_high_ob_db_tx_gain_table);
+ 	else if (AR_SREV_9550(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar955x_1p0_modes_no_xpa_tx_gain_table,
+-			ARRAY_SIZE(ar955x_1p0_modes_no_xpa_tx_gain_table),
+-			9);
++			ar955x_1p0_modes_no_xpa_tx_gain_table);
+ 	else if (AR_SREV_9462_20(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9462_modes_high_ob_db_tx_gain_table_2p0,
+-			ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_2p0),
+-			5);
++			ar9462_modes_high_ob_db_tx_gain_table_2p0);
+ 	else
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9300Modes_high_ob_db_tx_gain_table_2p2,
+-			ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
+-			5);
++			ar9300Modes_high_ob_db_tx_gain_table_2p2);
+ }
+ 
+ static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
+ {
+ 	if (AR_SREV_9330_12(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9331_modes_low_ob_db_tx_gain_1p2,
+-			ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2),
+-			5);
++			ar9331_modes_low_ob_db_tx_gain_1p2);
+ 	else if (AR_SREV_9330_11(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9331_modes_low_ob_db_tx_gain_1p1,
+-			ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1),
+-			5);
++			ar9331_modes_low_ob_db_tx_gain_1p1);
+ 	else if (AR_SREV_9340(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9340Modes_low_ob_db_tx_gain_table_1p0,
+-			ARRAY_SIZE(ar9340Modes_low_ob_db_tx_gain_table_1p0),
+-			5);
++			ar9340Modes_low_ob_db_tx_gain_table_1p0);
+ 	else if (AR_SREV_9485_11(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9485Modes_low_ob_db_tx_gain_1_1,
+-			ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
+-			5);
++			ar9485Modes_low_ob_db_tx_gain_1_1);
+ 	else if (AR_SREV_9580(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9580_1p0_low_ob_db_tx_gain_table,
+-			ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
+-			5);
++			ar9580_1p0_low_ob_db_tx_gain_table);
+ 	else
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9300Modes_low_ob_db_tx_gain_table_2p2,
+-			ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
+-			5);
++			ar9300Modes_low_ob_db_tx_gain_table_2p2);
+ }
+ 
+ static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
+ {
+ 	if (AR_SREV_9330_12(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9331_modes_high_power_tx_gain_1p2,
+-			ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2),
+-			5);
++			ar9331_modes_high_power_tx_gain_1p2);
+ 	else if (AR_SREV_9330_11(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9331_modes_high_power_tx_gain_1p1,
+-			ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1),
+-			5);
++			ar9331_modes_high_power_tx_gain_1p1);
+ 	else if (AR_SREV_9340(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9340Modes_high_power_tx_gain_table_1p0,
+-			ARRAY_SIZE(ar9340Modes_high_power_tx_gain_table_1p0),
+-			5);
++			ar9340Modes_high_power_tx_gain_table_1p0);
+ 	else if (AR_SREV_9485_11(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9485Modes_high_power_tx_gain_1_1,
+-			ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
+-			5);
++			ar9485Modes_high_power_tx_gain_1_1);
+ 	else if (AR_SREV_9580(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9580_1p0_high_power_tx_gain_table,
+-			ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table),
+-			5);
++			ar9580_1p0_high_power_tx_gain_table);
+ 	else
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9300Modes_high_power_tx_gain_table_2p2,
+-			ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
+-			5);
++			ar9300Modes_high_power_tx_gain_table_2p2);
+ }
+ 
+ static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
+ {
+ 	if (AR_SREV_9340(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9340Modes_mixed_ob_db_tx_gain_table_1p0,
+-			ARRAY_SIZE(ar9340Modes_mixed_ob_db_tx_gain_table_1p0),
+-			5);
++			ar9340Modes_mixed_ob_db_tx_gain_table_1p0);
+ 	else if (AR_SREV_9580(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesTxGain,
+-			ar9580_1p0_mixed_ob_db_tx_gain_table,
+-			ARRAY_SIZE(ar9580_1p0_mixed_ob_db_tx_gain_table),
+-			5);
++			ar9580_1p0_mixed_ob_db_tx_gain_table);
+ }
+ 
+ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
+@@ -699,104 +487,67 @@ static void ar9003_rx_gain_table_mode0(s
+ {
+ 	if (AR_SREV_9330_12(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-				ar9331_common_rx_gain_1p2,
+-				ARRAY_SIZE(ar9331_common_rx_gain_1p2),
+-				2);
++				ar9331_common_rx_gain_1p2);
+ 	else if (AR_SREV_9330_11(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-				ar9331_common_rx_gain_1p1,
+-				ARRAY_SIZE(ar9331_common_rx_gain_1p1),
+-				2);
++				ar9331_common_rx_gain_1p1);
+ 	else if (AR_SREV_9340(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-				ar9340Common_rx_gain_table_1p0,
+-				ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
+-				2);
++				ar9340Common_rx_gain_table_1p0);
+ 	else if (AR_SREV_9485_11(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-				ar9485Common_wo_xlna_rx_gain_1_1,
+-				ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
+-				2);
++				ar9485Common_wo_xlna_rx_gain_1_1);
+ 	else if (AR_SREV_9550(ah)) {
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-				ar955x_1p0_common_rx_gain_table,
+-				ARRAY_SIZE(ar955x_1p0_common_rx_gain_table),
+-				2);
++				ar955x_1p0_common_rx_gain_table);
+ 		INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
+-				ar955x_1p0_common_rx_gain_bounds,
+-				ARRAY_SIZE(ar955x_1p0_common_rx_gain_bounds),
+-				5);
++				ar955x_1p0_common_rx_gain_bounds);
+ 	} else if (AR_SREV_9580(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-				ar9580_1p0_rx_gain_table,
+-				ARRAY_SIZE(ar9580_1p0_rx_gain_table),
+-				2);
++				ar9580_1p0_rx_gain_table);
+ 	else if (AR_SREV_9462_20(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-				ar9462_common_rx_gain_table_2p0,
+-				ARRAY_SIZE(ar9462_common_rx_gain_table_2p0),
+-				2);
++				ar9462_common_rx_gain_table_2p0);
+ 	else
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-				ar9300Common_rx_gain_table_2p2,
+-				ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
+-				2);
++				ar9300Common_rx_gain_table_2p2);
+ }
+ 
+ static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
+ {
+ 	if (AR_SREV_9330_12(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-			ar9331_common_wo_xlna_rx_gain_1p2,
+-			ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2),
+-			2);
++			ar9331_common_wo_xlna_rx_gain_1p2);
+ 	else if (AR_SREV_9330_11(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-			ar9331_common_wo_xlna_rx_gain_1p1,
+-			ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1),
+-			2);
++			ar9331_common_wo_xlna_rx_gain_1p1);
+ 	else if (AR_SREV_9340(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-			ar9340Common_wo_xlna_rx_gain_table_1p0,
+-			ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
+-			2);
++			ar9340Common_wo_xlna_rx_gain_table_1p0);
+ 	else if (AR_SREV_9485_11(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-			ar9485Common_wo_xlna_rx_gain_1_1,
+-			ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
+-			2);
++			ar9485Common_wo_xlna_rx_gain_1_1);
+ 	else if (AR_SREV_9462_20(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-			ar9462_common_wo_xlna_rx_gain_table_2p0,
+-			ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
+-			2);
++			ar9462_common_wo_xlna_rx_gain_table_2p0);
+ 	else if (AR_SREV_9550(ah)) {
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-			ar955x_1p0_common_wo_xlna_rx_gain_table,
+-			ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
+-			2);
++			ar955x_1p0_common_wo_xlna_rx_gain_table);
+ 		INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
+-			ar955x_1p0_common_wo_xlna_rx_gain_bounds,
+-			ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
+-			5);
++			ar955x_1p0_common_wo_xlna_rx_gain_bounds);
+ 	} else if (AR_SREV_9580(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-			ar9580_1p0_wo_xlna_rx_gain_table,
+-			ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
+-			2);
++			ar9580_1p0_wo_xlna_rx_gain_table);
+ 	else
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-			ar9300Common_wo_xlna_rx_gain_table_2p2,
+-			ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
+-			2);
++			ar9300Common_wo_xlna_rx_gain_table_2p2);
+ }
+ 
+ static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
+ {
+ 	if (AR_SREV_9462_20(ah))
+ 		INIT_INI_ARRAY(&ah->iniModesRxGain,
+-			       ar9462_common_mixed_rx_gain_table_2p0,
+-			       ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);
++			       ar9462_common_mixed_rx_gain_table_2p0);
+ }
+ 
+ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)