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| author | Tomasz Maciej Nowak <tomek_n@o2.pl> | 2020-03-18 19:04:13 +0100 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2020-04-18 00:18:13 +0200 |
| commit | dee8fcfe9f84b584073ca28349c3c04634650744 (patch) | |
| tree | fe7be3b99a3ae6b29ebde1cd515b7e808cfc1136 /package/libs/mbedtls/Makefile | |
| parent | d8e0b015e82324dbb7ea701a1008babbf97fffe0 (diff) | |
| download | upstream-dee8fcfe9f84b584073ca28349c3c04634650744.tar.gz upstream-dee8fcfe9f84b584073ca28349c3c04634650744.tar.bz2 upstream-dee8fcfe9f84b584073ca28349c3c04634650744.zip | |
tegra: correct cpu subtype
Tegra 2 processors have only 16 double-precision registers. The change
introduced by 8dcc1087602e ("toolchain: ARM: Fix toolchain compilation
for gcc 8.x") switched accidentally the toolchain for tegra target to cpu
type with 32 double-precision registers. This stems from gcc defaults
which assume "vfpv3-d32" if only "vfpv3" as mfpu is specified. That
change resulted in unusable image, in which kernel will kill userspace as
soon as it causing "Illegal instruction".
Ref: https://forum.openwrt.org/t/gcc-was-broken-on-mvebu-armada-370-device-after-commit-on-2019-03-25/43272
Fixes: 8dcc1087602e ("toolchain: ARM: Fix toolchain compilation for
gcc 8.x")
Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl>
(cherry picked from commit 43d1d88510621801d66a0a7f46f4c4f44d89633a)
Diffstat (limited to 'package/libs/mbedtls/Makefile')
0 files changed, 0 insertions, 0 deletions