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| author | Hauke Mehrtens <hauke@hauke-m.de> | 2018-06-09 18:40:17 +0200 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2018-06-18 07:10:20 +0200 |
| commit | 9a26a9e8b9624d59e9d19b386d2365bb713e28b0 (patch) | |
| tree | 1a110d999b41bb983e0227c221cf73961c2f7857 /package/boot/uboot-sunxi/patches/310-sunxi-h3-Sync-OTG-and-HCI-nodes-from-Linux-DT.patch | |
| parent | f2135e7811fec7174f5a74bc579a6a8f936d1100 (diff) | |
| download | upstream-9a26a9e8b9624d59e9d19b386d2365bb713e28b0.tar.gz upstream-9a26a9e8b9624d59e9d19b386d2365bb713e28b0.tar.bz2 upstream-9a26a9e8b9624d59e9d19b386d2365bb713e28b0.zip | |
uboot-sunxi: update Orange Pi R1 and Zero Plus
The device tree files are now matching the kernel 4.17 and this will be
send also for integration into mainline U-Boot.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Diffstat (limited to 'package/boot/uboot-sunxi/patches/310-sunxi-h3-Sync-OTG-and-HCI-nodes-from-Linux-DT.patch')
| -rw-r--r-- | package/boot/uboot-sunxi/patches/310-sunxi-h3-Sync-OTG-and-HCI-nodes-from-Linux-DT.patch | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/package/boot/uboot-sunxi/patches/310-sunxi-h3-Sync-OTG-and-HCI-nodes-from-Linux-DT.patch b/package/boot/uboot-sunxi/patches/310-sunxi-h3-Sync-OTG-and-HCI-nodes-from-Linux-DT.patch new file mode 100644 index 0000000000..97aad78796 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/310-sunxi-h3-Sync-OTG-and-HCI-nodes-from-Linux-DT.patch @@ -0,0 +1,63 @@ +From 96c04aab58e351fa9ed7e95783018d6dbf60768f Mon Sep 17 00:00:00 2001 +From: Jun Nie <jun.nie@linaro.org> +Date: Mon, 7 May 2018 13:03:40 +0530 +Subject: sunxi: h3: Sync OTG and HCI nodes from Linux DT + +Allwinner H3 have a dual-routed USB PHY0 -- routed to either OHCI/EHCI +or MUSB controller. + +Signed-off-by: Jun Nie <jun.nie@linaro.org> +Reviewed-by: Jagan Teki <jagan@openedev.com> +Acked-by: Jun Nie <jun.nie@linaro.org> +--- + arch/arm/dts/sun8i-h3.dtsi | 32 ++++++++++++++++++++++++++++++++ + 1 file changed, 32 insertions(+) + +--- a/arch/arm/dts/sun8i-h3.dtsi ++++ b/arch/arm/dts/sun8i-h3.dtsi +@@ -219,6 +219,19 @@ + #size-cells = <0>; + }; + ++ usb_otg: usb@1c19000 { ++ compatible = "allwinner,sun8i-h3-musb"; ++ reg = <0x01c19000 0x400>; ++ clocks = <&ccu CLK_BUS_OTG>; ++ resets = <&ccu RST_BUS_OTG>; ++ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "mc"; ++ phys = <&usbphy 0>; ++ phy-names = "usb"; ++ extcon = <&usbphy 0>; ++ status = "disabled"; ++ }; ++ + usbphy: phy@01c19400 { + compatible = "allwinner,sun8i-h3-usb-phy"; + reg = <0x01c19400 0x2c>, +@@ -251,6 +264,25 @@ + #phy-cells = <1>; + }; + ++ ehci0: usb@1c1a000 { ++ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; ++ reg = <0x01c1a000 0x100>; ++ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; ++ resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; ++ status = "disabled"; ++ }; ++ ++ ohci0: usb@1c1a400 { ++ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; ++ reg = <0x01c1a400 0x100>; ++ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, ++ <&ccu CLK_USB_OHCI0>; ++ resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; ++ status = "disabled"; ++ }; ++ + ehci1: usb@01c1b000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1b000 0x100>; |