layerscape: add 64b/32b target for ls1012ardb device

The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

LEDE/OPENWRT will auto strip executable program file while make. So we
need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network
fiemware be destroyed, then run make to build ls1012ardb firmware.

The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message.
This issue have noticed the IP owner for investigate, hope he can solve it
earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default
firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4"
bootargs.

Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>

1 files changed, 283 insertions, 0 deletions

diff --git a/package/boot/uboot-layerscape/patches/0051-PPFE-warnings-Fix.patch b/package/boot/uboot-layerscape/patches/0051-PPFE-warnings-Fix.patch
new file mode 100644
index 0000000000..5397616cd8
--- /dev/null
+++ b/package/boot/uboot-layerscape/patches/0051-PPFE-warnings-Fix.patch
@@ -0,0 +1,283 @@
+From 4332e5748301df5b608f894e451999f873bda307 Mon Sep 17 00:00:00 2001
+From: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
+Date: Wed, 1 Jun 2016 05:18:38 +0530
+Subject: [PATCH 51/93] PPFE warnings Fix
+
+Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
+---
+ Makefile                                |    1 +
+ arch/arm/cpu/armv8/fsl-layerscape/cpu.c |    1 +
+ board/freescale/ls1012aqds/eth.c        |    4 ++--
+ board/freescale/ls1012ardb/eth.c        |    1 +
+ common/cmd_pfe_commands.c               |    7 +++++--
+ drivers/net/pfe_eth/pfe.c               |    7 ++++---
+ drivers/net/pfe_eth/pfe/pfe.h           |    2 +-
+ drivers/net/pfe_eth/pfe_driver.c        |    8 ++++----
+ drivers/net/pfe_eth/pfe_eth.c           |    7 +------
+ drivers/net/pfe_eth/pfe_eth.h           |    6 +++++-
+ drivers/net/pfe_eth/pfe_firmware.c      |    2 +-
+ 11 files changed, 26 insertions(+), 20 deletions(-)
+
+diff --git a/Makefile b/Makefile
+index 100de92..1c2818c 100644
+--- a/Makefile
++++ b/Makefile
+@@ -612,6 +612,7 @@ UBOOTINCLUDE    := \
+ 		$(if $(CONFIG_SYS_THUMB_BUILD), $(if $(CONFIG_HAS_THUMB2),, \
+ 			-I$(srctree)/arch/$(ARCH)/thumb1/include),) \
+ 		-I$(srctree)/arch/$(ARCH)/include \
++		-I$(srctree)/drivers/net/pfe_eth \
+ 		-include $(srctree)/include/linux/kconfig.h
+ 
+ NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include)
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+index 8f59577..bfd7078 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
++++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+@@ -20,6 +20,7 @@
+ #include <fm_eth.h>
+ #include <fsl_debug_server.h>
+ #include <fsl-mc/fsl_mc.h>
++#include <pfe_eth.h>
+ #ifdef CONFIG_FSL_ESDHC
+ #include <fsl_esdhc.h>
+ #endif
+diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
+index 1bd7c9d..6fbbdbe 100644
+--- a/board/freescale/ls1012aqds/eth.c
++++ b/board/freescale/ls1012aqds/eth.c
+@@ -27,8 +27,6 @@
+ 
+ #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+ 
+-static int mdio_mux[NUM_FM_PORTS];
+-
+ static const char * const mdio_names[] = {
+ 	"NULL",
+ 	"LS1012AQDS_MDIO_RGMII",
+@@ -85,6 +83,8 @@ static int ls1012aqds_mdio_reset(struct mii_dev *bus)
+ 
+ 	if(priv->realbus->reset)
+ 		return priv->realbus->reset(priv->realbus);
++	else
++		return -1;
+ }
+ 
+ static int ls1012aqds_mdio_init(char *realbusname, u8 muxval)
+diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
+index 638db95..7b0e450 100644
+--- a/board/freescale/ls1012ardb/eth.c
++++ b/board/freescale/ls1012ardb/eth.c
+@@ -17,6 +17,7 @@
+ 
+ #include "../../../drivers/net/pfe_eth/pfe_eth.h"
+ #include <asm/arch-fsl-layerscape/immap_lsch2.h>
++#include <i2c.h>
+ 
+ #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+ 
+diff --git a/common/cmd_pfe_commands.c b/common/cmd_pfe_commands.c
+index ca479d7..84999a6 100644
+--- a/common/cmd_pfe_commands.c
++++ b/common/cmd_pfe_commands.c
+@@ -602,7 +602,6 @@ void  bmu(int id, void *base)
+ static void pfe_pe_status(int argc, char * const argv[])
+ {
+ 	int do_clear = 0;
+-	int j;
+ 	u32 id;
+ 	u32 dmem_addr;
+ 	u32 cpu_state;
+@@ -612,9 +611,11 @@ static void pfe_pe_status(int argc, char * const argv[])
+ 	u32 drop;
+ 	char statebuf[5];
+ 	u32 class_debug_reg = 0;
++#ifdef CONFIG_PFE_WARN_WA
+ 	u32 debug_indicator;
+ 	u32 debug[16];
+-
++	int j;
++#endif
+ 	if (argc == 4 && strcmp(argv[3], "clear") == 0)
+ 		do_clear = 1;
+ 
+@@ -684,6 +685,7 @@ static void pfe_pe_status(int argc, char * const argv[])
+ 					statebuf, cpu_to_be32(activity_counter),
+ 					cpu_to_be32(rx), cpu_to_be32(tx), cpu_to_be32(drop));
+ 		}
++#ifdef CONFIG_PFE_WARN_WA
+ 		debug_indicator = pe_dmem_read(id, dmem_addr, 4);
+ 		dmem_addr += 4;
+ 		if (debug_indicator == cpu_to_be32('DBUG'))
+@@ -705,6 +707,7 @@ static void pfe_pe_status(int argc, char * const argv[])
+ 				printf("%08x%s", cpu_to_be32(debug[j]), (j & 0x7) == 0x7 || j == last - 1 ? "\n" : " ");
+ 			}
+ 		}
++#endif
+ 	}
+ 
+ }
+diff --git a/drivers/net/pfe_eth/pfe.c b/drivers/net/pfe_eth/pfe.c
+index 2c31cad..94cfe4e 100644
+--- a/drivers/net/pfe_eth/pfe.c
++++ b/drivers/net/pfe_eth/pfe.c
+@@ -368,6 +368,7 @@ void pe_lmem_write(u32 *src, u32 len, u32 offset)
+ 		class_bus_write(*src, PE_LMEM_BASE_ADDR + offset, (len & 0x03));
+ }
+ 
++#if !defined(CONFIG_UTIL_PE_DISABLED)
+ /** Writes UTIL program memory (DDR) from the host.
+  *
+  * @param[in] addr	Address to write (virtual, must be aligned on size)
+@@ -413,7 +414,7 @@ static void util_pmem_memcpy(void *dst, const void *src, unsigned int len)
+ 	if (len & 0x2)
+ 		util_pmem_write(*(u16 *)src, dst, len & 0x2);
+ }
+-
++#endif
+ 
+ /** Loads an elf section into pmem
+  * Code needs to be at least 16bit aligned and only PROGBITS sections are supported
+@@ -581,7 +582,7 @@ static int pe_load_ddr_section(int id, const void *data, Elf32_Shdr *shdr)
+ 						return -1;
+ 					}
+ 
+-					memcpy(DDR_PFE_TO_VIRT(addr), data + offset, size);
++					memcpy((void *)DDR_PFE_TO_VIRT(addr), data + offset, size);
+ 				}
+ 			}
+ 
+@@ -620,7 +621,7 @@ static int pe_load_ddr_section(int id, const void *data, Elf32_Shdr *shdr)
+ 		}
+ 		else
+ 		{
+-			memcpy(DDR_PFE_TO_VIRT(addr), data + offset, size);
++			memcpy((void *)DDR_PFE_TO_VIRT(addr), data + offset, size);
+ 		}
+ 
+ 		break;
+diff --git a/drivers/net/pfe_eth/pfe/pfe.h b/drivers/net/pfe_eth/pfe/pfe.h
+index 6994a20..9445155 100644
+--- a/drivers/net/pfe_eth/pfe/pfe.h
++++ b/drivers/net/pfe_eth/pfe/pfe.h
+@@ -50,7 +50,7 @@ extern void *ddr_base_addr;
+ #define PFE_CBUS_PHYS_BASE_ADDR	0xc0000000	/**< CBUS physical base address as seen by PE's. */
+ 
+ /* Host<->PFE Mapping */
+-#define DDR_PFE_TO_VIRT(p)	((p ) + 0x80000000)
++#define DDR_PFE_TO_VIRT(p)	((unsigned long int)((p ) + 0x80000000))
+ #define CBUS_VIRT_TO_PFE(v)	(((v) - CBUS_BASE_ADDR) + PFE_CBUS_PHYS_BASE_ADDR)
+ #define CBUS_PFE_TO_VIRT(p)	(((p) - PFE_CBUS_PHYS_BASE_ADDR) + CBUS_BASE_ADDR)
+ 
+diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
+index b06a352..2f4c385 100644
+--- a/drivers/net/pfe_eth/pfe_driver.c
++++ b/drivers/net/pfe_eth/pfe_driver.c
+@@ -87,7 +87,7 @@ int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
+ 	}
+ #endif
+ 
+-	*pkt_ptr = (unsigned int )(hif_header + 1);
++	*pkt_ptr = (unsigned long)(hif_header + 1);
+ 	*phy_port = hif_header->port_no;
+ 	len -= sizeof(struct hif_header_s);
+ 
+@@ -174,7 +174,7 @@ int pfe_send(int phy_port, void *data, int length)
+ 		length = MIN_PKT_SIZE;
+ 	}
+ 
+-	tx_buf_va = (u8 *)DDR_PFE_TO_VIRT(bd->data);
++	tx_buf_va = (void *)DDR_PFE_TO_VIRT(bd->data);
+ 	dprint("%s: tx_buf_va: %p, tx_buf_pa: %08x\n", __func__, tx_buf_va, bd->data);
+ 
+ 	/* Fill the gemac/phy port number to send this packet out */
+@@ -388,7 +388,7 @@ static int hif_rx_desc_init(struct pfe *pfe)
+ 	ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
+ #endif
+ 	for (i=0; i < rx_desc->rxRingSize; i++) {
+-		bd_va->next = (u32 )(bd_pa + 1);
++		bd_va->next = (unsigned long)(bd_pa + 1);
+ 		bd_va->ctrl = ctrl;
+ 		bd_va->data = rx_buf_pa + (i * MAX_FRAME_SIZE);
+ //		printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
+@@ -476,7 +476,7 @@ static int hif_tx_desc_init(struct pfe *pfe)
+ 	tx_buf_pa = pfe->ddr_phys_baseaddr + HIF_TX_PKT_DDR_BASEADDR;
+ 
+ 	for (i=0; i < tx_desc->txRingSize; i++) {
+-		bd_va->next = (u32 )(bd_pa + 1);
++		bd_va->next = (unsigned long)(bd_pa + 1);
+ 		bd_va->data = tx_buf_pa + (i * MAX_FRAME_SIZE);
+ //		printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
+ //			bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
+diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
+index 4aa318d..4a935ca 100644
+--- a/drivers/net/pfe_eth/pfe_eth.c
++++ b/drivers/net/pfe_eth/pfe_eth.c
+@@ -53,10 +53,6 @@ static void ls1012a_gemac_disable(void *gemac_base)
+         writel(readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);	
+ }
+ 
+-static void ls1012a_gemac_set_mode(void *gemac_base, u32 mode)
+-{
+-}
+-
+ static void ls1012a_gemac_set_speed(void *gemac_base, u32 speed)
+ {
+ 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+@@ -125,7 +121,6 @@ static int ls1012a_eth_init(struct eth_device *dev, bd_t * bd)
+         struct ls1012a_eth_dev *priv = (struct ls1012a_eth_dev *)dev->priv;
+         struct gemac_s *gem = priv->gem;
+ 	int speed;
+-	int tmp;
+ 
+         /* set ethernet mac address */
+         ls1012a_gemac_set_ethaddr(gem->gemac_base, dev->enetaddr);
+@@ -220,7 +215,7 @@ static int ls1012a_eth_recv(struct eth_device *dev)
+         }
+ 
+ 	// Pass the packet up to the protocol layers.
+-	net_process_received_packet((uchar *)pkt_buf, len);
++	net_process_received_packet((void *)(long int)pkt_buf, len);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/net/pfe_eth/pfe_eth.h b/drivers/net/pfe_eth/pfe_eth.h
+index c16b8c0..af6191d 100644
+--- a/drivers/net/pfe_eth/pfe_eth.h
++++ b/drivers/net/pfe_eth/pfe_eth.h
+@@ -26,6 +26,7 @@
+ 
+ 
+ #include "pfe_driver.h"
++#include <phy.h>
+ 
+ #ifndef SZ_1K
+ #define SZ_1K 1024
+@@ -151,7 +152,10 @@ struct firmware {
+ 
+ int pfe_probe(struct pfe *pfe);
+ int pfe_remove(struct pfe *pfe);
+-
++struct mii_dev *ls1012a_mdio_init(struct mdio_info *mdio_info);
++void ls1012a_set_mdio(int dev_id, struct mii_dev *bus);
++void ls1012a_set_phy_address_mode(int dev_id, int phy_id, int phy_mode);
++int ls1012a_gemac_initialize(bd_t * bis, int dev_id, char *devname);
+ 
+ //#define dprint(fmt, arg...)	printf(fmt, ##arg)
+ #define dprint(fmt, arg...)
+diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c
+index 165eb3c..5957afd 100644
+--- a/drivers/net/pfe_eth/pfe_firmware.c
++++ b/drivers/net/pfe_eth/pfe_firmware.c
+@@ -45,7 +45,7 @@ int pfe_load_elf(int pe_mask, const struct firmware *fw)
+ 	printf("%s: no of sections: %d\n", __func__, sections);
+ 
+ 	/* Some sanity checks */
+-	if (strncmp(&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG))
++	if (strncmp((char *)&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG))
+ 	{
+ 		printf("%s: incorrect elf magic number\n", __func__);
+ 		return -1;
+-- 
+1.7.9.5
+