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| author | Adrian Schmutzler <freifunk@adrianschmutzler.de> | 2019-11-14 12:26:05 +0100 |
|---|---|---|
| committer | Adrian Schmutzler <freifunk@adrianschmutzler.de> | 2019-11-17 13:06:31 +0100 |
| commit | a9d3084b83bb2d0fa2c0b43bf2a0831b5ae1df13 (patch) | |
| tree | 1f4edc5de326eeca2c1c98063f9d4c652b440841 | |
| parent | 7a7610c21bb0979f2ae14f3c31012ac9e148b439 (diff) | |
| download | upstream-a9d3084b83bb2d0fa2c0b43bf2a0831b5ae1df13.tar.gz upstream-a9d3084b83bb2d0fa2c0b43bf2a0831b5ae1df13.tar.bz2 upstream-a9d3084b83bb2d0fa2c0b43bf2a0831b5ae1df13.zip | |
ar71xx: fix MAC address setup for TL-WDR4900 v2
The MAC address setup of the TL-WDR4900 v2 is different from the
C5/C7. This aligns ar71xx with the setup in ath79:
wlan0 (5GHz) : -2
wlan1 (2.4GHz) : -1
eth1 (LAN) : 0
eth0 (WAN) : 1
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c index 923ed28b4a..304a8c7057 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c @@ -207,19 +207,22 @@ static void __init common_setup(bool pcie_slot) u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); u8 tmpmac[ETH_ALEN]; + u8 tmpmac2[ETH_ALEN]; ath79_register_m25p80(&archer_c7_flash_data); ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c7_leds_gpio), archer_c7_leds_gpio); - ath79_register_wmac(art + ARCHER_C7_WMAC_CALDATA_OFFSET, mac); - if (pcie_slot) { + ath79_register_wmac(art + ARCHER_C7_WMAC_CALDATA_OFFSET, mac); ath79_register_pci(); } else { ath79_init_mac(tmpmac, mac, -1); + ath79_register_wmac(art + ARCHER_C7_WMAC_CALDATA_OFFSET, tmpmac); + + ath79_init_mac(tmpmac2, mac, -2); ap9x_pci_setup_wmac_led_pin(0, 0); - ap91_pci_init(art + ARCHER_C7_PCIE_CALDATA_OFFSET, tmpmac); + ap91_pci_init(art + ARCHER_C7_PCIE_CALDATA_OFFSET, tmpmac2); } mdiobus_register_board_info(archer_c7_mdio0_info, |