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| author | Matteo Croce <rootkit85@yahoo.it> | 2008-01-29 20:47:34 +0000 |
|---|---|---|
| committer | Matteo Croce <rootkit85@yahoo.it> | 2008-01-29 20:47:34 +0000 |
| commit | 72506a987f811b57f8d6751f1c636acdcc4ba82b (patch) | |
| tree | 37e60c77f22e02b20187db878bfae50b83dd720e | |
| parent | 0b96bf6063626538e1d646835cf19f68175baa46 (diff) | |
| download | upstream-72506a987f811b57f8d6751f1c636acdcc4ba82b.tar.gz upstream-72506a987f811b57f8d6751f1c636acdcc4ba82b.tar.bz2 upstream-72506a987f811b57f8d6751f1c636acdcc4ba82b.zip | |
added missing war.h
SVN-Revision: 10315
| -rw-r--r-- | target/linux/ar7/files/include/asm-mips/war.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/target/linux/ar7/files/include/asm-mips/war.h b/target/linux/ar7/files/include/asm-mips/war.h new file mode 100644 index 0000000000..4a2b7986b5 --- /dev/null +++ b/target/linux/ar7/files/include/asm-mips/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MIPS_MACH_BCM947XX_WAR_H +#define __ASM_MIPS_MACH_BCM947XX_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_BCM947XX_WAR_H */ |