--- a/arch/arm/configs/ixp4xx_defconfig +++ b/arch/arm/configs/ixp4xx_defconfig @@ -15,6 +15,8 @@ CONFIG_ARCH_ADI_COYOTE=y CONFIG_MACH_GATEWAY7001=y CONFIG_MACH_WG302V1=y CONFIG_MACH_WG302V2=y +CONFIG_MACH_PRONGHORN=y +CONFIG_MACH_PRONGHORNMETRO=y CONFIG_ARCH_IXDP425=y CONFIG_MACH_IXDPG425=y CONFIG_MACH_IXDP465=y --- a/arch/arm/mach-ixp4xx/Kconfig +++ b/arch/arm/mach-ixp4xx/Kconfig @@ -61,6 +61,22 @@ config MACH_WG302V2 WG302 v2 or WAG302 v2 Access Points. For more information on this platform, see http://openwrt.org +config MACH_PRONGHORN + bool "ADI Pronghorn series" + select PCI + help + Say 'Y' here if you want your kernel to support the ADI + Engineering Pronghorn series. For more + information on this platform, see http://www.adiengineering.com + +# +# There're only minimal differences kernel-wise between the Pronghorn and +# Pronghorn Metro boards - they use different chip selects to drive the +# CF slot connected to the expansion bus, so we just enable them together. +# +config MACH_PRONGHORNMETRO + def_bool MACH_PRONGHORN + config ARCH_IXDP425 bool "IXDP425" help --- a/arch/arm/mach-ixp4xx/Makefile +++ b/arch/arm/mach-ixp4xx/Makefile @@ -19,6 +19,7 @@ obj-pci-$(CONFIG_MACH_WG302V1) += wg302 obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o obj-pci-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-pci.o +obj-pci-$(CONFIG_MACH_PRONGHORN) += pronghorn-pci.o obj-y += common.o @@ -39,6 +40,7 @@ obj-$(CONFIG_MACH_WG302V2) += wg302v2-se obj-$(CONFIG_MACH_FSG) += fsg-setup.o obj-$(CONFIG_MACH_GORAMO_MLR) += goramo_mlr.o obj-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-setup.o +obj-$(CONFIG_MACH_PRONGHORN) += pronghorn-setup.o obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o --- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h +++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h @@ -42,7 +42,8 @@ static __inline__ void __arch_decomp_set */ if (machine_is_adi_coyote() || machine_is_gtwx5715() || machine_is_gateway7001() || machine_is_wg302v2() || - machine_is_devixp() || machine_is_miccpt() || machine_is_mic256()) + machine_is_devixp() || machine_is_miccpt() || machine_is_mic256() || + machine_is_pronghorn() || machine_is_pronghorn_metro()) uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; else uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; --- /dev/null +++ b/arch/arm/mach-ixp4xx/pronghorn-pci.c @@ -0,0 +1,69 @@ +/* + * arch/arch/mach-ixp4xx/pronghorn-pci.c + * + * PCI setup routines for ADI Engineering Pronghorn series + * + * Copyright (C) 2008 Imre Kaloz + * + * based on coyote-pci.c: + * Copyright (C) 2002 Jungo Software Technologies. + * Copyright (C) 2003 MontaVista Softwrae, Inc. + * + * Maintainer: Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include + +#include +#include + +#include + +void __init pronghorn_pci_preinit(void) +{ + irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(IRQ_IXP4XX_GPIO1, IRQ_TYPE_LEVEL_LOW); + + ixp4xx_pci_preinit(); +} + +static int __init pronghorn_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + if (slot == 13) + return IRQ_IXP4XX_GPIO4; + else if (slot == 14) + return IRQ_IXP4XX_GPIO6; + else if (slot == 15) + return IRQ_IXP4XX_GPIO11; + else if (slot == 16) + return IRQ_IXP4XX_GPIO1; + else + return -1; +} + +struct hw_pci pronghorn_pci __initdata = { + .nr_controllers = 1, + .preinit = pronghorn_pci_preinit, + .ops = &ixp4xx_ops, + .setup = ixp4xx_setup, + .map_irq = pronghorn_map_irq, +}; + +int __init pronghorn_pci_init(void) +{ + if (machine_is_pronghorn() || machine_is_pronghorn_metro()) + pci_common_init(&pronghorn_pci); + return 0; +} + +subsys_initcall(pronghorn_pci_init); --- /dev/null +++ b/arch/arm/mach-ixp4xx/pronghorn-setup.c @@ -0,0 +1,252 @@ +/* + * arch/arm/mach-ixp4xx/pronghorn-setup.c + * + * Board setup for the ADI Engineering Pronghorn series + * + * Copyright (C) 2008 Imre Kaloz + * + * based on coyote-setup.c: + * Copyright (C) 2003-2005 MontaVista Software, Inc. + * + * Author: Imre Kaloz + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +static struct flash_platform_data pronghorn_flash_data = { + .map_name = "cfi_probe", + .width = 2, +}; + +static struct resource pronghorn_flash_resource = { + .flags = IORESOURCE_MEM, +}; + +static struct platform_device pronghorn_flash = { + .name = "IXP4XX-Flash", + .id = 0, + .dev = { + .platform_data = &pronghorn_flash_data, + }, + .num_resources = 1, + .resource = &pronghorn_flash_resource, +}; + +static struct resource pronghorn_uart_resources [] = { + { + .start = IXP4XX_UART1_BASE_PHYS, + .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, + .flags = IORESOURCE_MEM + }, + { + .start = IXP4XX_UART2_BASE_PHYS, + .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, + .flags = IORESOURCE_MEM + } +}; + +static struct plat_serial8250_port pronghorn_uart_data[] = { + { + .mapbase = IXP4XX_UART1_BASE_PHYS, + .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, + .irq = IRQ_IXP4XX_UART1, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = IXP4XX_UART_XTAL, + }, + { + .mapbase = IXP4XX_UART2_BASE_PHYS, + .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, + .irq = IRQ_IXP4XX_UART2, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = IXP4XX_UART_XTAL, + }, + { }, +}; + +static struct platform_device pronghorn_uart = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = pronghorn_uart_data, + }, + .num_resources = 2, + .resource = pronghorn_uart_resources, +}; + +static struct i2c_gpio_platform_data pronghorn_i2c_gpio_data = { + .sda_pin = 9, + .scl_pin = 10, +}; + +static struct platform_device pronghorn_i2c_gpio = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &pronghorn_i2c_gpio_data, + }, +}; + +static struct gpio_led pronghorn_led_pin[] = { + { + .name = "pronghorn:green:status", + .gpio = 7, + } +}; + +static struct gpio_led_platform_data pronghorn_led_data = { + .num_leds = 1, + .leds = pronghorn_led_pin, +}; + +static struct platform_device pronghorn_led = { + .name = "leds-gpio", + .id = -1, + .dev.platform_data = &pronghorn_led_data, +}; + +static struct resource pronghorn_pata_resources[] = {
--- a/arch/mips/bcm63xx/usb-common.c
+++ b/arch/mips/bcm63xx/usb-common.c
@@ -109,6 +109,27 @@ void bcm63xx_usb_priv_ohci_cfg_set(void)
 		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
 		reg |= USBH_PRIV_SETUP_IOC_MASK;
 		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
+	} else if (BCMCPU_IS_6318()) {
+		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
+		reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN;
+		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
+
+		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG);
+		reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK;
+		reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK;
+		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6318_REG);
+
+		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6318_REG);
+		reg |= USBH_PRIV_SETUP_IOC_MASK;
+		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG);
+
+		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
+		reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN;
+		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
+
+		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG);
+		reg |= USBH_PRIV_SIM_CTRL_LADDR_SEL;
+		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SIM_CTRL_6318_REG);
 	}
 
 	spin_unlock_irqrestore(&usb_priv_reg_lock, flags);
@@ -144,6 +165,27 @@ void bcm63xx_usb_priv_ehci_cfg_set(void)
 		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
 		reg |= USBH_PRIV_SETUP_IOC_MASK;
 		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
+	} else if (BCMCPU_IS_6318()) {
+		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
+		reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN;
+		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
+
+		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG);
+		reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK;
+		reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK;
+		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6318_REG);
+
+		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6318_REG);
+		reg |= USBH_PRIV_SETUP_IOC_MASK;
+		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG);
+
+		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
+		reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN;
+		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
+
+		reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG);
+		reg |= USBH_PRIV_SIM_CTRL_LADDR_SEL;
+		bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SIM_CTRL_6318_REG);
 	}
 
 	spin_unlock_irqrestore(&usb_priv_reg_lock, flags);
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -681,6 +681,12 @@
 #define GPIO_MODE_6368_SPI_SSN4		(1 << 30)
 #define GPIO_MODE_6368_SPI_SSN5		(1 << 31)
 
+#define GPIO_PINMUX_SEL0_6318		0x1c
+#define GPIO_PINMUX_SEL0_GPIO13_SHIFT	26
+#define GPIO_PINMUX_SEL0_GPIO13_MASK	(0x3 << GPIO_PINMUX_SEL0_GPIO13_SHIFT)
+#define GPIO_PINMUX_SEL0_GPIO13_PWRON	(1 << GPIO_PINMUX_SEL0_GPIO13_SHIFT)
+#define GPIO_PINMUX_SEL0_GPIO13_LED	(2 << GPIO_PINMUX_SEL0_GPIO13_SHIFT)
+#define GPIO_PINMUX_SEL0_GPIO13_GPIO	(3 << GPIO_PINMUX_SEL0_GPIO13_SHIFT)
 
 #define GPIO_PINMUX_OTHR_REG		0x24
 #define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12
@@ -999,6 +1005,7 @@
 
 #define USBH_PRIV_SWAP_6358_REG		0x0
 #define USBH_PRIV_SWAP_6368_REG		0x1c
+#define USBH_PRIV_SWAP_6318_REG		0x0c
 
 #define USBH_PRIV_SWAP_USBD_SHIFT	6
 #define USBH_PRIV_SWAP_USBD_MASK	(1 << USBH_PRIV_SWAP_USBD_SHIFT)
@@ -1024,6 +1031,13 @@
 #define USBH_PRIV_SETUP_IOC_SHIFT	4
 #define USBH_PRIV_SETUP_IOC_MASK	(1 << USBH_PRIV_SETUP_IOC_SHIFT)
 
+#define USBH_PRIV_SETUP_6318_REG	0x00
+#define USBH_PRIV_PLL_CTRL1_6318_REG	0x04
+#define USBH_PRIV_PLL_CTRL1_SUSP_EN	(1 << 27)
+#define USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN	(1 << 31)
+#define USBH_PRIV_SIM_CTRL_6318_REG	0x20
+#define USBH_PRIV_SIM_CTRL_LADDR_SEL	(1 << 5)
+
 
 /*************************************************************************
  * _REG relative to RSET_USBD
--- a/arch/mips/bcm63xx/boards/board_common.c
+++ b/arch/mips/bcm63xx/boards/board_common.c
@@ -126,6 +126,15 @@ void __init board_early_setup(const stru
 	}
 
 	bcm_gpio_writel(val, GPIO_MODE_REG);
+
+#if IS_ENABLED(CONFIG_USB)
+	if (BCMCPU_IS_6318() && (board.has_ehci0 || board.has_ohci0)) {
+		val = bcm_gpio_readl(GPIO_PINMUX_SEL0_6318);
+		val &= ~GPIO_PINMUX_SEL0_GPIO13_MASK;
+		val |= GPIO_PINMUX_SEL0_GPIO13_PWRON;
+		bcm_gpio_writel(val, GPIO_PINMUX_SEL0_6318);
+	}
+#endif
 }
 
 
--- a/arch/mips/bcm63xx/Kconfig
+++ b/arch/mips/bcm63xx/Kconfig
@@ -22,6 +22,8 @@ config BCM63XX_CPU_6318
 	bool "support 6318 CPU"
 	select SYS_HAS_CPU_BMIPS32_3300
 	select HW_HAS_PCI
+	select BCM63XX_OHCI
+	select BCM63XX_EHCI
 
 config BCM63XX_CPU_6328
 	bool "support 6328 CPU"
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-29 16:35:29 +0000