From d1b4dfc97bb0e911680426afa0213d9d174839d7 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 23 Mar 2016 12:52:17 +0000 Subject: Revert "ar71xx: Allow to set the RXDV, RXD, TXD, TXE delays for QCA955x" The default delays RXD 3. RDV 3, TXD 0, TXE 0 doesn't seem to work for some boards. These boards depend on the preset values of u-boot which may differ. This reverts commit f2d4bb96b62512caa161dcc2867c91692fb16a38. Signed-off-by: Sven Eckelmann git-svn-id: svn://svn.openwrt.org/openwrt/trunk@49071 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd-v2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd-v2.c') diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd-v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd-v2.c index 73808aba2b..abdbde08d2 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd-v2.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd-v2.c @@ -183,7 +183,7 @@ static void __init tl_wr1043nd_v2_setup(void) ARRAY_SIZE(wr1043nd_v2_mdio0_info)); ath79_register_mdio(0, 0x0); - ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0); + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); /* GMAC0 is connected to the RMGII interface */ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -- cgit v1.2.3