| Commit message (Collapse) | Author | Age | Files | Lines |
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At least on my b53 chip, the mask is 3 bits wide, and because
of this some STP states are not set properly and discarded when read.
Maybe for some other chips it makes sense to have just 2 bits width,
but I don't have other versions around to test/validate.
If that's the case then maybe we could add another STP state mask.
Signed-off-by: Alexandru Ardelean <ardeleanalex@gmail.com>
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45937 3c298f89-4303-0410-b956-a3cf2f4a3e73
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On BCM5301X there are two different cases to handle: CPU port 8 vs. any
other one. Support for CPU port 8 was already partially implemented but
it lacked setting some extra bit for 2G speed. It also will need to be
extended to implement "SMP dual core 3 GMAC setup". That's the reason
for handling it in separated code block.
This patch also adds overriding CPU port state for port other than 8. It
requires using recently defined GMII_PORT registers.
It was tested for regressions on BCM53011 revs 2 & 3. It was also
confirmed to fix switch on some internal Broadcom board.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Jonas Gorski <jogo@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45402 3c298f89-4303-0410-b956-a3cf2f4a3e73
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* properly enclose macro arguments in paranthesis on use
* remove trailing white space
* convert C99 // comments
* add missing blank lines after declaration
* remove braces from single statement blocks
* split lines > 80 chars (except for one)
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45356 3c298f89-4303-0410-b956-a3cf2f4a3e73
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They are also present on some BCM63xx switches.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45355 3c298f89-4303-0410-b956-a3cf2f4a3e73
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@44875 3c298f89-4303-0410-b956-a3cf2f4a3e73
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The BCM5365 needs a shift of 7 bits and not 6 bits like the BCM5325 for
the untagged ports.
Thank you Russell for reporting this and testing the patch.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@38793 3c298f89-4303-0410-b956-a3cf2f4a3e73
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The revision is stored in a different register than it is in other
Broadcom switches.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@37995 3c298f89-4303-0410-b956-a3cf2f4a3e73
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Add swconfig switch driver for Broadcom BCM53XX switch chips. Supports
switches connected through MDIO, SPI or memory mapped registers, and
supports BCM5325, BCM539x, BCM531x5 and the BCM63XX internal switch
chips.
Tested are BCM5325 trough MDIO, BCM53115 through SPI, and BCM6328.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@35305 3c298f89-4303-0410-b956-a3cf2f4a3e73
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