diff options
Diffstat (limited to 'target/linux/imx6/patches-3.14')
21 files changed, 0 insertions, 4458 deletions
diff --git a/target/linux/imx6/patches-3.14/0001-ARM-dts-disable-flexcan-by-default.patch b/target/linux/imx6/patches-3.14/0001-ARM-dts-disable-flexcan-by-default.patch deleted file mode 100644 index babd544af8..0000000000 --- a/target/linux/imx6/patches-3.14/0001-ARM-dts-disable-flexcan-by-default.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 1759b172f78263de7077a2743e11f3b718682849 Mon Sep 17 00:00:00 2001 -From: Tim Harvey <tharvey@gateworks.com> -Date: Tue, 22 Oct 2013 21:51:27 -0700 -Subject: [PATCH 1/3] ARM: dts: disable flexcan by default - -Typically nodes are disabled by default and enabled when needed. - -Signed-off-by: Tim Harvey <tharvey@gateworks.com> -Signed-off-by: Shawn Guo <shawn.guo@linaro.org> ---- - arch/arm/boot/dts/imx6qdl.dtsi | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm/boot/dts/imx6qdl.dtsi -+++ b/arch/arm/boot/dts/imx6qdl.dtsi -@@ -331,6 +331,7 @@ - interrupts = <0 110 0x04>; - clocks = <&clks 108>, <&clks 109>; - clock-names = "ipg", "per"; -+ status = "disabled"; - }; - - can2: flexcan@02094000 { -@@ -339,6 +340,7 @@ - interrupts = <0 111 0x04>; - clocks = <&clks 110>, <&clks 111>; - clock-names = "ipg", "per"; -+ status = "disabled"; - }; - - gpt: gpt@02098000 { diff --git a/target/linux/imx6/patches-3.14/0002-ARM-dts-added-several-new-imx-pinmux-groups.patch b/target/linux/imx6/patches-3.14/0002-ARM-dts-added-several-new-imx-pinmux-groups.patch deleted file mode 100644 index f2d7f6ca17..0000000000 --- a/target/linux/imx6/patches-3.14/0002-ARM-dts-added-several-new-imx-pinmux-groups.patch +++ /dev/null @@ -1,115 +0,0 @@ -From 925467009cc6d92edb02b9e68710db022cd56f41 Mon Sep 17 00:00:00 2001 -From: Tim Harvey <tharvey@gateworks.com> -Date: Tue, 22 Oct 2013 21:51:25 -0700 -Subject: [PATCH 2/3] ARM: dts: added several new imx-pinmux groups - -Signed-off-by: Tim Harvey <tharvey@gateworks.com> -Signed-off-by: Shawn Guo <shawn.guo@linaro.org> ---- - arch/arm/boot/dts/imx6qdl.dtsi | 60 ++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 60 insertions(+) - ---- a/arch/arm/boot/dts/imx6qdl.dtsi -+++ b/arch/arm/boot/dts/imx6qdl.dtsi -@@ -639,6 +639,14 @@ - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000 - >; - }; -+ -+ pinctrl_audmux_4: audmux-4 { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x80000000 -+ MX6QDL_PAD_EIM_D25__AUD5_RXC 0x80000000 -+ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000 -+ >; -+ }; - }; - - ecspi1 { -@@ -811,6 +819,28 @@ - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; -+ -+ /* No Strobe */ -+ pinctrl_gpmi_nand_2: gpmi-nand-2 { -+ fsl,pins = < -+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 -+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 -+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 -+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 -+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 -+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 -+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 -+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 -+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 -+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 -+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 -+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 -+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 -+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 -+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 -+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 -+ >; -+ }; - }; - - hdmi_hdcp { -@@ -1058,6 +1088,13 @@ - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; -+ -+ pinctrl_uart1_2: uart1grp-2 { -+ fsl,pins = < -+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 -+ >; -+ }; - }; - - uart2 { -@@ -1076,6 +1113,13 @@ - MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 - >; - }; -+ -+ pinctrl_uart2_3: uart2grp-3 { -+ fsl,pins = < -+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 -+ >; -+ }; - }; - - uart3 { -@@ -1096,6 +1140,13 @@ - MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 - >; - }; -+ -+ pinctrl_uart3_3: uart3grp-3 { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 -+ >; -+ }; - }; - - uart4 { -@@ -1106,6 +1157,15 @@ - >; - }; - }; -+ -+ uart5 { -+ pinctrl_uart5_1: uart5grp-1 { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 -+ >; -+ }; -+ }; - - usbotg { - pinctrl_usbotg_1: usbotggrp-1 { diff --git a/target/linux/imx6/patches-3.14/0003-ARM-dts-add-Gateworks-Ventana-support.patch b/target/linux/imx6/patches-3.14/0003-ARM-dts-add-Gateworks-Ventana-support.patch deleted file mode 100644 index cfc2898d2e..0000000000 --- a/target/linux/imx6/patches-3.14/0003-ARM-dts-add-Gateworks-Ventana-support.patch +++ /dev/null @@ -1,2886 +0,0 @@ -From e3946fe8050534ccaf8c1266cb1fa90c7f3345c3 Mon Sep 17 00:00:00 2001 -From: Tim Harvey <tharvey@gateworks.com> -Date: Fri, 7 Feb 2014 15:24:56 +0800 -Subject: [PATCH] ARM: dts: add Gateworks Ventana support - -The Gateworks Ventana product family consists of several baseboard designs -based on the Freescale i.MX6 family of processors. Each baseboard has a -different set of possible features. - -Signed-off-by: Tim Harvey <tharvey@gateworks.com> -Signed-off-by: Shawn Guo <shawn.guo@linaro.org> ---- - arch/arm/boot/dts/Makefile | 9 + - arch/arm/boot/dts/imx6dl-gw51xx.dts | 19 ++ - arch/arm/boot/dts/imx6dl-gw52xx.dts | 19 ++ - arch/arm/boot/dts/imx6dl-gw53xx.dts | 19 ++ - arch/arm/boot/dts/imx6dl-gw54xx.dts | 19 ++ - arch/arm/boot/dts/imx6q-gw51xx.dts | 19 ++ - arch/arm/boot/dts/imx6q-gw52xx.dts | 23 ++ - arch/arm/boot/dts/imx6q-gw53xx.dts | 23 ++ - arch/arm/boot/dts/imx6q-gw5400-a.dts | 546 ++++++++++++++++++++++++++++++++ - arch/arm/boot/dts/imx6q-gw54xx.dts | 23 ++ - arch/arm/boot/dts/imx6qdl-gw51xx.dtsi | 374 ++++++++++++++++++++++ - arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 490 ++++++++++++++++++++++++++++ - arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 553 ++++++++++++++++++++++++++++++++ - arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 580 ++++++++++++++++++++++++++++++++++ - 14 files changed, 2716 insertions(+) - create mode 100644 arch/arm/boot/dts/imx6dl-gw51xx.dts - create mode 100644 arch/arm/boot/dts/imx6dl-gw52xx.dts - create mode 100644 arch/arm/boot/dts/imx6dl-gw53xx.dts - create mode 100644 arch/arm/boot/dts/imx6dl-gw54xx.dts - create mode 100644 arch/arm/boot/dts/imx6q-gw51xx.dts - create mode 100644 arch/arm/boot/dts/imx6q-gw52xx.dts - create mode 100644 arch/arm/boot/dts/imx6q-gw53xx.dts - create mode 100644 arch/arm/boot/dts/imx6q-gw5400-a.dts - create mode 100644 arch/arm/boot/dts/imx6q-gw54xx.dts - create mode 100644 arch/arm/boot/dts/imx6qdl-gw51xx.dtsi - create mode 100644 arch/arm/boot/dts/imx6qdl-gw52xx.dtsi - create mode 100644 arch/arm/boot/dts/imx6qdl-gw53xx.dtsi - create mode 100644 arch/arm/boot/dts/imx6qdl-gw54xx.dtsi - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -154,12 +154,21 @@ dtb-$(CONFIG_ARCH_MXC) += \ - imx53-qsb.dtb \ - imx53-smd.dtb \ - imx6dl-cubox-i.dtb \ -+ imx6dl-gw51xx.dtb \ -+ imx6dl-gw52xx.dtb \ -+ imx6dl-gw53xx.dtb \ -+ imx6dl-gw54xx.dtb \ - imx6dl-hummingboard.dtb \ - imx6dl-sabreauto.dtb \ - imx6dl-sabresd.dtb \ - imx6dl-wandboard.dtb \ - imx6q-arm2.dtb \ - imx6q-cubox-i.dtb \ -+ imx6q-gw51xx.dtb \ -+ imx6q-gw52xx.dtb \ -+ imx6q-gw53xx.dtb \ -+ imx6q-gw5400-a.dtb \ -+ imx6q-gw54xx.dtb \ - imx6q-phytec-pbab01.dtb \ - imx6q-sabreauto.dtb \ - imx6q-sabrelite.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/imx6dl-gw51xx.dts -@@ -0,0 +1,19 @@ -+/* -+ * Copyright 2013 Gateworks Corporation -+ * -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/dts-v1/; -+#include "imx6dl.dtsi" -+#include "imx6qdl-gw51xx.dtsi" -+ -+/ { -+ model = "Gateworks Ventana i.MX6 DualLite/Solo GW51XX"; -+ compatible = "gw,imx6dl-gw51xx", "gw,ventana", "fsl,imx6dl"; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/imx6dl-gw52xx.dts -@@ -0,0 +1,19 @@ -+/* -+ * Copyright 2013 Gateworks Corporation -+ * -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/dts-v1/; -+#include "imx6dl.dtsi" -+#include "imx6qdl-gw52xx.dtsi" -+ -+/ { -+ model = "Gateworks Ventana i.MX6 DualLite/Solo GW52XX"; -+ compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl"; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/imx6dl-gw53xx.dts -@@ -0,0 +1,19 @@ -+/* -+ * Copyright 2013 Gateworks Corporation -+ * -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/dts-v1/; -+#include "imx6dl.dtsi" -+#include "imx6qdl-gw53xx.dtsi" -+ -+/ { -+ model = "Gateworks Ventana i.MX6 DualLite/Solo GW53XX"; -+ compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl"; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/imx6dl-gw54xx.dts -@@ -0,0 +1,19 @@ -+/* -+ * Copyright 2013 Gateworks Corporation -+ * -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/dts-v1/; -+#include "imx6dl.dtsi" -+#include "imx6qdl-gw54xx.dtsi" -+ -+/ { -+ model = "Gateworks Ventana i.MX6 DualLite/Solo GW54XX"; -+ compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl"; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/imx6q-gw51xx.dts -@@ -0,0 +1,19 @@ -+/* -+ * Copyright 2013 Gateworks Corporation -+ * -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/dts-v1/; -+#include "imx6q.dtsi" -+#include "imx6qdl-gw51xx.dtsi" -+ -+/ { -+ model = "Gateworks Ventana i.MX6 Dual/Quad GW51XX"; -+ compatible = "gw,imx6q-gw51xx", "gw,ventana", "fsl,imx6q"; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/imx6q-gw52xx.dts -@@ -0,0 +1,23 @@ -+/* -+ * Copyright 2013 Gateworks Corporation -+ * -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/dts-v1/; -+#include "imx6q.dtsi" -+#include "imx6qdl-gw52xx.dtsi" -+ -+/ { -+ model = "Gateworks Ventana i.MX6 Dual/Quad GW52XX"; -+ compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q"; -+}; -+ -+&sata { -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/imx6q-gw53xx.dts -@@ -0,0 +1,23 @@ -+/* -+ * Copyright 2013 Gateworks Corporation -+ * -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/dts-v1/; -+#include "imx6q.dtsi" -+#include "imx6qdl-gw53xx.dtsi" -+ -+/ { -+ model = "Gateworks Ventana i.MX6 Dual/Quad GW53XX"; -+ compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q"; -+}; -+ -+&sata { -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts -@@ -0,0 +1,543 @@ -+/* -+ * Copyright 2013 Gateworks Corporation -+ * -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/dts-v1/; -+#include "imx6q.dtsi" -+ -+/ { -+ model = "Gateworks Ventana GW5400-A"; -+ compatible = "gw,imx6q-gw5400-a", "gw,ventana", "fsl,imx6q"; -+ -+ /* these are used by bootloader for disabling nodes */ -+ aliases { -+ ethernet0 = &fec; -+ ethernet1 = ð1; -+ i2c0 = &i2c1; -+ i2c1 = &i2c2; -+ i2c2 = &i2c3; -+ led0 = &led0; -+ led1 = &led1; -+ led2 = &led2; -+ sky2 = ð1; -+ ssi0 = &ssi1; -+ spi0 = &ecspi1; -+ usb0 = &usbh1; -+ usb1 = &usbotg; -+ usdhc2 = &usdhc3; -+ }; -+ -+ chosen { -+ bootargs = "console=ttymxc1,115200"; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ led0: user1 { -+ label = "user1"; -+ gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ led1: user2 { -+ label = "user2"; -+ gpios = <&gpio4 10 0>; /* 106 -> MX6_PANLEDR */ -+ default-state = "off"; -+ }; -+ -+ led2: user3 { -+ label = "user3"; -+ gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ -+ default-state = "off"; -+ }; -+ }; -+ -+ memory { -+ reg = <0x10000000 0x40000000>; -+ }; -+ -+ pps { -+ compatible = "pps-gpio"; -+ gpios = <&gpio1 5 0>; -+ status = "okay"; -+ }; -+ -+ regulators { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ reg_1p0v: regulator@0 { -+ compatible = "regulator-fixed"; -+ reg = <0>; -+ regulator-name = "1P0V"; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1000000>; -+ regulator-always-on; -+ }; -+ -+ reg_3p3v: regulator@1 { -+ compatible = "regulator-fixed"; -+ reg = <1>; -+ regulator-name = "3P3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ reg_usb_h1_vbus: regulator@2 { -+ compatible = "regulator-fixed"; -+ reg = <2>; -+ regulator-name = "usb_h1_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ }; -+ -+ reg_usb_otg_vbus: regulator@3 { -+ compatible = "regulator-fixed"; -+ reg = <3>; -+ regulator-name = "usb_otg_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&gpio3 22 0>; -+ enable-active-high; -+ }; -+ }; -+ -+ sound { -+ compatible = "fsl,imx6q-ventana-sgtl5000", -+ "fsl,imx-audio-sgtl5000"; -+ model = "sgtl5000-audio"; -+ ssi-controller = <&ssi1>; -+ audio-codec = <&codec>; -+ audio-routing = -+ "MIC_IN", "Mic Jack", -+ "Mic Jack", "Mic Bias", -+ "Headphone Jack", "HP_OUT"; -+ mux-int-port = <1>; -+ mux-ext-port = <4>; -+ }; -+}; -+ -+&audmux { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_audmux>; -+ status = "okay"; -+}; -+ -+&ecspi1 { -+ fsl,spi-num-chipselects = <1>; -+ cs-gpios = <&gpio3 19 0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_ecspi1>; -+ status = "okay"; -+ -+ flash: m25p80@0 { -+ compatible = "sst,w25q256"; -+ spi-max-frequency = <30000000>; -+ reg = <0>; -+ }; -+}; -+ -+&fec { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_enet>; -+ phy-mode = "rgmii"; -+ phy-reset-gpios = <&gpio1 30 0>; -+ status = "okay"; -+}; -+ -+&i2c1 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1>; -+ status = "okay"; -+ -+ eeprom1: eeprom@50 { -+ compatible = "atmel,24c02"; -+ reg = <0x50>; -+ pagesize = <16>; -+ }; -+ -+ eeprom2: eeprom@51 { -+ compatible = "atmel,24c02"; -+ reg = <0x51>; -+ pagesize = <16>; -+ }; -+ -+ eeprom3: eeprom@52 { -+ compatible = "atmel,24c02"; -+ reg = <0x52>; -+ pagesize = <16>; -+ }; -+ -+ eeprom4: eeprom@53 { -+ compatible = "atmel,24c02"; -+ reg = <0x53>; -+ pagesize = <16>; -+ }; -+ -+ gpio: pca9555@23 { -+ compatible = "nxp,pca9555"; -+ reg = <0x23>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ hwmon: gsc@29 { -+ compatible = "gw,gsp"; -+ reg = <0x29>; -+ }; -+ -+ rtc: ds1672@68 { -+ compatible = "dallas,ds1672"; -+ reg = <0x68>; -+ }; -+}; -+ -+&i2c2 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+ -+ pmic: pfuze100@08 { -+ compatible = "fsl,pfuze100"; -+ reg = <0x08>; -+ -+ regulators { -+ sw1a_reg: sw1ab { -+ regulator-min-microvolt = <300000>; -+ regulator-max-microvolt = <1875000>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-ramp-delay = <6250>; -+ }; -+ -+ sw1c_reg: sw1c { -+ regulator-min-microvolt = <300000>; -+ regulator-max-microvolt = <1875000>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-ramp-delay = <6250>; -+ }; -+ -+ sw2_reg: sw2 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <3950000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ sw3a_reg: sw3a { -+ regulator-min-microvolt = <400000>; -+ regulator-max-microvolt = <1975000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ sw3b_reg: sw3b { -+ regulator-min-microvolt = <400000>; -+ regulator-max-microvolt = <1975000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ sw4_reg: sw4 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ swbst_reg: swbst { -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5150000>; -+ }; -+ -+ snvs_reg: vsnvs { -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ vref_reg: vrefddr { -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ vgen1_reg: vgen1 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1550000>; -+ }; -+ -+ vgen2_reg: vgen2 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1550000>; -+ }; -+ -+ vgen3_reg: vgen3 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ vgen4_reg: vgen4 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ vgen5_reg: vgen5 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ vgen6_reg: vgen6 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ }; -+ }; -+ -+ pciswitch: pex8609@3f { -+ compatible = "plx,pex8609"; -+ reg = <0x3f>; -+ }; -+ -+ pciclkgen: si52147@6b { -+ compatible = "sil,si52147"; -+ reg = <0x6b>; -+ }; -+}; -+ -+&i2c3 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+ -+ accelerometer: mma8450@1c { -+ compatible = "fsl,mma8450"; -+ reg = <0x1c>; -+ }; -+ -+ codec: sgtl5000@0a { -+ compatible = "fsl,sgtl5000"; -+ reg = <0x0a>; -+ clocks = <&clks 201>; -+ VDDA-supply = <&sw4_reg>; -+ VDDIO-supply = <®_3p3v>; -+ }; -+ -+ hdmiin: adv7611@4c { -+ compatible = "adi,adv7611"; -+ reg = <0x4c>; -+ }; -+ -+ touchscreen: egalax_ts@04 { -+ compatible = "eeti,egalax_ts"; -+ reg = <0x04>; -+ interrupt-parent = <&gpio7>; -+ interrupts = <12 2>; /* gpio7_12 active low */ -+ wakeup-gpios = <&gpio7 12 0>; -+ }; -+ -+ videoout: adv7393@2a { -+ compatible = "adi,adv7393"; -+ reg = <0x2a>; -+ }; -+ -+ videoin: adv7180@20 { -+ compatible = "adi,adv7180"; -+ reg = <0x20>; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ imx6q-gw5400-a { -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ -+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */ -+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ -+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ -+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ -+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* GPS_PPS */ -+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ -+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ -+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* user2 led */ -+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ -+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */ -+ MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */ -+ >; -+ }; -+ -+ pinctrl_audmux: audmuxgrp { -+ fsl,pins = < -+ MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 -+ MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 -+ MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 -+ MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 -+ >; -+ }; -+ -+ pinctrl_ecspi1: ecspi1grp { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 -+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 -+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 -+ >; -+ }; -+ -+ pinctrl_enet: enetgrp { -+ fsl,pins = < -+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 -+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 -+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 -+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 -+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 -+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 -+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 -+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 -+ >; -+ }; -+ -+ pinctrl_i2c1: i2c1grp { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 -+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 -+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 -+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_uart2: uart2grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_uart5: uart5grp { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_usbotg: usbotggrp { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 -+ >; -+ }; -+ -+ pinctrl_usdhc3: usdhc3grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 -+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 -+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 -+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 -+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 -+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 -+ >; -+ }; -+ }; -+}; -+ -+&ldb { -+ status = "okay"; -+}; -+ -+&pcie { -+ reset-gpio = <&gpio1 29 0>; -+ status = "okay"; -+ -+ eth1: sky2@8 { /* MAC/PHY on bus 8 */ -+ compatible = "marvell,sky2"; -+ }; -+}; -+ -+&ssi1 { -+ fsl,mode = "i2s-slave"; -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart2>; -+ status = "okay"; -+}; -+ -+&uart5 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart5>; -+ status = "okay"; -+}; -+ -+&usbotg { -+ vbus-supply = <®_usb_otg_vbus>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usbotg>; -+ disable-over-current; -+ status = "okay"; -+}; -+ -+&usbh1 { -+ vbus-supply = <®_usb_h1_vbus>; -+ status = "okay"; -+}; -+ -+&usdhc3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usdhc3>; -+ cd-gpios = <&gpio7 0 0>; -+ vmmc-supply = <®_3p3v>; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/imx6q-gw54xx.dts -@@ -0,0 +1,23 @@ -+/* -+ * Copyright 2013 Gateworks Corporation -+ * -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/dts-v1/; -+#include "imx6q.dtsi" -+#include "imx6qdl-gw54xx.dtsi" -+ -+/ { -+ model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX"; -+ compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q"; -+}; -+ -+&sata { -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi -@@ -0,0 +1,374 @@ -+/* -+ * Copyright 2013 Gateworks Corporation -+ * -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/ { -+ /* these are used by bootloader for disabling nodes */ -+ aliases { -+ can0 = &can1; -+ ethernet0 = &fec; -+ led0 = &led0; -+ led1 = &led1; -+ nand = &gpmi; -+ usb0 = &usbh1; -+ usb1 = &usbotg; -+ }; -+ -+ chosen { -+ bootargs = "console=ttymxc1,115200"; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ led0: user1 { -+ label = "user1"; -+ gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ led1: user2 { -+ label = "user2"; -+ gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ -+ default-state = "off"; -+ }; -+ }; -+ -+ memory { -+ reg = <0x10000000 0x20000000>; -+ }; -+ -+ pps { -+ compatible = "pps-gpio"; -+ gpios = <&gpio1 26 0>; -+ status = "okay"; -+ }; -+ -+ regulators { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ reg_3p3v: regulator@0 { -+ compatible = "regulator-fixed"; -+ reg = <0>; -+ regulator-name = "3P3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ reg_5p0v: regulator@1 { -+ compatible = "regulator-fixed"; -+ reg = <1>; -+ regulator-name = "5P0V"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ }; -+ -+ reg_usb_otg_vbus: regulator@2 { -+ compatible = "regulator-fixed"; -+ reg = <2>; -+ regulator-name = "usb_otg_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&gpio3 22 0>; -+ enable-active-high; -+ }; -+ }; -+}; -+ -+&fec { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_enet>; -+ phy-mode = "rgmii"; -+ phy-reset-gpios = <&gpio1 30 0>; -+ status = "okay"; -+}; -+ -+&gpmi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpmi_nand>; -+ status = "okay"; -+}; -+ -+&i2c1 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1>; -+ status = "okay"; -+ -+ eeprom1: eeprom@50 { -+ compatible = "atmel,24c02"; -+ reg = <0x50>; -+ pagesize = <16>; -+ }; -+ -+ eeprom2: eeprom@51 { -+ compatible = "atmel,24c02"; -+ reg = <0x51>; -+ pagesize = <16>; -+ }; -+ -+ eeprom3: eeprom@52 { -+ compatible = "atmel,24c02"; -+ reg = <0x52>; -+ pagesize = <16>; -+ }; -+ -+ eeprom4: eeprom@53 { -+ compatible = "atmel,24c02"; -+ reg = <0x53>; -+ pagesize = <16>; -+ }; -+ -+ gpio: pca9555@23 { -+ compatible = "nxp,pca9555"; -+ reg = <0x23>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ hwmon: gsc@29 { -+ compatible = "gw,gsp"; -+ reg = <0x29>; -+ }; -+ -+ rtc: ds1672@68 { -+ compatible = "dallas,ds1672"; -+ reg = <0x68>; -+ }; -+}; -+ -+&i2c2 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+ -+ pmic: ltc3676@3c { -+ compatible = "ltc,ltc3676"; -+ reg = <0x3c>; -+ -+ regulators { -+ sw1_reg: ltc3676__sw1 { -+ regulator-min-microvolt = <1175000>; -+ regulator-max-microvolt = <1175000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ sw2_reg: ltc3676__sw2 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ sw3_reg: ltc3676__sw3 { -+ regulator-min-microvolt = <1175000>; -+ regulator-max-microvolt = <1175000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ sw4_reg: ltc3676__sw4 { -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo2_reg: ltc3676__ldo2 { -+ regulator-min-microvolt = <2500000>; -+ regulator-max-microvolt = <2500000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo4_reg: ltc3676__ldo4 { -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c3 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+ -+ videoin: adv7180@20 { -+ compatible = "adi,adv7180"; -+ reg = <0x20>; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ imx6qdl-gw51xx { -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */ -+ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */ -+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ -+ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ -+ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */ -+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x80000000 /* PCIE_RST# */ -+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ -+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ -+ >; -+ }; -+ -+ pinctrl_enet: enetgrp { -+ fsl,pins = < -+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 -+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 -+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 -+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 -+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 -+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 -+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 -+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 -+ >; -+ }; -+ -+ pinctrl_gpmi_nand: gpminandgrp { -+ fsl,pins = < -+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 -+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 -+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 -+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 -+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 -+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 -+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 -+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 -+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 -+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 -+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 -+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 -+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 -+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 -+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 -+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 -+ >; -+ }; -+ -+ pinctrl_i2c1: i2c1grp { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 -+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 -+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 -+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_uart2: uart2grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_uart3: uart3grp { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_uart5: uart5grp { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_usbotg: usbotggrp { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 -+ >; -+ }; -+ }; -+}; -+ -+&pcie { -+ reset-gpio = <&gpio1 0 0>; -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart2>; -+ status = "okay"; -+}; -+ -+&uart3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart3>; -+ status = "okay"; -+}; -+ -+&uart5 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart5>; -+ status = "okay"; -+}; -+ -+&usbotg { -+ vbus-supply = <®_usb_otg_vbus>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usbotg>; -+ disable-over-current; -+ status = "okay"; -+}; -+ -+&usbh1 { -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi -@@ -0,0 +1,528 @@ -+/* -+ * Copyright 2013 Gateworks Corporation -+ * -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/ { -+ /* these are used by bootloader for disabling nodes */ -+ aliases { -+ ethernet0 = &fec; -+ led0 = &led0; -+ led1 = &led1; -+ led2 = &led2; -+ nand = &gpmi; -+ ssi0 = &ssi1; -+ usb0 = &usbh1; -+ usb1 = &usbotg; -+ usdhc2 = &usdhc3; -+ }; -+ -+ chosen { -+ bootargs = "console=ttymxc1,115200"; -+ }; -+ -+ backlight { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm4 0 5000000>; -+ brightness-levels = <0 4 8 16 32 64 128 255>; -+ default-brightness-level = <7>; -+ status = "okay"; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ led0: user1 { -+ label = "user1"; -+ gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ led1: user2 { -+ label = "user2"; -+ gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ -+ default-state = "off"; -+ }; -+ -+ led2: user3 { -+ label = "user3"; -+ gpios = <&gpio4 15 1>; /* 111 - MX6_LOCLED# */ -+ default-state = "off"; -+ }; -+ }; -+ -+ memory { -+ reg = <0x10000000 0x20000000>; -+ }; -+ -+ pps { -+ compatible = "pps-gpio"; -+ gpios = <&gpio1 26 0>; -+ status = "okay"; -+ }; -+ -+ regulators { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ reg_1p0v: regulator@0 { -+ compatible = "regulator-fixed"; -+ reg = <0>; -+ regulator-name = "1P0V"; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1000000>; -+ regulator-always-on; -+ }; -+ -+ /* remove this fixed regulator once ltc3676__sw2 driver available */ -+ reg_1p8v: regulator@1 { -+ compatible = "regulator-fixed"; -+ reg = <1>; -+ regulator-name = "1P8V"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ }; -+ -+ reg_3p3v: regulator@2 { -+ compatible = "regulator-fixed"; -+ reg = <2>; -+ regulator-name = "3P3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ reg_5p0v: regulator@3 { -+ compatible = "regulator-fixed"; -+ reg = <3>; -+ regulator-name = "5P0V"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ }; -+ -+ reg_usb_otg_vbus: regulator@4 { -+ compatible = "regulator-fixed"; -+ reg = <4>; -+ regulator-name = "usb_otg_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&gpio3 22 0>; -+ enable-active-high; -+ }; -+ }; -+ -+ sound { -+ compatible = "fsl,imx6q-ventana-sgtl5000", -+ "fsl,imx-audio-sgtl5000"; -+ model = "sgtl5000-audio"; -+ ssi-controller = <&ssi1>; -+ audio-codec = <&codec>; -+ audio-routing = -+ "MIC_IN", "Mic Jack", -+ "Mic Jack", "Mic Bias", -+ "Headphone Jack", "HP_OUT"; -+ mux-int-port = <1>; -+ mux-ext-port = <4>; -+ }; -+}; -+ -+&audmux { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_audmux>; -+ status = "okay"; -+}; -+ -+&fec { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_enet>; -+ phy-mode = "rgmii"; -+ phy-reset-gpios = <&gpio1 30 0>; -+ status = "okay"; -+}; -+ -+&gpmi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpmi_nand>; -+ status = "okay"; -+}; -+ -+&i2c1 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1>; -+ status = "okay"; -+ -+ eeprom1: eeprom@50 { -+ compatible = "atmel,24c02"; -+ reg = <0x50>; -+ pagesize = <16>; -+ }; -+ -+ eeprom2: eeprom@51 { -+ compatible = "atmel,24c02"; -+ reg = <0x51>; -+ pagesize = <16>; -+ }; -+ -+ eeprom3: eeprom@52 { -+ compatible = "atmel,24c02"; -+ reg = <0x52>; -+ pagesize = <16>; -+ }; -+ -+ eeprom4: eeprom@53 { -+ compatible = "atmel,24c02"; -+ reg = <0x53>; -+ pagesize = <16>; -+ }; -+ -+ gpio: pca9555@23 { -+ compatible = "nxp,pca9555"; -+ reg = <0x23>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ hwmon: gsc@29 { -+ compatible = "gw,gsp"; -+ reg = <0x29>; -+ }; -+ -+ rtc: ds1672@68 { -+ compatible = "dallas,ds1672"; -+ reg = <0x68>; -+ }; -+}; -+ -+&i2c2 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+ -+ pciswitch: pex8609@3f { -+ compatible = "plx,pex8609"; -+ reg = <0x3f>; -+ }; -+ -+ pmic: ltc3676@3c { -+ compatible = "ltc,ltc3676"; -+ reg = <0x3c>; -+ -+ regulators { -+ sw1_reg: ltc3676__sw1 { -+ regulator-min-microvolt = <1175000>; -+ regulator-max-microvolt = <1175000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ sw2_reg: ltc3676__sw2 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ sw3_reg: ltc3676__sw3 { -+ regulator-min-microvolt = <1175000>; -+ regulator-max-microvolt = <1175000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ sw4_reg: ltc3676__sw4 { -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo2_reg: ltc3676__ldo2 { -+ regulator-min-microvolt = <2500000>; -+ regulator-max-microvolt = <2500000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo3_reg: ltc3676__ldo3 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo4_reg: ltc3676__ldo4 { -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c3 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+ -+ accelerometer: fxos8700@1e { -+ compatible = "fsl,fxos8700"; -+ reg = <0x13>; -+ }; -+ -+ codec: sgtl5000@0a { -+ compatible = "fsl,sgtl5000"; -+ reg = <0x0a>; -+ clocks = <&clks 201>; -+ VDDA-supply = <®_1p8v>; -+ VDDIO-supply = <®_3p3v>; -+ }; -+ -+ touchscreen: egalax_ts@04 { -+ compatible = "eeti,egalax_ts"; -+ reg = <0x04>; -+ interrupt-parent = <&gpio7>; -+ interrupts = <12 2>; /* gpio7_12 active low */ -+ wakeup-gpios = <&gpio7 12 0>; -+ }; -+ -+ videoin: adv7180@20 { -+ compatible = "adi,adv7180"; -+ reg = <0x20>; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ imx6qdl-gw52xx { -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */ -+ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */ -+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ -+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x80000000 /* VIDDEC_PDN# */ -+ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */ -+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE_RST# */ -+ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_PWDN */ -+ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ -+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ -+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USB_SEL_PCI */ -+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ -+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ -+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ -+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ -+ MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* LVDS_TCH# */ -+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_CD# */ -+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000 /* UART2_EN# */ -+ >; -+ }; -+ -+ pinctrl_audmux: audmuxgrp { -+ fsl,pins = < -+ MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 -+ MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 -+ MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 -+ MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 -+ >; -+ }; -+ -+ pinctrl_enet: enetgrp { -+ fsl,pins = < -+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 -+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 -+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 -+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 -+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 -+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 -+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 -+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 -+ >; -+ }; -+ -+ pinctrl_gpmi_nand: gpminandgrp { -+ fsl,pins = < -+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 -+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 -+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 -+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 -+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 -+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 -+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 -+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 -+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 -+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 -+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 -+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 -+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 -+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 -+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 -+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 -+ >; -+ }; -+ -+ pinctrl_i2c1: i2c1grp { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 -+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 -+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 -+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_pwm4: pwm4grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_uart2: uart2grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_uart5: uart5grp { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_usbotg: usbotggrp { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 -+ >; -+ }; -+ -+ pinctrl_usdhc3: usdhc3grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 -+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 -+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 -+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 -+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 -+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 -+ >; -+ }; -+ }; -+}; -+ -+&ldb { -+ status = "okay"; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "spwg"; -+ fsl,data-width = <18>; -+ status = "okay"; -+ -+ display-timings { -+ native-mode = <&timing0>; -+ timing0: hsd100pxn1 { -+ clock-frequency = <65000000>; -+ hactive = <1024>; -+ vactive = <768>; -+ hback-porch = <220>; -+ hfront-porch = <40>; -+ vback-porch = <21>; -+ vfront-porch = <7>; -+ hsync-len = <60>; -+ vsync-len = <10>; -+ }; -+ }; -+ }; -+}; -+ -+&pcie { -+ reset-gpio = <&gpio1 29 0>; -+ status = "okay"; -+}; -+ -+&pwm4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm4>; -+ status = "okay"; -+}; -+ -+&ssi1 { -+ fsl,mode = "i2s-slave"; -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart2>; -+ status = "okay"; -+}; -+ -+&uart5 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart5>; -+ status = "okay"; -+}; -+ -+&usbotg { -+ vbus-supply = <®_usb_otg_vbus>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usbotg>; -+ disable-over-current; -+ status = "okay"; -+}; -+ -+&usbh1 { -+ status = "okay"; -+}; -+ -+&usdhc3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usdhc3>; -+ cd-gpios = <&gpio7 0 0>; -+ vmmc-supply = <®_3p3v>; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi -@@ -0,0 +1,573 @@ -+/* -+ * Copyright 2013 Gateworks Corporation -+ * -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/ { -+ /* these are used by bootloader for disabling nodes */ -+ aliases { -+ can0 = &can1; -+ ethernet0 = &fec; -+ ethernet1 = ð1; -+ led0 = &led0; -+ led1 = &led1; -+ led2 = &led2; -+ nand = &gpmi; -+ sky2 = ð1; -+ ssi0 = &ssi1; -+ usb0 = &usbh1; -+ usb1 = &usbotg; -+ usdhc2 = &usdhc3; -+ }; -+ -+ chosen { -+ bootargs = "console=ttymxc1,115200"; -+ }; -+ -+ backlight { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm4 0 5000000>; -+ brightness-levels = <0 4 8 16 32 64 128 255>; -+ default-brightness-level = <7>; -+ status = "okay"; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ led0: user1 { -+ label = "user1"; -+ gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ led1: user2 { -+ label = "user2"; -+ gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ -+ default-state = "off"; -+ }; -+ -+ led2: user3 { -+ label = "user3"; -+ gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ -+ default-state = "off"; -+ }; -+ }; -+ -+ memory { -+ reg = <0x10000000 0x40000000>; -+ }; -+ -+ pps { -+ compatible = "pps-gpio"; -+ gpios = <&gpio1 26 0>; -+ status = "okay"; -+ }; -+ -+ regulators { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ reg_1p0v: regulator@0 { -+ compatible = "regulator-fixed"; -+ reg = <0>; -+ regulator-name = "1P0V"; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1000000>; -+ regulator-always-on; -+ }; -+ -+ /* remove when pmic 1p8 regulator available */ -+ reg_1p8v: regulator@1 { -+ compatible = "regulator-fixed"; -+ reg = <1>; -+ regulator-name = "1P8V"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ }; -+ -+ reg_3p3v: regulator@2 { -+ compatible = "regulator-fixed"; -+ reg = <2>; -+ regulator-name = "3P3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ reg_usb_h1_vbus: regulator@3 { -+ compatible = "regulator-fixed"; -+ reg = <3>; -+ regulator-name = "usb_h1_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ }; -+ -+ reg_usb_otg_vbus: regulator@4 { -+ compatible = "regulator-fixed"; -+ reg = <4>; -+ regulator-name = "usb_otg_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&gpio3 22 0>; -+ enable-active-high; -+ }; -+ }; -+ -+ sound { -+ compatible = "fsl,imx6q-ventana-sgtl5000", -+ "fsl,imx-audio-sgtl5000"; -+ model = "sgtl5000-audio"; -+ ssi-controller = <&ssi1>; -+ audio-codec = <&codec>; -+ audio-routing = -+ "MIC_IN", "Mic Jack", -+ "Mic Jack", "Mic Bias", -+ "Headphone Jack", "HP_OUT"; -+ mux-int-port = <1>; -+ mux-ext-port = <4>; -+ }; -+}; -+ -+&audmux { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_audmux>; -+ status = "okay"; -+}; -+ -+&can1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan1>; -+ status = "okay"; -+}; -+ -+&fec { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_enet>; -+ phy-mode = "rgmii"; -+ phy-reset-gpios = <&gpio1 30 0>; -+ status = "okay"; -+}; -+ -+&gpmi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpmi_nand>; -+ status = "okay"; -+}; -+ -+&i2c1 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1>; -+ status = "okay"; -+ -+ eeprom1: eeprom@50 { -+ compatible = "atmel,24c02"; -+ reg = <0x50>; -+ pagesize = <16>; -+ }; -+ -+ eeprom2: eeprom@51 { -+ compatible = "atmel,24c02"; -+ reg = <0x51>; -+ pagesize = <16>; -+ }; -+ -+ eeprom3: eeprom@52 { -+ compatible = "atmel,24c02"; -+ reg = <0x52>; -+ pagesize = <16>; -+ }; -+ -+ eeprom4: eeprom@53 { -+ compatible = "atmel,24c02"; -+ reg = <0x53>; -+ pagesize = <16>; -+ }; -+ -+ gpio: pca9555@23 { -+ compatible = "nxp,pca9555"; -+ reg = <0x23>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ hwmon: gsc@29 { -+ compatible = "gw,gsp"; -+ reg = <0x29>; -+ }; -+ -+ rtc: ds1672@68 { -+ compatible = "dallas,ds1672"; -+ reg = <0x68>; -+ }; -+}; -+ -+&i2c2 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+ -+ pciclkgen: si53156@6b { -+ compatible = "sil,si53156"; -+ reg = <0x6b>; -+ }; -+ -+ pciswitch: pex8606@3f { -+ compatible = "plx,pex8606"; -+ reg = <0x3f>; -+ }; -+ -+ pmic: ltc3676@3c { -+ compatible = "ltc,ltc3676"; -+ reg = <0x3c>; -+ -+ regulators { -+ /* VDD_SOC */ -+ sw1_reg: ltc3676__sw1 { -+ regulator-min-microvolt = <1175000>; -+ regulator-max-microvolt = <1175000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ /* VDD_1P8 */ -+ sw2_reg: ltc3676__sw2 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ /* VDD_ARM */ -+ sw3_reg: ltc3676__sw3 { -+ regulator-min-microvolt = <1175000>; -+ regulator-max-microvolt = <1175000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ /* VDD_DDR */ -+ sw4_reg: ltc3676__sw4 { -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ /* VDD_2P5 */ -+ ldo2_reg: ltc3676__ldo2 { -+ regulator-min-microvolt = <2500000>; -+ regulator-max-microvolt = <2500000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ /* VDD_1P8 */ -+ ldo3_reg: ltc3676__ldo3 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ /* VDD_HIGH */ -+ ldo4_reg: ltc3676__ldo4 { -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c3 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+ -+ accelerometer: fxos8700@1e { -+ compatible = "fsl,fxos8700"; -+ reg = <0x1e>; -+ }; -+ -+ codec: sgtl5000@0a { -+ compatible = "fsl,sgtl5000"; -+ reg = <0x0a>; -+ clocks = <&clks 201>; -+ VDDA-supply = <®_1p8v>; -+ VDDIO-supply = <®_3p3v>; -+ }; -+ -+ hdmiin: adv7611@4c { -+ compatible = "adi,adv7611"; -+ reg = <0x4c>; -+ }; -+ -+ touchscreen: egalax_ts@04 { -+ compatible = "eeti,egalax_ts"; -+ reg = <0x04>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <11 2>; /* gpio1_11 active low */ -+ wakeup-gpios = <&gpio1 11 0>; -+ }; -+ -+ videoout: adv7393@2a { -+ compatible = "adi,adv7393"; -+ reg = <0x2a>; -+ }; -+ -+ videoin: adv7180@20 { -+ compatible = "adi,adv7180"; -+ reg = <0x20>; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ imx6qdl-gw53xx { -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* PCIE6EXP_DIO0 */ -+ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* PCIE6EXP_DIO1 */ -+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ -+ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_SHDN */ -+ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ -+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ -+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ -+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ -+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */ -+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000 /* PMIC_IRQ# */ -+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 /* HUB_RST# */ -+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIE_WDIS# */ -+ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* ACCEL_IRQ# */ -+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ -+ MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x80000000 /* USBOTG_OC# */ -+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ -+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ -+ MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* TOUCH_IRQ# */ -+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_DET# */ -+ >; -+ }; -+ -+ pinctrl_audmux: audmuxgrp { -+ fsl,pins = < -+ MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 -+ MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 -+ MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 -+ MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 -+ >; -+ }; -+ -+ pinctrl_enet: enetgrp { -+ fsl,pins = < -+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 -+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 -+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 -+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 -+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 -+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 -+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 -+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 -+ >; -+ }; -+ -+ pinctrl_flexcan1: flexcan1grp { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 -+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 -+ >; -+ }; -+ -+ pinctrl_gpmi_nand: gpminandgrp { -+ fsl,pins = < -+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 -+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 -+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 -+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 -+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 -+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 -+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 -+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 -+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 -+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 -+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 -+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 -+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 -+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 -+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 -+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 -+ >; -+ }; -+ -+ pinctrl_i2c1: i2c1grp { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 -+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 -+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 -+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_pwm4: pwm4grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_uart2: uart2grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_uart5: uart5grp { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_usbotg: usbotggrp { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 -+ >; -+ }; -+ -+ pinctrl_usdhc3: usdhc3grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 -+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 -+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 -+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 -+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 -+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 -+ >; -+ }; -+ }; -+}; -+ -+&ldb { -+ status = "okay"; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "spwg"; -+ fsl,data-width = <18>; -+ status = "okay"; -+ -+ display-timings { -+ native-mode = <&timing0>; -+ timing0: hsd100pxn1 { -+ clock-frequency = <65000000>; -+ hactive = <1024>; -+ vactive = <768>; -+ hback-porch = <220>; -+ hfront-porch = <40>; -+ vback-porch = <21>; -+ vfront-porch = <7>; -+ hsync-len = <60>; -+ vsync-len = <10>; -+ }; -+ }; -+ }; -+}; -+ -+&pcie { -+ reset-gpio = <&gpio1 29 0>; -+ status = "okay"; -+ -+ eth1: sky2@8 { /* MAC/PHY on bus 8 */ -+ compatible = "marvell,sky2"; -+ }; -+}; -+ -+&pwm4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm4>; -+ status = "okay"; -+}; -+ -+&ssi1 { -+ fsl,mode = "i2s-slave"; -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart2>; -+ status = "okay"; -+}; -+ -+&uart5 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart5>; -+ status = "okay"; -+}; -+ -+&usbotg { -+ vbus-supply = <®_usb_otg_vbus>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usbotg>; -+ disable-over-current; -+ status = "okay"; -+}; -+ -+&usbh1 { -+ vbus-supply = <®_usb_h1_vbus>; -+ status = "okay"; -+}; -+ -+&usdhc3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usdhc3>; -+ cd-gpios = <&gpio7 0 0>; -+ vmmc-supply = <®_3p3v>; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -@@ -0,0 +1,600 @@ -+/* -+ * Copyright 2013 Gateworks Corporation -+ * -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/ { -+ /* these are used by bootloader for disabling nodes */ -+ aliases { -+ can0 = &can1; -+ ethernet0 = &fec; -+ ethernet1 = ð1; -+ led0 = &led0; -+ led1 = &led1; -+ led2 = &led2; -+ nand = &gpmi; -+ sky2 = ð1; -+ ssi0 = &ssi1; -+ usb0 = &usbh1; -+ usb1 = &usbotg; -+ usdhc2 = &usdhc3; -+ }; -+ -+ chosen { -+ bootargs = "console=ttymxc1,115200"; -+ }; -+ -+ backlight { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm4 0 5000000>; -+ brightness-levels = <0 4 8 16 32 64 128 255>; -+ default-brightness-level = <7>; -+ status = "okay"; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ led0: user1 { -+ label = "user1"; -+ gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ led1: user2 { -+ label = "user2"; -+ gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ -+ default-state = "off"; -+ }; -+ -+ led2: user3 { -+ label = "user3"; -+ gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ -+ default-state = "off"; -+ }; -+ }; -+ -+ memory { -+ reg = <0x10000000 0x40000000>; -+ }; -+ -+ pps { -+ compatible = "pps-gpio"; -+ gpios = <&gpio1 26 0>; -+ status = "okay"; -+ }; -+ -+ regulators { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ reg_1p0v: regulator@0 { -+ compatible = "regulator-fixed"; -+ reg = <0>; -+ regulator-name = "1P0V"; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1000000>; -+ regulator-always-on; -+ }; -+ -+ reg_3p3v: regulator@1 { -+ compatible = "regulator-fixed"; -+ reg = <1>; -+ regulator-name = "3P3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ reg_usb_h1_vbus: regulator@2 { -+ compatible = "regulator-fixed"; -+ reg = <2>; -+ regulator-name = "usb_h1_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ }; -+ -+ reg_usb_otg_vbus: regulator@3 { -+ compatible = "regulator-fixed"; -+ reg = <3>; -+ regulator-name = "usb_otg_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&gpio3 22 0>; -+ enable-active-high; -+ }; -+ }; -+ -+ sound { -+ compatible = "fsl,imx6q-ventana-sgtl5000", -+ "fsl,imx-audio-sgtl5000"; -+ model = "sgtl5000-audio"; -+ ssi-controller = <&ssi1>; -+ audio-codec = <&codec>; -+ audio-routing = -+ "MIC_IN", "Mic Jack", -+ "Mic Jack", "Mic Bias", -+ "Headphone Jack", "HP_OUT"; -+ mux-int-port = <1>; -+ mux-ext-port = <4>; -+ }; -+}; -+ -+&audmux { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */ -+ status = "okay"; -+}; -+ -+&can1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan1>; -+ status = "okay"; -+}; -+ -+&fec { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_enet>; -+ phy-mode = "rgmii"; -+ phy-reset-gpios = <&gpio1 30 0>; -+ status = "okay"; -+}; -+ -+&gpmi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpmi_nand>; -+ status = "okay"; -+}; -+ -+&i2c1 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1>; -+ status = "okay"; -+ -+ eeprom1: eeprom@50 { -+ compatible = "atmel,24c02"; -+ reg = <0x50>; -+ pagesize = <16>; -+ }; -+ -+ eeprom2: eeprom@51 { -+ compatible = "atmel,24c02"; -+ reg = <0x51>; -+ pagesize = <16>; -+ }; -+ -+ eeprom3: eeprom@52 { -+ compatible = "atmel,24c02"; -+ reg = <0x52>; -+ pagesize = <16>; -+ }; -+ -+ eeprom4: eeprom@53 { -+ compatible = "atmel,24c02"; -+ reg = <0x53>; -+ pagesize = <16>; -+ }; -+ -+ gpio: pca9555@23 { -+ compatible = "nxp,pca9555"; -+ reg = <0x23>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ hwmon: gsc@29 { -+ compatible = "gw,gsp"; -+ reg = <0x29>; -+ }; -+ -+ rtc: ds1672@68 { -+ compatible = "dallas,ds1672"; -+ reg = <0x68>; -+ }; -+}; -+ -+&i2c2 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+ -+ pmic: pfuze100@08 { -+ compatible = "fsl,pfuze100"; -+ reg = <0x08>; -+ -+ regulators { -+ sw1a_reg: sw1ab { -+ regulator-min-microvolt = <300000>; -+ regulator-max-microvolt = <1875000>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-ramp-delay = <6250>; -+ }; -+ -+ sw1c_reg: sw1c { -+ regulator-min-microvolt = <300000>; -+ regulator-max-microvolt = <1875000>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-ramp-delay = <6250>; -+ }; -+ -+ sw2_reg: sw2 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <3950000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ sw3a_reg: sw3a { -+ regulator-min-microvolt = <400000>; -+ regulator-max-microvolt = <1975000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ sw3b_reg: sw3b { -+ regulator-min-microvolt = <400000>; -+ regulator-max-microvolt = <1975000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ sw4_reg: sw4 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ swbst_reg: swbst { -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5150000>; -+ }; -+ -+ snvs_reg: vsnvs { -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ vref_reg: vrefddr { -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ vgen1_reg: vgen1 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1550000>; -+ }; -+ -+ vgen2_reg: vgen2 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1550000>; -+ }; -+ -+ vgen3_reg: vgen3 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ vgen4_reg: vgen4 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ vgen5_reg: vgen5 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ vgen6_reg: vgen6 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ }; -+ }; -+ -+ pciswitch: pex8609@3f { -+ compatible = "plx,pex8609"; -+ reg = <0x3f>; -+ }; -+ -+ pciclkgen: si52147@6b { -+ compatible = "sil,si52147"; -+ reg = <0x6b>; -+ }; -+}; -+ -+&i2c3 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+ -+ accelerometer: fxos8700@1e { -+ compatible = "fsl,fxos8700"; -+ reg = <0x1e>; -+ }; -+ -+ codec: sgtl5000@0a { -+ compatible = "fsl,sgtl5000"; -+ reg = <0x0a>; -+ clocks = <&clks 201>; -+ VDDA-supply = <&sw4_reg>; -+ VDDIO-supply = <®_3p3v>; -+ }; -+ -+ hdmiin: adv7611@4c { -+ compatible = "adi,adv7611"; -+ reg = <0x4c>; -+ }; -+ -+ touchscreen: egalax_ts@04 { -+ compatible = "eeti,egalax_ts"; -+ reg = <0x04>; -+ interrupt-parent = <&gpio7>; -+ interrupts = <12 2>; /* gpio7_12 active low */ -+ wakeup-gpios = <&gpio7 12 0>; -+ }; -+ -+ videoout: adv7393@2a { -+ compatible = "adi,adv7393"; -+ reg = <0x2a>; -+ }; -+ -+ videoin: adv7180@20 { -+ compatible = "adi,adv7180"; -+ reg = <0x20>; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ imx6qdl-gw54xx { -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ -+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */ -+ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ -+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ -+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ -+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ -+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */ -+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ -+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ -+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ -+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ -+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */ -+ MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */ -+ >; -+ }; -+ -+ pinctrl_audmux: audmuxgrp { -+ fsl,pins = < -+ MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 -+ MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 -+ MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 -+ MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 -+ >; -+ }; -+ -+ pinctrl_enet: enetgrp { -+ fsl,pins = < -+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 -+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 -+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 -+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 -+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 -+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 -+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 -+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 -+ >; -+ }; -+ -+ pinctrl_flexcan1: flexcan1grp { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 -+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 -+ >; -+ }; -+ -+ pinctrl_gpmi_nand: gpminandgrp { -+ fsl,pins = < -+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 -+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 -+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 -+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 -+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 -+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 -+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 -+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 -+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 -+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 -+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 -+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 -+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 -+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 -+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 -+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 -+ >; -+ }; -+ -+ pinctrl_i2c1: i2c1grp { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 -+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 -+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 -+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_pwm4: pwm4grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_uart1: uart1grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_uart2: uart2grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_uart5: uart5grp { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_usbotg: usbotggrp { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 -+ >; -+ }; -+ -+ pinctrl_usdhc3: usdhc3grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 -+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 -+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 -+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 -+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 -+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 -+ >; -+ }; -+ }; -+}; -+ -+&ldb { -+ status = "okay"; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "spwg"; -+ fsl,data-width = <18>; -+ status = "okay"; -+ -+ display-timings { -+ native-mode = <&timing0>; -+ timing0: hsd100pxn1 { -+ clock-frequency = <65000000>; -+ hactive = <1024>; -+ vactive = <768>; -+ hback-porch = <220>; -+ hfront-porch = <40>; -+ vback-porch = <21>; -+ vfront-porch = <7>; -+ hsync-len = <60>; -+ vsync-len = <10>; -+ }; -+ }; -+ }; -+}; -+ -+&pcie { -+ reset-gpio = <&gpio1 29 0>; -+ status = "okay"; -+ -+ eth1: sky2@8 { /* MAC/PHY on bus 8 */ -+ compatible = "marvell,sky2"; -+ }; -+}; -+ -+&pwm4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm4>; -+ status = "okay"; -+}; -+ -+&ssi1 { -+ fsl,mode = "i2s-slave"; -+ status = "okay"; -+}; -+ -+&ssi2 { -+ fsl,mode = "i2s-slave"; -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart1>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart2>; -+ status = "okay"; -+}; -+ -+&uart5 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart5>; -+ status = "okay"; -+}; -+ -+&usbotg { -+ vbus-supply = <®_usb_otg_vbus>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usbotg>; -+ disable-over-current; -+ status = "okay"; -+}; -+ -+&usbh1 { -+ vbus-supply = <®_usb_h1_vbus>; -+ status = "okay"; -+}; -+ -+&usdhc3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usdhc3>; -+ cd-gpios = <&gpio7 0 0>; -+ vmmc-supply = <®_3p3v>; -+ status = "okay"; -+}; diff --git a/target/linux/imx6/patches-3.14/0004-ARM-dts-imx6dl-enable-cpufreq-support.patch b/target/linux/imx6/patches-3.14/0004-ARM-dts-imx6dl-enable-cpufreq-support.patch deleted file mode 100644 index 6f07cdd277..0000000000 --- a/target/linux/imx6/patches-3.14/0004-ARM-dts-imx6dl-enable-cpufreq-support.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 978ed904c17cd39700a5e1f95ee29ef4fee08ce9 Mon Sep 17 00:00:00 2001 -From: Anson Huang <b20788@freescale.com> -Date: Thu, 19 Dec 2013 10:02:10 -0500 -Subject: [PATCH] ARM: dts: imx6dl: enable cpufreq support - -This patch adds cpufreq dts for i.mx6dl to support cpufreq driver. - -Signed-off-by: Anson Huang <b20788@freescale.com> -Signed-off-by: Shawn Guo <shawn.guo@linaro.org> ---- - arch/arm/boot/dts/imx6dl.dtsi | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - ---- a/arch/arm/boot/dts/imx6dl.dtsi -+++ b/arch/arm/boot/dts/imx6dl.dtsi -@@ -21,6 +21,26 @@ - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; -+ operating-points = < -+ /* kHz uV */ -+ 996000 1275000 -+ 792000 1175000 -+ 396000 1075000 -+ >; -+ fsl,soc-operating-points = < -+ /* ARM kHz SOC-PU uV */ -+ 996000 1175000 -+ 792000 1175000 -+ 396000 1175000 -+ >; -+ clock-latency = <61036>; /* two CLK32 periods */ -+ clocks = <&clks 104>, <&clks 6>, <&clks 16>, -+ <&clks 17>, <&clks 170>; -+ clock-names = "arm", "pll2_pfd2_396m", "step", -+ "pll1_sw", "pll1_sys"; -+ arm-supply = <®_arm>; -+ pu-supply = <®_pu>; -+ soc-supply = <®_soc>; - }; - - cpu@1 { diff --git a/target/linux/imx6/patches-3.14/0005-PCI-designware-Use-new-OF-interrupt-mapping-when-pos.patch b/target/linux/imx6/patches-3.14/0005-PCI-designware-Use-new-OF-interrupt-mapping-when-pos.patch deleted file mode 100644 index 19db40451d..0000000000 --- a/target/linux/imx6/patches-3.14/0005-PCI-designware-Use-new-OF-interrupt-mapping-when-pos.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 804f57b1a63c7435fe43b36942581cc6c79ebb5c Mon Sep 17 00:00:00 2001 -From: Lucas Stach <l.stach@pengutronix.de> -Date: Wed, 5 Mar 2014 14:25:51 +0100 -Subject: [PATCH] PCI: designware: Use new OF interrupt mapping when possible - -Use new OF interrupt mapping (of_irq_parse_and_map_pci()) when possible. -This is the recommended method of doing the IRQ mapping. For old -devicetrees we fall back to the previous practice. - -This makes INTB, INTC, and INTD work on i.MX. - -Tested-by: Tim Harvey <tharvey@gateworks.com> -Signed-off-by: Lucas Stach <l.stach@pengutronix.de> -Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> -Reviewed-by: Marek Vasut <marex@denx.de> -Acked-by: Arnd Bergmann <arnd@arndb.de> -Acked-by: Jingoo Han <jg1.han@samsung.com> ---- - drivers/pci/host/pcie-designware.c | 12 +++++++++--- - 1 file changed, 9 insertions(+), 3 deletions(-) - ---- a/drivers/pci/host/pcie-designware.c -+++ b/drivers/pci/host/pcie-designware.c -@@ -17,6 +17,7 @@ - #include <linux/module.h> - #include <linux/msi.h> - #include <linux/of_address.h> -+#include <linux/of_pci.h> - #include <linux/pci.h> - #include <linux/pci_regs.h> - #include <linux/types.h> -@@ -492,7 +493,7 @@ int __init dw_pcie_host_init(struct pcie - dw_pci.nr_controllers = 1; - dw_pci.private_data = (void **)&pp; - -- pci_common_init(&dw_pci); -+ pci_common_init_dev(pp->dev, &dw_pci); - pci_assign_unassigned_resources(); - #ifdef CONFIG_PCI_DOMAINS - dw_pci.domain++; -@@ -725,7 +726,7 @@ static struct pci_bus *dw_pcie_scan_bus( - - if (pp) { - pp->root_bus_nr = sys->busnr; -- bus = pci_scan_root_bus(NULL, sys->busnr, &dw_pcie_ops, -+ bus = pci_scan_root_bus(pp->dev, sys->busnr, &dw_pcie_ops, - sys, &sys->resources); - } else { - bus = NULL; -@@ -738,8 +739,13 @@ static struct pci_bus *dw_pcie_scan_bus( - static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) - { - struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); -+ int irq; - -- return pp->irq; -+ irq = of_irq_parse_and_map_pci(dev, slot, pin); -+ if (!irq) -+ irq = pp->irq; -+ -+ return irq; - } - - static void dw_pcie_add_bus(struct pci_bus *bus) diff --git a/target/linux/imx6/patches-3.14/0006-ARM-dts-imx6-add-PCIe-interrupt-mapping-properties.patch b/target/linux/imx6/patches-3.14/0006-ARM-dts-imx6-add-PCIe-interrupt-mapping-properties.patch deleted file mode 100644 index ade85fc290..0000000000 --- a/target/linux/imx6/patches-3.14/0006-ARM-dts-imx6-add-PCIe-interrupt-mapping-properties.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 07134a365f1c4be6e840a00ae452d1593f15c5fc Mon Sep 17 00:00:00 2001 -From: Lucas Stach <l.stach@pengutronix.de> -Date: Wed, 5 Mar 2014 14:25:50 +0100 -Subject: [PATCH] ARM: dts: imx6: add PCIe interrupt mapping properties - -As defined by the common PCI bindings. - -Signed-off-by: Lucas Stach <l.stach@pengutronix.de> -Acked-by: Arnd Bergmann <arnd@arndb.de> -Signed-off-by: Shawn Guo <shawn.guo@linaro.org> ---- - arch/arm/boot/dts/imx6qdl.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm/boot/dts/imx6qdl.dtsi -+++ b/arch/arm/boot/dts/imx6qdl.dtsi -@@ -10,6 +10,8 @@ - * http://www.gnu.org/copyleft/gpl.html - */ - -+#include <dt-bindings/interrupt-controller/arm-gic.h> -+ - #include "skeleton.dtsi" - - / { -@@ -127,6 +129,12 @@ - 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ - num-lanes = <1>; - interrupts = <0 123 0x04>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; - clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; - status = "disabled"; diff --git a/target/linux/imx6/patches-3.14/0007-ARM-dts-imx-drop-invalid-size-and-address-cells-prop.patch b/target/linux/imx6/patches-3.14/0007-ARM-dts-imx-drop-invalid-size-and-address-cells-prop.patch deleted file mode 100644 index 075e4a9670..0000000000 --- a/target/linux/imx6/patches-3.14/0007-ARM-dts-imx-drop-invalid-size-and-address-cells-prop.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 54e8eaeec1227a024373e37315770cc79d69917b Mon Sep 17 00:00:00 2001 -From: Lucas Stach <l.stach@pengutronix.de> -Date: Fri, 28 Mar 2014 17:25:51 +0100 -Subject: [PATCH] ARM: dts: imx: drop invalid size and address cells properties - -Those two properties should have been set to zero, which -is the same as not specifying them. - -Having address-cells set to 1 causes OF interrupt -mapping routines to add 1 to the interrupt-cells -property and as result fail because all calculations -are off by one. - -Signed-off-by: Lucas Stach <l.stach@pengutronix.de> -Signed-off-by: Shawn Guo <shawn.guo@freescale.com> ---- - arch/arm/boot/dts/imx6qdl.dtsi | 2 -- - arch/arm/boot/dts/imx6sl.dtsi | 2 -- - 2 files changed, 4 deletions(-) - ---- a/arch/arm/boot/dts/imx6qdl.dtsi -+++ b/arch/arm/boot/dts/imx6qdl.dtsi -@@ -40,8 +40,6 @@ - intc: interrupt-controller@00a01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; -- #address-cells = <1>; -- #size-cells = <1>; - interrupt-controller; - reg = <0x00a01000 0x1000>, - <0x00a00100 0x100>; ---- a/arch/arm/boot/dts/imx6sl.dtsi -+++ b/arch/arm/boot/dts/imx6sl.dtsi -@@ -44,8 +44,6 @@ - intc: interrupt-controller@00a01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; -- #address-cells = <1>; -- #size-cells = <1>; - interrupt-controller; - reg = <0x00a01000 0x1000>, - <0x00a00100 0x100>; diff --git a/target/linux/imx6/patches-3.14/0008-ARM-imx-add-speed-grading-check-for-i.mx6-soc.patch b/target/linux/imx6/patches-3.14/0008-ARM-imx-add-speed-grading-check-for-i.mx6-soc.patch deleted file mode 100644 index 70b7014314..0000000000 --- a/target/linux/imx6/patches-3.14/0008-ARM-imx-add-speed-grading-check-for-i.mx6-soc.patch +++ /dev/null @@ -1,76 +0,0 @@ -From c962a0996335fae7f79e64677f47d4784b86f692 Mon Sep 17 00:00:00 2001 -From: Anson Huang <b20788@freescale.com> -Date: Wed, 12 Feb 2014 17:57:03 +0800 -Subject: [PATCH] ARM: imx: add speed grading check for i.mx6 soc - -The fuse map of speed_grading[1:0] defines the max speed -of ARM, see below the definition: - -2b'11: 1200000000Hz; -2b'10: 996000000Hz; -2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz. -2b'00: 792000000Hz; - -Need to remove all illegal setpoints according to fuse -map. - -Signed-off-by: Anson Huang <b20788@freescale.com> -Signed-off-by: Shawn Guo <shawn.guo@linaro.org> ---- - arch/arm/mach-imx/mach-imx6q.c | 26 +++++++++++++++++++++++--- - 1 file changed, 23 insertions(+), 3 deletions(-) - ---- a/arch/arm/mach-imx/mach-imx6q.c -+++ b/arch/arm/mach-imx/mach-imx6q.c -@@ -219,8 +219,10 @@ static void __init imx6q_init_machine(vo - #define OCOTP_CFG3 0x440 - #define OCOTP_CFG3_SPEED_SHIFT 16 - #define OCOTP_CFG3_SPEED_1P2GHZ 0x3 -+#define OCOTP_CFG3_SPEED_996MHZ 0x2 -+#define OCOTP_CFG3_SPEED_852MHZ 0x1 - --static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev) -+static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev) - { - struct device_node *np; - void __iomem *base; -@@ -238,11 +240,29 @@ static void __init imx6q_opp_check_1p2gh - goto put_node; - } - -+ /* -+ * SPEED_GRADING[1:0] defines the max speed of ARM: -+ * 2b'11: 1200000000Hz; -+ * 2b'10: 996000000Hz; -+ * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz. -+ * 2b'00: 792000000Hz; -+ * We need to set the max speed of ARM according to fuse map. -+ */ - val = readl_relaxed(base + OCOTP_CFG3); - val >>= OCOTP_CFG3_SPEED_SHIFT; -- if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ) -+ val &= 0x3; -+ -+ if (val != OCOTP_CFG3_SPEED_1P2GHZ) - if (dev_pm_opp_disable(cpu_dev, 1200000000)) - pr_warn("failed to disable 1.2 GHz OPP\n"); -+ if (val < OCOTP_CFG3_SPEED_996MHZ) -+ if (dev_pm_opp_disable(cpu_dev, 996000000)) -+ pr_warn("failed to disable 996 MHz OPP\n"); -+ if (cpu_is_imx6q()) { -+ if (val != OCOTP_CFG3_SPEED_852MHZ) -+ if (dev_pm_opp_disable(cpu_dev, 852000000)) -+ pr_warn("failed to disable 852 MHz OPP\n"); -+ } - - put_node: - of_node_put(np); -@@ -268,7 +288,7 @@ static void __init imx6q_opp_init(void) - goto put_node; - } - -- imx6q_opp_check_1p2ghz(cpu_dev); -+ imx6q_opp_check_speed_grading(cpu_dev); - - put_node: - of_node_put(np); diff --git a/target/linux/imx6/patches-3.14/0050-sky2-allow-mac-to-come-from-dt.patch b/target/linux/imx6/patches-3.14/0050-sky2-allow-mac-to-come-from-dt.patch deleted file mode 100644 index bab418bf26..0000000000 --- a/target/linux/imx6/patches-3.14/0050-sky2-allow-mac-to-come-from-dt.patch +++ /dev/null @@ -1,69 +0,0 @@ -From: Tim Harvey <tharvey@gateworks.com> -Subject: [PATCH] sky2: allow mac to come from dt - -The driver reads the mac address from the device registers which would -need to have been programmed by the bootloader. This patch adds -the ability to pull the mac from devicetree via the aliases/sky2 node. - -Signed-off-by: Tim Harvey <tharvey@gateworks.com> ---- - drivers/net/ethernet/marvell/sky2.c | 33 ++++++++++++++++++++++++++++++++- - 1 file changed, 32 insertions(+), 1 deletion(-) - ---- a/drivers/net/ethernet/marvell/sky2.c -+++ b/drivers/net/ethernet/marvell/sky2.c -@@ -44,6 +44,8 @@ - #include <linux/prefetch.h> - #include <linux/debugfs.h> - #include <linux/mii.h> -+#include <linux/of_device.h> -+#include <linux/of_net.h> - - #include <asm/irq.h> - -@@ -4748,6 +4750,7 @@ static struct net_device *sky2_init_netd - { - struct sky2_port *sky2; - struct net_device *dev = alloc_etherdev(sizeof(*sky2)); -+ unsigned char *iap, tmpaddr[ETH_ALEN]; - - if (!dev) - return NULL; -@@ -4805,8 +4808,36 @@ static struct net_device *sky2_init_netd - - dev->features |= dev->hw_features; - -+ /* -+ * try to get mac address in the following order: -+ * 1) from device tree data -+ * 2) from internal registers set by bootloader -+ */ -+ iap = NULL; -+ if (IS_ENABLED(CONFIG_OF)) { -+ struct device_node *np; -+ np = of_find_node_by_path("/aliases"); -+ if (np) { -+ const char *path = of_get_property(np, "sky2", NULL); -+ if (path) -+ np = of_find_node_by_path(path); -+ if (np) -+ path = of_get_mac_address(np); -+ if (path) -+ iap = (unsigned char *) path; -+ } -+ } -+ -+ /* -+ * 2) mac registers set by bootloader -+ */ -+ if (!iap || !is_valid_ether_addr(iap)) { -+ memcpy_fromio(&tmpaddr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); -+ iap = &tmpaddr[0]; -+ } -+ - /* read the mac address */ -- memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); -+ memcpy(dev->dev_addr, iap, ETH_ALEN); - - return dev; - } diff --git a/target/linux/imx6/patches-3.14/0055-pci_imx6_fix-boot-hang-when-link-already-enabled.patch b/target/linux/imx6/patches-3.14/0055-pci_imx6_fix-boot-hang-when-link-already-enabled.patch deleted file mode 100644 index bae5a1fdf8..0000000000 --- a/target/linux/imx6/patches-3.14/0055-pci_imx6_fix-boot-hang-when-link-already-enabled.patch +++ /dev/null @@ -1,86 +0,0 @@ -This fixes a boot hang observed when the bootloader -already enabled the PCIe link for it's own use. The -fundamental problem is that Freescale forgot to wire -up the core reset, so software doesn't have a sane way -to get the core into a defined state. - -According to the DW PCIe core reference manual configuration -of the core may only happen when the LTSSM is disabled, so -this is one of the first things we need to do. Apparently -this isn't safe to do when the LTSSM is in any other state -than "detect" as we observe an instant machine hang when -trying to do so while the link is already up. - -As a workaround force LTSSM into detect state right before -hitting the disable switch. - -Reported-by: Fabio Estevam <fabio.estevam <at> freescale.com> -Signed-off-by: Lucas Stach <l.stach <at> pengutronix.de> -Acked-by: Tim Harvey <tharvey <at> gateworks.com> ---- a/drivers/pci/host/pci-imx6.c -+++ b/drivers/pci/host/pci-imx6.c -@@ -52,6 +52,9 @@ struct imx6_pcie { - - /* PCIe Port Logic registers (memory-mapped) */ - #define PL_OFFSET 0x700 -+#define PCIE_PL_PFLR (PL_OFFSET + 0x08) -+#define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16) -+#define PCIE_PL_PFLR_FORCE_LINK (1 << 15) - #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) - #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) - #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29) -@@ -217,6 +220,31 @@ static int imx6q_pcie_abort_handler(unsi - static int imx6_pcie_assert_core_reset(struct pcie_port *pp) - { - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); -+ u32 val, gpr1, gpr12; -+ -+ /* -+ * If the bootloader already enabled the link we need some special -+ * handling to get the core back into a state where it is safe to -+ * touch it for configuration. As there is no dedicated reset signal -+ * wired up for MX6QDL, we need to manually force LTSSM into "detect" -+ * state before completely disabling LTSSM, which is a prerequisite -+ * for core configuration. -+ * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong -+ * indication that the bootloader activated the link. -+ */ -+ regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1); -+ regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12); -+ -+ if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) && -+ (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) { -+ val = readl(pp->dbi_base + PCIE_PL_PFLR); -+ val &= ~PCIE_PL_PFLR_LINK_STATE_MASK; -+ val |= PCIE_PL_PFLR_FORCE_LINK; -+ writel(val, pp->dbi_base + PCIE_PL_PFLR); -+ -+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, -+ IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); -+ } - - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); -@@ -627,6 +655,14 @@ static int __init imx6_pcie_probe(struct - return 0; - } - -+static void imx6_pcie_shutdown(struct platform_device *pdev) -+{ -+ struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev); -+ -+ /* bring down link, so bootloader gets clean state in case of reboot */ -+ imx6_pcie_assert_core_reset(&imx6_pcie->pp); -+} -+ - static const struct of_device_id imx6_pcie_of_match[] = { - { .compatible = "fsl,imx6q-pcie", }, - {}, -@@ -639,6 +675,7 @@ static struct platform_driver imx6_pcie_ - .owner = THIS_MODULE, - .of_match_table = imx6_pcie_of_match, - }, -+ .shutdown = imx6_pcie_shutdown, - }; - - /* Freescale PCIe driver does not allow module unload */ diff --git a/target/linux/imx6/patches-3.14/0060-pci_imx6_fix-link-failure.patch b/target/linux/imx6/patches-3.14/0060-pci_imx6_fix-link-failure.patch deleted file mode 100644 index e416d8332d..0000000000 --- a/target/linux/imx6/patches-3.14/0060-pci_imx6_fix-link-failure.patch +++ /dev/null @@ -1,38 +0,0 @@ -PCI: imx6: fix occasional link failure - -According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable -for SS function) must remain deasserted until the reference clock is running -at the appropriate frequency. - -Without this patch we find a high link failure rate (>5%) on certain -IMX6 boards at various temperatures. - -Signed-off-by: Tim Harvey <tharvey@gateworks.com> - ---- a/drivers/pci/host/pci-imx6.c -+++ b/drivers/pci/host/pci-imx6.c -@@ -262,11 +262,6 @@ static int imx6_pcie_deassert_core_reset - if (gpio_is_valid(imx6_pcie->power_on_gpio)) - gpio_set_value(imx6_pcie->power_on_gpio, 1); - -- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, -- IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); -- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, -- IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); -- - ret = clk_prepare_enable(imx6_pcie->sata_ref_100m); - if (ret) { - dev_err(pp->dev, "unable to enable sata_ref_100m\n"); -@@ -294,6 +289,12 @@ static int imx6_pcie_deassert_core_reset - /* allow the clocks to stabilize */ - usleep_range(200, 500); - -+ /* power up core phy and enable ref clock */ -+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, -+ IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); -+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, -+ IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); -+ - /* Some boards don't have PCIe reset GPIO. */ - if (gpio_is_valid(imx6_pcie->reset_gpio)) { - gpio_set_value(imx6_pcie->reset_gpio, 0); diff --git a/target/linux/imx6/patches-3.14/100-bootargs.patch b/target/linux/imx6/patches-3.14/100-bootargs.patch deleted file mode 100644 index 0954391203..0000000000 --- a/target/linux/imx6/patches-3.14/100-bootargs.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/boot/dts/imx6dl-wandboard.dts -+++ b/arch/arm/boot/dts/imx6dl-wandboard.dts -@@ -19,4 +19,8 @@ - memory { - reg = <0x10000000 0x40000000>; - }; -+ -+ chosen { -+ bootargs = "console=ttymxc0,115200"; -+ }; - }; diff --git a/target/linux/imx6/patches-3.14/200-pci_designware_add-ability-for-custom-swizzle.patch b/target/linux/imx6/patches-3.14/200-pci_designware_add-ability-for-custom-swizzle.patch deleted file mode 100644 index b174376860..0000000000 --- a/target/linux/imx6/patches-3.14/200-pci_designware_add-ability-for-custom-swizzle.patch +++ /dev/null @@ -1,33 +0,0 @@ -commit e84634dc6c7f3f6af9b8ef1fb36f0d85c476ab95 -Author: Tim Harvey <tharvey@gateworks.com> -Date: Thu Feb 27 01:02:23 2014 -0800 - - PCI: designware: add ability for custom swizzle - - Add the ability for a platform driver to provide a platform-specific - swizzle function. - - Signed-off-by: Tim Harvey <tharvey@gateworks.com> - ---- a/drivers/pci/host/pcie-designware.c -+++ b/drivers/pci/host/pcie-designware.c -@@ -481,6 +481,9 @@ int __init dw_pcie_host_init(struct pcie - if (pp->ops->host_init) - pp->ops->host_init(pp); - -+ if (pp->swizzle) -+ dw_pci.swizzle = pp->swizzle; -+ - dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); - - /* program correct class for RC */ ---- a/drivers/pci/host/pcie-designware.h -+++ b/drivers/pci/host/pcie-designware.h -@@ -53,6 +53,7 @@ struct pcie_port { - struct irq_domain *irq_domain; - unsigned long msi_data; - DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); -+ u8 (*swizzle)(struct pci_dev *, u8 *); - }; - - struct pcie_host_ops { diff --git a/target/linux/imx6/patches-3.14/201-pci_imx6_ventana_fixup-for-IRQ-mismapping.patch b/target/linux/imx6/patches-3.14/201-pci_imx6_ventana_fixup-for-IRQ-mismapping.patch deleted file mode 100644 index c8e2a0e0e3..0000000000 --- a/target/linux/imx6/patches-3.14/201-pci_imx6_ventana_fixup-for-IRQ-mismapping.patch +++ /dev/null @@ -1,81 +0,0 @@ -commit 2c0d0491438433a1f327f2e754c7b6b55fec51c4 -Author: Tim Harvey <tharvey@gateworks.com> -Date: Thu Feb 27 00:59:53 2014 -0800 - - PCI: imx6: ventana: fixup for IRQ mismapping - - The TI XIO2001 PCIe-to-PCI bridge used on several Ventana expansion boards - has its slot-to-bridge IRQ mapping reversed from the PCI specification: - - INTA->INTD - INTB->INTC - INTC->INTB - INTD->INTA - - Implement a custom swizzle function that does a fixup on the interrupt for - devices on a TI XIO2001 bridge. - - Signed-off-by: Tim Harvey <tharvey@gateworks.com> - ---- a/drivers/pci/host/pci-imx6.c -+++ b/drivers/pci/host/pci-imx6.c -@@ -540,6 +540,39 @@ static int imx6_add_pcie_port(struct pci - return 0; - } - -+/* TI XIO2001 PCIe-to-PCI bridge on GW16082 exp card has IRQs reversed */ -+u8 ventana_swizzle(struct pci_dev *dev, u8 *pin) -+{ -+ u8 i = 0; -+ struct pci_dev *pdev = dev; -+ -+ /* count number of TI XIO2001 bridges on bus */ -+ while (!pci_is_root_bus(pdev->bus)) { -+ if (pdev->bus && pdev->bus->self && -+ (pdev->bus->self->vendor == PCI_VENDOR_ID_TI) && -+ (pdev->bus->self->device == PCI_DEVICE_ID_TI_XIO2001)) { -+ i++; -+ } -+ pdev = pdev->bus->self; -+ } -+ while (!pci_is_root_bus(dev->bus)) { -+ /* if we are directly downstream from 1st TI XIO2001 bridge */ -+ if (dev->bus && dev->bus->self && -+ (dev->bus->self->vendor == PCI_VENDOR_ID_TI) && -+ (dev->bus->self->device == PCI_DEVICE_ID_TI_XIO2001)) { -+ if (--i == 0) { -+ /* swap IRQs and swizzle backwards */ -+ *pin = (15 - PCI_SLOT(dev->devfn)) + 1; -+ dev = dev->bus->self; -+ continue; -+ } -+ } -+ *pin = pci_swizzle_interrupt_pin(dev, *pin); -+ dev = dev->bus->self; -+ } -+ return PCI_SLOT(dev->devfn); -+} -+ - static int __init imx6_pcie_probe(struct platform_device *pdev) - { - struct imx6_pcie *imx6_pcie; -@@ -648,6 +681,9 @@ static int __init imx6_pcie_probe(struct - return PTR_ERR(imx6_pcie->iomuxc_gpr); - } - -+ if (of_machine_is_compatible("gw,ventana")) -+ pp->swizzle = ventana_swizzle; -+ - ret = imx6_add_pcie_port(pp, pdev); - if (ret < 0) - return ret; ---- a/include/linux/pci_ids.h -+++ b/include/linux/pci_ids.h -@@ -822,6 +822,7 @@ - #define PCI_DEVICE_ID_TI_XX12 0x8039 - #define PCI_DEVICE_ID_TI_XX12_FM 0x803b - #define PCI_DEVICE_ID_TI_XIO2000A 0x8231 -+#define PCI_DEVICE_ID_TI_XIO2001 0x8240 - #define PCI_DEVICE_ID_TI_1130 0xac12 - #define PCI_DEVICE_ID_TI_1031 0xac13 - #define PCI_DEVICE_ID_TI_1131 0xac15 diff --git a/target/linux/imx6/patches-3.14/202-net-igb-add-i210-i211-support-for-phy-read-write.patch b/target/linux/imx6/patches-3.14/202-net-igb-add-i210-i211-support-for-phy-read-write.patch deleted file mode 100644 index 9de5dfe44a..0000000000 --- a/target/linux/imx6/patches-3.14/202-net-igb-add-i210-i211-support-for-phy-read-write.patch +++ /dev/null @@ -1,129 +0,0 @@ -Author: Tim Harvey <tharvey@gateworks.com> -Date: Thu May 15 00:12:26 2014 -0700 - - net: igb: add i210/i211 support for phy read/write - - The i210/i211 uses the MDICNFG register for the phy address instead of the - MDIC register. - - Signed-off-by: Tim Harvey <tharvey@gateworks.com> - ---- a/drivers/net/ethernet/intel/igb/e1000_phy.c -+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c -@@ -139,7 +139,7 @@ out: - s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) - { - struct e1000_phy_info *phy = &hw->phy; -- u32 i, mdic = 0; -+ u32 i, mdicnfg, mdic = 0; - s32 ret_val = 0; - - if (offset > MAX_PHY_REG_ADDRESS) { -@@ -152,11 +152,25 @@ s32 igb_read_phy_reg_mdic(struct e1000_h - * Control register. The MAC will take care of interfacing with the - * PHY to retrieve the desired data. - */ -- mdic = ((offset << E1000_MDIC_REG_SHIFT) | -- (phy->addr << E1000_MDIC_PHY_SHIFT) | -- (E1000_MDIC_OP_READ)); -+ switch (hw->mac.type) { -+ case e1000_i210: -+ case e1000_i211: -+ mdicnfg = rd32(E1000_MDICNFG); -+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); -+ mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); -+ wr32(E1000_MDICNFG, mdicnfg); -+ mdic = ((offset << E1000_MDIC_REG_SHIFT) | -+ (E1000_MDIC_OP_READ)); -+ break; -+ default: -+ mdic = ((offset << E1000_MDIC_REG_SHIFT) | -+ (phy->addr << E1000_MDIC_PHY_SHIFT) | -+ (E1000_MDIC_OP_READ)); -+ break; -+ } - - wr32(E1000_MDIC, mdic); -+ wrfl(); - - /* Poll the ready bit to see if the MDI read completed - * Increasing the time out as testing showed failures with -@@ -181,6 +195,18 @@ s32 igb_read_phy_reg_mdic(struct e1000_h - *data = (u16) mdic; - - out: -+ switch (hw->mac.type) { -+ /* restore MDICNFG to have phy's addr */ -+ case e1000_i210: -+ case e1000_i211: -+ mdicnfg = rd32(E1000_MDICNFG); -+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); -+ mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT); -+ wr32(E1000_MDICNFG, mdicnfg); -+ break; -+ default: -+ break; -+ } - return ret_val; - } - -@@ -195,7 +221,7 @@ out: - s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) - { - struct e1000_phy_info *phy = &hw->phy; -- u32 i, mdic = 0; -+ u32 i, mdicnfg, mdic = 0; - s32 ret_val = 0; - - if (offset > MAX_PHY_REG_ADDRESS) { -@@ -208,12 +234,27 @@ s32 igb_write_phy_reg_mdic(struct e1000_ - * Control register. The MAC will take care of interfacing with the - * PHY to retrieve the desired data. - */ -- mdic = (((u32)data) | -- (offset << E1000_MDIC_REG_SHIFT) | -- (phy->addr << E1000_MDIC_PHY_SHIFT) | -- (E1000_MDIC_OP_WRITE)); -+ switch (hw->mac.type) { -+ case e1000_i210: -+ case e1000_i211: -+ mdicnfg = rd32(E1000_MDICNFG); -+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); -+ mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); -+ wr32(E1000_MDICNFG, mdicnfg); -+ mdic = (((u32)data) | -+ (offset << E1000_MDIC_REG_SHIFT) | -+ (E1000_MDIC_OP_WRITE)); -+ break; -+ default: -+ mdic = (((u32)data) | -+ (offset << E1000_MDIC_REG_SHIFT) | -+ (phy->addr << E1000_MDIC_PHY_SHIFT) | -+ (E1000_MDIC_OP_WRITE)); -+ break; -+ } - - wr32(E1000_MDIC, mdic); -+ wrfl(); - - /* Poll the ready bit to see if the MDI read completed - * Increasing the time out as testing showed failures with -@@ -237,6 +278,18 @@ s32 igb_write_phy_reg_mdic(struct e1000_ - } - - out: -+ switch (hw->mac.type) { -+ /* restore MDICNFG to have phy's addr */ -+ case e1000_i210: -+ case e1000_i211: -+ mdicnfg = rd32(E1000_MDICNFG); -+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); -+ mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT); -+ wr32(E1000_MDICNFG, mdicnfg); -+ break; -+ default: -+ break; -+ } - return ret_val; - } - diff --git a/target/linux/imx6/patches-3.14/203-net-igb-add-phy-read-write-functions-that-accept-phy.patch b/target/linux/imx6/patches-3.14/203-net-igb-add-phy-read-write-functions-that-accept-phy.patch deleted file mode 100644 index b6688db9ac..0000000000 --- a/target/linux/imx6/patches-3.14/203-net-igb-add-phy-read-write-functions-that-accept-phy.patch +++ /dev/null @@ -1,255 +0,0 @@ -Author: Tim Harvey <tharvey@gateworks.com> -Date: Thu May 15 00:29:18 2014 -0700 - - net: igb: add phy read/write functions that accept phy addr - - Add igb_write_reg_gs40g/igb_read_reg_gs40g that can be passed a phy address. - The existing igb_write_phy_reg_gs40g/igb_read_phy_reg_gs40g become wrappers - to this function. - - Signed-off-by: Tim Harvey <tharvey@gateworks.com> - ---- a/drivers/net/ethernet/intel/igb/e1000_82575.c -+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c -@@ -2142,7 +2142,7 @@ static s32 igb_read_phy_reg_82580(struct - if (ret_val) - goto out; - -- ret_val = igb_read_phy_reg_mdic(hw, offset, data); -+ ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr, offset, data); - - hw->phy.ops.release(hw); - -@@ -2167,7 +2167,7 @@ static s32 igb_write_phy_reg_82580(struc - if (ret_val) - goto out; - -- ret_val = igb_write_phy_reg_mdic(hw, offset, data); -+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, offset, data); - - hw->phy.ops.release(hw); - ---- a/drivers/net/ethernet/intel/igb/e1000_phy.c -+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c -@@ -136,9 +136,8 @@ out: - * Reads the MDI control regsiter in the PHY at offset and stores the - * information read to data. - **/ --s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) -+s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data) - { -- struct e1000_phy_info *phy = &hw->phy; - u32 i, mdicnfg, mdic = 0; - s32 ret_val = 0; - -@@ -157,14 +156,14 @@ s32 igb_read_phy_reg_mdic(struct e1000_h - case e1000_i211: - mdicnfg = rd32(E1000_MDICNFG); - mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); -- mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); -+ mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT); - wr32(E1000_MDICNFG, mdicnfg); - mdic = ((offset << E1000_MDIC_REG_SHIFT) | - (E1000_MDIC_OP_READ)); - break; - default: - mdic = ((offset << E1000_MDIC_REG_SHIFT) | -- (phy->addr << E1000_MDIC_PHY_SHIFT) | -+ (addr << E1000_MDIC_PHY_SHIFT) | - (E1000_MDIC_OP_READ)); - break; - } -@@ -218,9 +217,8 @@ out: - * - * Writes data to MDI control register in the PHY at offset. - **/ --s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) -+s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data) - { -- struct e1000_phy_info *phy = &hw->phy; - u32 i, mdicnfg, mdic = 0; - s32 ret_val = 0; - -@@ -239,7 +237,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_ - case e1000_i211: - mdicnfg = rd32(E1000_MDICNFG); - mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); -- mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); -+ mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT); - wr32(E1000_MDICNFG, mdicnfg); - mdic = (((u32)data) | - (offset << E1000_MDIC_REG_SHIFT) | -@@ -248,7 +246,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_ - default: - mdic = (((u32)data) | - (offset << E1000_MDIC_REG_SHIFT) | -- (phy->addr << E1000_MDIC_PHY_SHIFT) | -+ (addr << E1000_MDIC_PHY_SHIFT) | - (E1000_MDIC_OP_WRITE)); - break; - } -@@ -539,7 +537,7 @@ s32 igb_read_phy_reg_igp(struct e1000_hw - goto out; - - if (offset > MAX_PHY_MULTI_PAGE_REG) { -- ret_val = igb_write_phy_reg_mdic(hw, -+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, - IGP01E1000_PHY_PAGE_SELECT, - (u16)offset); - if (ret_val) { -@@ -548,8 +546,8 @@ s32 igb_read_phy_reg_igp(struct e1000_hw - } - } - -- ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, -- data); -+ ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr, -+ MAX_PHY_REG_ADDRESS & offset, data); - - hw->phy.ops.release(hw); - -@@ -578,7 +576,7 @@ s32 igb_write_phy_reg_igp(struct e1000_h - goto out; - - if (offset > MAX_PHY_MULTI_PAGE_REG) { -- ret_val = igb_write_phy_reg_mdic(hw, -+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, - IGP01E1000_PHY_PAGE_SELECT, - (u16)offset); - if (ret_val) { -@@ -587,8 +585,8 @@ s32 igb_write_phy_reg_igp(struct e1000_h - } - } - -- ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, -- data); -+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, -+ MAX_PHY_REG_ADDRESS & offset, data); - - hw->phy.ops.release(hw); - -@@ -2554,8 +2552,9 @@ out: - } - - /** -- * igb_write_phy_reg_gs40g - Write GS40G PHY register -+ * igb_write_reg_gs40g - Write GS40G PHY register - * @hw: pointer to the HW structure -+ * @addr: phy address to write to - * @offset: lower half is register offset to write to - * upper half is page to use. - * @data: data to write at register offset -@@ -2563,7 +2562,7 @@ out: - * Acquires semaphore, if necessary, then writes the data to PHY register - * at the offset. Release any acquired semaphores before exiting. - **/ --s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) -+s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data) - { - s32 ret_val; - u16 page = offset >> GS40G_PAGE_SHIFT; -@@ -2573,10 +2572,10 @@ s32 igb_write_phy_reg_gs40g(struct e1000 - if (ret_val) - return ret_val; - -- ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); -+ ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page); - if (ret_val) - goto release; -- ret_val = igb_write_phy_reg_mdic(hw, offset, data); -+ ret_val = igb_write_phy_reg_mdic(hw, addr, offset, data); - - release: - hw->phy.ops.release(hw); -@@ -2584,8 +2583,24 @@ release: - } - - /** -- * igb_read_phy_reg_gs40g - Read GS40G PHY register -+ * igb_write_phy_reg_gs40g - Write GS40G PHY register -+ * @hw: pointer to the HW structure -+ * @offset: lower half is register offset to write to -+ * upper half is page to use. -+ * @data: data to write at register offset -+ * -+ * Acquires semaphore, if necessary, then writes the data to PHY register -+ * at the offset. Release any acquired semaphores before exiting. -+ **/ -+s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) -+{ -+ return igb_write_reg_gs40g(hw, hw->phy.addr, offset, data); -+} -+ -+/** -+ * igb_read_reg_gs40g - Read GS40G PHY register - * @hw: pointer to the HW structure -+ * @addr: phy address to read from - * @offset: lower half is register offset to read to - * upper half is page to use. - * @data: data to read at register offset -@@ -2593,7 +2608,7 @@ release: - * Acquires semaphore, if necessary, then reads the data in the PHY register - * at the offset. Release any acquired semaphores before exiting. - **/ --s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) -+s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data) - { - s32 ret_val; - u16 page = offset >> GS40G_PAGE_SHIFT; -@@ -2603,10 +2618,10 @@ s32 igb_read_phy_reg_gs40g(struct e1000_ - if (ret_val) - return ret_val; - -- ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); -+ ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page); - if (ret_val) - goto release; -- ret_val = igb_read_phy_reg_mdic(hw, offset, data); -+ ret_val = igb_read_phy_reg_mdic(hw, addr, offset, data); - - release: - hw->phy.ops.release(hw); -@@ -2614,6 +2629,21 @@ release: - } - - /** -+ * igb_read_phy_reg_gs40g - Read GS40G PHY register -+ * @hw: pointer to the HW structure -+ * @offset: lower half is register offset to read to -+ * upper half is page to use. -+ * @data: data to read at register offset -+ * -+ * Acquires semaphore, if necessary, then reads the data in the PHY register -+ * at the offset. Release any acquired semaphores before exiting. -+ **/ -+s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) -+{ -+ return igb_read_reg_gs40g(hw, hw->phy.addr, offset, data); -+} -+ -+/** - * igb_set_master_slave_mode - Setup PHY for Master/slave mode - * @hw: pointer to the HW structure - * ---- a/drivers/net/ethernet/intel/igb/e1000_phy.h -+++ b/drivers/net/ethernet/intel/igb/e1000_phy.h -@@ -65,8 +65,8 @@ s32 igb_phy_has_link(struct e1000_hw *h - void igb_power_up_phy_copper(struct e1000_hw *hw); - void igb_power_down_phy_copper(struct e1000_hw *hw); - s32 igb_phy_init_script_igp3(struct e1000_hw *hw); --s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); --s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); -+s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data); -+s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data); - s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data); - s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data); - s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data); -@@ -77,6 +77,8 @@ s32 igb_phy_force_speed_duplex_82580(st - s32 igb_get_cable_length_82580(struct e1000_hw *hw); - s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); - s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data); -+s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data); -+s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data); - s32 igb_check_polarity_m88(struct e1000_hw *hw); - - /* IGP01E1000 Specific Registers */ diff --git a/target/linux/imx6/patches-3.14/204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch b/target/linux/imx6/patches-3.14/204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch deleted file mode 100644 index 0bcbbd7bc3..0000000000 --- a/target/linux/imx6/patches-3.14/204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch +++ /dev/null @@ -1,303 +0,0 @@ -Author: Tim Harvey <tharvey@gateworks.com> -Date: Thu May 15 12:36:23 2014 -0700 - - net: igb: register mii_bus for SerDes w/ external phy - - If an i210 is configured for 1000BASE-BX link_mode and has an external phy - specified, then register an mii bus using the external phy address as - a mask. - - An i210 hooked to an external standard phy will be configured with a link_mo - of SGMII in which case phy ops will be configured and used internall in the - igb driver for link status. However, in certain cases one might be using a - backplane SerDes connection to something that talks on the mdio bus but is - not a standard phy, such as a switch. In this case by registering an mdio - bus a phy driver can manage the device. - - Signed-off-by: Tim Harvey <tharvey@gateworks.com> - ---- a/drivers/net/ethernet/intel/igb/e1000_82575.c -+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c -@@ -606,13 +606,25 @@ static s32 igb_get_invariants_82575(stru - switch (link_mode) { - case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: - hw->phy.media_type = e1000_media_type_internal_serdes; -+ if (igb_sgmii_uses_mdio_82575(hw)) { -+ u32 mdicnfg = rd32(E1000_MDICNFG); -+ mdicnfg &= E1000_MDICNFG_PHY_MASK; -+ hw->phy.addr = mdicnfg >> E1000_MDICNFG_PHY_SHIFT; -+ hw_dbg("1000BASE_KX w/ external MDIO device at 0x%x\n", -+ hw->phy.addr); -+ } else { -+ hw_dbg("1000BASE_KX"); -+ } - break; - case E1000_CTRL_EXT_LINK_MODE_SGMII: - /* Get phy control interface type set (MDIO vs. I2C)*/ - if (igb_sgmii_uses_mdio_82575(hw)) { - hw->phy.media_type = e1000_media_type_copper; - dev_spec->sgmii_active = true; -+ hw_dbg("SGMII with external MDIO PHY"); - break; -+ } else { -+ hw_dbg("SGMII with external I2C PHY"); - } - /* fall through for I2C based SGMII */ - case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: -@@ -629,8 +641,11 @@ static s32 igb_get_invariants_82575(stru - hw->phy.media_type = e1000_media_type_copper; - dev_spec->sgmii_active = true; - } -+ hw_dbg("SERDES with external SFP"); - - break; -+ } else { -+ hw_dbg("SERDES"); - } - - /* do not change link mode for 100BaseFX */ ---- a/drivers/net/ethernet/intel/igb/e1000_hw.h -+++ b/drivers/net/ethernet/intel/igb/e1000_hw.h -@@ -32,6 +32,7 @@ - #include <linux/delay.h> - #include <linux/io.h> - #include <linux/netdevice.h> -+#include <linux/phy.h> - - #include "e1000_regs.h" - #include "e1000_defines.h" -@@ -553,6 +554,12 @@ struct e1000_hw { - struct e1000_mbx_info mbx; - struct e1000_host_mng_dhcp_cookie mng_cookie; - -+#ifdef CONFIG_PHYLIB -+ /* Phylib and MDIO interface */ -+ struct mii_bus *mii_bus; -+ struct phy_device *phy_dev; -+ phy_interface_t phy_interface; -+#endif - union { - struct e1000_dev_spec_82575 _82575; - } dev_spec; ---- a/drivers/net/ethernet/intel/igb/igb_main.c -+++ b/drivers/net/ethernet/intel/igb/igb_main.c -@@ -45,6 +45,7 @@ - #include <linux/if_vlan.h> - #include <linux/pci.h> - #include <linux/pci-aspm.h> -+#include <linux/phy.h> - #include <linux/delay.h> - #include <linux/interrupt.h> - #include <linux/ip.h> -@@ -2191,6 +2192,126 @@ static s32 igb_init_i2c(struct igb_adapt - return status; - } - -+ -+#ifdef CONFIG_PHYLIB -+/* -+ * MMIO/PHYdev support -+ */ -+ -+static int igb_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) -+{ -+ struct e1000_hw *hw = bus->priv; -+ u16 out; -+ int err; -+ -+ err = igb_read_reg_gs40g(hw, mii_id, regnum, &out); -+ if (err) -+ return err; -+ return out; -+} -+ -+static int igb_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, -+ u16 val) -+{ -+ struct e1000_hw *hw = bus->priv; -+ -+ return igb_write_reg_gs40g(hw, mii_id, regnum, val); -+} -+ -+static int igb_enet_mdio_reset(struct mii_bus *bus) -+{ -+ udelay(300); -+ return 0; -+} -+ -+static void igb_enet_mii_link(struct net_device *netdev) -+{ -+} -+ -+/* Probe the mdio bus for phys and connect them */ -+static int igb_enet_mii_probe(struct net_device *netdev) -+{ -+ struct igb_adapter *adapter = netdev_priv(netdev); -+ struct e1000_hw *hw = &adapter->hw; -+ struct phy_device *phy_dev = NULL; -+ int phy_id; -+ -+ /* check for attached phy */ -+ for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { -+ if (hw->mii_bus->phy_map[phy_id]) { -+ phy_dev = hw->mii_bus->phy_map[phy_id]; -+ break; -+ } -+ } -+ if (!phy_dev) { -+ netdev_err(netdev, "no PHY found\n"); -+ return -ENODEV; -+ } -+ -+ hw->phy_interface = PHY_INTERFACE_MODE_RGMII; -+ phy_dev = phy_connect(netdev, dev_name(&phy_dev->dev), -+ igb_enet_mii_link, hw->phy_interface); -+ if (IS_ERR(phy_dev)) { -+ netdev_err(netdev, "could not attach to PHY\n"); -+ return PTR_ERR(phy_dev); -+ } -+ -+ hw->phy_dev = phy_dev; -+ netdev_info(netdev, "igb PHY driver [%s] (mii_bus:phy_addr=%s)\n", -+ hw->phy_dev->drv->name, dev_name(&hw->phy_dev->dev)); -+ -+ return 0; -+} -+ -+/* Create and register mdio bus */ -+static int igb_enet_mii_init(struct pci_dev *pdev) -+{ -+ struct mii_bus *mii_bus; -+ struct net_device *netdev = pci_get_drvdata(pdev); -+ struct igb_adapter *adapter = netdev_priv(netdev); -+ struct e1000_hw *hw = &adapter->hw; -+ int err; -+ -+ mii_bus = mdiobus_alloc(); -+ if (mii_bus == NULL) { -+ err = -ENOMEM; -+ goto err_out; -+ } -+ -+ mii_bus->name = "igb_enet_mii_bus"; -+ mii_bus->read = igb_enet_mdio_read; -+ mii_bus->write = igb_enet_mdio_write; -+ mii_bus->reset = igb_enet_mdio_reset; -+ snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", -+ pci_name(pdev), hw->device_id + 1); -+ mii_bus->priv = hw; -+ mii_bus->parent = &pdev->dev; -+ mii_bus->phy_mask = ~(1 << hw->phy.addr); -+ -+ err = mdiobus_register(mii_bus); -+ if (err) { -+ printk(KERN_ERR "failed to register mii_bus: %d\n", err); -+ goto err_out_free_mdiobus; -+ } -+ hw->mii_bus = mii_bus; -+ -+ return 0; -+ -+err_out_free_mdiobus: -+ mdiobus_free(mii_bus); -+err_out: -+ return err; -+} -+ -+static void igb_enet_mii_remove(struct e1000_hw *hw) -+{ -+ if (hw->mii_bus) { -+ mdiobus_unregister(hw->mii_bus); -+ mdiobus_free(hw->mii_bus); -+ } -+} -+#endif /* CONFIG_PHYLIB */ -+ - /** - * igb_probe - Device Initialization Routine - * @pdev: PCI device information struct -@@ -2593,6 +2714,13 @@ static int igb_probe(struct pci_dev *pde - } - - pm_runtime_put_noidle(&pdev->dev); -+ -+#ifdef CONFIG_PHYLIB -+ /* create and register the mdio bus if using ext phy */ -+ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO) -+ igb_enet_mii_init(pdev); -+#endif -+ - return 0; - - err_register: -@@ -2736,6 +2864,10 @@ static void igb_remove(struct pci_dev *p - struct e1000_hw *hw = &adapter->hw; - - pm_runtime_get_noresume(&pdev->dev); -+#ifdef CONFIG_PHYLIB -+ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO) -+ igb_enet_mii_remove(hw); -+#endif - #ifdef CONFIG_IGB_HWMON - igb_sysfs_exit(adapter); - #endif -@@ -3040,6 +3172,12 @@ static int __igb_open(struct net_device - if (!resuming) - pm_runtime_put(&pdev->dev); - -+#ifdef CONFIG_PHYLIB -+ /* Probe and connect to PHY if using ext phy */ -+ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO) -+ igb_enet_mii_probe(netdev); -+#endif -+ - /* start the watchdog. */ - hw->mac.get_link_status = 1; - schedule_work(&adapter->watchdog_task); -@@ -7095,21 +7233,41 @@ void igb_alloc_rx_buffers(struct igb_rin - static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) - { - struct igb_adapter *adapter = netdev_priv(netdev); -+ struct e1000_hw *hw = &adapter->hw; - struct mii_ioctl_data *data = if_mii(ifr); - -- if (adapter->hw.phy.media_type != e1000_media_type_copper) -+ if (adapter->hw.phy.media_type != e1000_media_type_copper && -+ !(rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)) - return -EOPNOTSUPP; - - switch (cmd) { - case SIOCGMIIPHY: -- data->phy_id = adapter->hw.phy.addr; -+ data->phy_id = hw->phy.addr; - break; - case SIOCGMIIREG: -- if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, -- &data->val_out)) -- return -EIO; -+ if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) { -+ if (igb_read_reg_gs40g(hw, data->phy_id, -+ data->reg_num & 0x1F, -+ &data->val_out)) -+ return -EIO; -+ } else { -+ if (igb_read_phy_reg(hw, data->reg_num & 0x1F, -+ &data->val_out)) -+ return -EIO; -+ } - break; - case SIOCSMIIREG: -+ if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) { -+ if (igb_write_reg_gs40g(hw, data->phy_id, -+ data->reg_num & 0x1F, -+ data->val_in)) -+ return -EIO; -+ } else { -+ if (igb_write_phy_reg(hw, data->reg_num & 0x1F, -+ data->val_in)) -+ return -EIO; -+ } -+ break; - default: - return -EOPNOTSUPP; - } diff --git a/target/linux/imx6/patches-3.14/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch b/target/linux/imx6/patches-3.14/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch deleted file mode 100644 index 1350d5a0bb..0000000000 --- a/target/linux/imx6/patches-3.14/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -273,6 +273,14 @@ endif # RTL8366_SMI - - source "drivers/net/phy/b53/Kconfig" - -+config GATEWORKS_GW16083 -+ tristate "Gateworks GW16083 Ethernet Expansion Mezzanine" -+ ---help--- -+ The Gateworks GW16083 Ethernet Expansion Mezzanine connects to a -+ Gateworks Ventana baseboard and provides a 7-port GbE managed -+ Ethernet switch with 4 dedicated GbE RJ45 ports, and 2 Gbe/SFP -+ ports" -+ - endif # PHYLIB - - config MICREL_KS8995MA ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -39,6 +39,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o - obj-$(CONFIG_DP83640_PHY) += dp83640.o - obj-$(CONFIG_STE10XP) += ste10Xp.o - obj-$(CONFIG_MICREL_PHY) += micrel.o -+obj-$(CONFIG_GATEWORKS_GW16083) += gw16083.o - obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o - obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o - obj-$(CONFIG_AT803X_PHY) += at803x.o diff --git a/target/linux/imx6/patches-3.14/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch b/target/linux/imx6/patches-3.14/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch deleted file mode 100644 index cc5f920267..0000000000 --- a/target/linux/imx6/patches-3.14/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch +++ /dev/null @@ -1,56 +0,0 @@ ---- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi -@@ -201,6 +201,11 @@ - }; - }; - }; -+ -+ gw16083: gw16083@52 { -+ compatible = "gateworks,gw16083"; -+ reg = <0x52>; -+ }; - }; - - &i2c3 { ---- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi -@@ -268,6 +268,11 @@ - }; - }; - }; -+ -+ gw16083: gw16083@52 { -+ compatible = "gateworks,gw16083"; -+ reg = <0x52>; -+ }; - }; - - &i2c3 { ---- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi -@@ -289,6 +289,11 @@ - }; - }; - }; -+ -+ gw16083: gw16083@52 { -+ compatible = "gateworks,gw16083"; -+ reg = <0x52>; -+ }; - }; - - &i2c3 { ---- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -@@ -317,6 +317,11 @@ - compatible = "sil,si52147"; - reg = <0x6b>; - }; -+ -+ gw16083: gw16083@52 { -+ compatible = "gateworks,gw16083"; -+ reg = <0x52>; -+ }; - }; - - &i2c3 { diff --git a/target/linux/imx6/patches-3.14/208-ventana-plx-allow-override-gpio-output-mask.patch b/target/linux/imx6/patches-3.14/208-ventana-plx-allow-override-gpio-output-mask.patch deleted file mode 100644 index 97298fd694..0000000000 --- a/target/linux/imx6/patches-3.14/208-ventana-plx-allow-override-gpio-output-mask.patch +++ /dev/null @@ -1,58 +0,0 @@ -This patch allows passing in the gpio output mask used for GPIO0-7 on the -PLX PCIe bridge. These GPIO's are used for PERST# on the downstream ports. - -Allowing the kernel to override the default configuration allows for keeping -specific devices held in reset. One important use of this is to allow -temporarily disabling devices that may request too many resources such as -an unprogrammed i210 device. - ---- a/arch/arm/mach-imx/mach-imx6q.c -+++ b/arch/arm/mach-imx/mach-imx6q.c -@@ -84,6 +84,7 @@ static int ksz9031rn_phy_fixup(struct ph - * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High - * as they are used for slots1-7 PERST# - */ -+unsigned int ventana_plx_gpio = 0xfe; - static void ventana_pciesw_early_fixup(struct pci_dev *dev) - { - u32 dw; -@@ -95,19 +96,25 @@ static void ventana_pciesw_early_fixup(s - return; - - pci_read_config_dword(dev, 0x62c, &dw); -+ dev_info(&dev->dev, "de-asserting downstream PERST# 0x%04x\n", -+ ventana_plx_gpio); - dw |= 0xaaa8; // GPIO1-7 outputs - pci_write_config_dword(dev, 0x62c, dw); -- -- pci_read_config_dword(dev, 0x644, &dw); -- dw |= 0xfe; // GPIO1-7 output high -- pci_write_config_dword(dev, 0x644, dw); -- -+ pci_write_config_dword(dev, 0x644, ventana_plx_gpio); - msleep(100); - } - DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup); - DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup); - DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup); - -+static int __init setup_ventana_plx_gpio(char *str) -+{ -+ get_option(&str, &ventana_plx_gpio); -+ -+ return 0; -+} -+early_param("plx_gpio", setup_ventana_plx_gpio); -+ - static int ar8031_phy_fixup(struct phy_device *dev) - { - u16 val; -@@ -328,7 +335,7 @@ static void __init imx6q_init_irq(void) - irqchip_init(); - } - --static const char *imx6q_dt_compat[] __initconst = { -+static const char *imx6q_dt_compat[] __initdata = { - "fsl,imx6dl", - "fsl,imx6q", - NULL, diff --git a/target/linux/imx6/patches-3.14/209-ventana-gw552x.patch b/target/linux/imx6/patches-3.14/209-ventana-gw552x.patch deleted file mode 100644 index 7c7a295cf5..0000000000 --- a/target/linux/imx6/patches-3.14/209-ventana-gw552x.patch +++ /dev/null @@ -1,18 +0,0 @@ ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -158,6 +158,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ - imx6dl-gw52xx.dtb \ - imx6dl-gw53xx.dtb \ - imx6dl-gw54xx.dtb \ -+ imx6dl-gw552x.dtb \ - imx6dl-hummingboard.dtb \ - imx6dl-sabreauto.dtb \ - imx6dl-sabresd.dtb \ -@@ -169,6 +170,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ - imx6q-gw53xx.dtb \ - imx6q-gw5400-a.dtb \ - imx6q-gw54xx.dtb \ -+ imx6q-gw552x.dtb \ - imx6q-phytec-pbab01.dtb \ - imx6q-sabreauto.dtb \ - imx6q-sabrelite.dtb \ |