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author | John Crispin <john@openwrt.org> | 2016-03-16 09:27:14 +0000 |
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committer | John Crispin <john@openwrt.org> | 2016-03-16 09:27:14 +0000 |
commit | 4d6c4994fc609ac40884631ced2d4e4127c8958e (patch) | |
tree | 6da1e874f0939f02862eee5ccd6a0717dbd122cf /target/linux/generic/patches-4.4/111-jffs2-add-RENAME_EXCHANGE-support.patch | |
parent | ebcce35be48abbd948d6c50ac2d1737f4850e028 (diff) | |
download | master-31e0f0ae-4d6c4994fc609ac40884631ced2d4e4127c8958e.tar.gz master-31e0f0ae-4d6c4994fc609ac40884631ced2d4e4127c8958e.tar.bz2 master-31e0f0ae-4d6c4994fc609ac40884631ced2d4e4127c8958e.zip |
ar71xx: Use PHY fixups for Open Mesh MR1750
The delays of PHY/MAC on the MR1750 are done by u-boot and OpenWrt in
different ways. u-boot only modifies the ETH_CFG of the QCA955x based on
the link speed. But OpenWrt can only modify the PHY delays based on the
link speed.
This can lead to communication problems when u-boot initializes the ETH_CFG
for a specific link speed (e.g. 10BASE-T) but then OpenWrt the sets the PHY
delays to an incompatible value.
Instead reset the ETH_CFG delay bits of the QCA955x to a specific value and
only rely on the AT803x PHY settings.
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
SVN-Revision: 49031
Diffstat (limited to 'target/linux/generic/patches-4.4/111-jffs2-add-RENAME_EXCHANGE-support.patch')
0 files changed, 0 insertions, 0 deletions