From 85b8cf5877ed7082564a47d94917ca7151977625 Mon Sep 17 00:00:00 2001
From: root <root@no.no.james.local>
Date: Thu, 17 May 2018 18:12:57 +0100
Subject: minor fixes, make clock simulator happy and fix AS programming

---
 Makefile | 17 +++--------------
 1 file changed, 3 insertions(+), 14 deletions(-)

(limited to 'Makefile')

diff --git a/Makefile b/Makefile
index b73ea37..7d2149e 100644
--- a/Makefile
+++ b/Makefile
@@ -6,8 +6,7 @@ S2=${S1:pll200.vhd=}
 TIDY_SRC=${S2}
 
 SOF=output_files/${PROJ}.sof
-POF=${PROJ}.pof
-JIC=${PROJ}.jic
+POF=output_files/${PROJ}.pof
 
 default: load_sof.stamp sim.stamp
 
@@ -38,8 +37,8 @@ sim.stamp: fit.stamp
 load_sof.stamp: ${SOF}
 	tools/wrap quartus_pgm -m JTAG -o "p;${SOF}"
 
-#flash: ${POF}
-#	tools/wrap quartus_pgm -m AS -o "p;${POF}"
+flash: ${POF}
+	tools/wrap quartus_pgm -m AS -o "p;${POF}"
 
 quartus:
 	tools/wrap quartus ${PROJ}.qpf
@@ -57,16 +56,6 @@ clean:
 	
 	
 
-${JIC}:${SOF}
-	tools/wrap quartus_cpf -c ${PROJ}.cof
-
-
-flash:${JIC}
-	tools/wrap quartus_pgm -m JTAG -o "ip;${JIC}"
-	tools/wrap quartus_pgm -m JTAG -o "p;${SOF}"
-
-	
-
 tidy:
 	for i in ${TIDY_SRC}; do tools/vhdl-pretty < $$i > $$i.pp && mv -f $$i $$i.orig && mv $$i.pp $$i ; done
 
-- 
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