| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | new pinout and ledHEADmaster | root | 2018-05-29 | 2 | -7/+18 |
| * | Just one freq supported | Rob Langley | 2018-05-29 | 3 | -28/+31 |
| * | only use +ve clock edges | fishsoupisgood | 2018-05-17 | 1 | -1/+1 |
| * | only mute if all mute | root | 2018-05-17 | 1 | -1/+1 |
| * | minor fixes, make clock simulator happy and fix AS programming | root | 2018-05-17 | 5 | -18/+11 |
| * | tidy | James | 2018-05-17 | 8 | -256/+256 |
| * | working 3 detectors with parity checks | root | 2018-05-17 | 3 | -1/+206 |
| * | working 3 detectors with parity checks | root | 2018-05-17 | 6 | -154/+177 |
| * | add silence detection | fishsoupisgood | 2018-05-17 | 6 | -104/+96 |
| * | first version for rob - supports only 44.1kHz | fishsoupisgood | 2018-05-17 | 16 | -0/+1580 |
 |
index : misc/rob_spdif | |
| rob spdif hdl | James |
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