fish

28 files changed, 30061 insertions, 0 deletions

diff --git a/libopencm3/scripts/black_magic_probe_debug.scr b/libopencm3/scripts/black_magic_probe_debug.scr
new file mode 100644
index 0000000..0bf774c
--- /dev/null
+++ b/libopencm3/scripts/black_magic_probe_debug.scr
@@ -0,0 +1,4 @@
+monitor version
+monitor swdp_scan
+attach 1
+run
diff --git a/libopencm3/scripts/black_magic_probe_flash.scr b/libopencm3/scripts/black_magic_probe_flash.scr
new file mode 100644
index 0000000..27663c8
--- /dev/null
+++ b/libopencm3/scripts/black_magic_probe_flash.scr
@@ -0,0 +1,4 @@
+monitor version
+monitor swdp_scan
+attach 1
+load
diff --git a/libopencm3/scripts/checkpatch.pl b/libopencm3/scripts/checkpatch.pl
new file mode 100755
index 0000000..e76ed7c
--- /dev/null
+++ b/libopencm3/scripts/checkpatch.pl
@@ -0,0 +1,3731 @@
+#!/usr/bin/perl -w
+# (c) 2001, Dave Jones. (the file handling bit)
+# (c) 2005, Joel Schopp <jschopp@austin.ibm.com> (the ugly bit)
+# (c) 2007,2008, Andy Whitcroft <apw@uk.ibm.com> (new conditions, test suite)
+# (c) 2008-2010 Andy Whitcroft <apw@canonical.com>
+# Licensed under the terms of the GNU GPL License version 2
+
+use strict;
+
+my $P = $0;
+$P =~ s@.*/@@g;
+
+my $V = '0.32';
+
+use Getopt::Long qw(:config no_auto_abbrev);
+
+my $quiet = 0;
+my $tree = 1;
+my $chk_signoff = 1;
+my $chk_patch = 1;
+my $tst_only;
+my $emacs = 0;
+my $terse = 0;
+my $file = 0;
+my $check = 0;
+my $summary = 1;
+my $mailback = 0;
+my $summary_file = 0;
+my $show_types = 0;
+my $root;
+my %debug;
+my %ignore_type = ();
+my @ignore = ();
+my $help = 0;
+my $configuration_file = ".checkpatch.conf";
+my $max_line_length = 80;
+
+sub help {
+	my ($exitcode) = @_;
+
+	print << "EOM";
+Usage: $P [OPTION]... [FILE]...
+Version: $V
+
+Options:
+  -q, --quiet                quiet
+  --no-tree                  run without a kernel tree
+  --no-signoff               do not check for 'Signed-off-by' line
+  --patch                    treat FILE as patchfile (default)
+  --emacs                    emacs compile window format
+  --terse                    one line per report
+  -f, --file                 treat FILE as regular source file
+  --subjective, --strict     enable more subjective tests
+  --ignore TYPE(,TYPE2...)   ignore various comma separated message types
+  --max-line-length=n        set the maximum line length, if exceeded, warn
+  --show-types               show the message "types" in the output
+  --root=PATH                PATH to the kernel tree root
+  --no-summary               suppress the per-file summary
+  --mailback                 only produce a report in case of warnings/errors
+  --summary-file             include the filename in summary
+  --debug KEY=[0|1]          turn on/off debugging of KEY, where KEY is one of
+                             'values', 'possible', 'type', and 'attr' (default
+                             is all off)
+  --test-only=WORD           report only warnings/errors containing WORD
+                             literally
+  -h, --help, --version      display this help and exit
+
+When FILE is - read standard input.
+EOM
+
+	exit($exitcode);
+}
+
+my $conf = which_conf($configuration_file);
+if (-f $conf) {
+	my @conf_args;
+	open(my $conffile, '<', "$conf")
+	    or warn "$P: Can't find a readable $configuration_file file $!\n";
+
+	while (<$conffile>) {
+		my $line = $_;
+
+		$line =~ s/\s*\n?$//g;
+		$line =~ s/^\s*//g;
+		$line =~ s/\s+/ /g;
+
+		next if ($line =~ m/^\s*#/);
+		next if ($line =~ m/^\s*$/);
+
+		my @words = split(" ", $line);
+		foreach my $word (@words) {
+			last if ($word =~ m/^#/);
+			push (@conf_args, $word);
+		}
+	}
+	close($conffile);
+	unshift(@ARGV, @conf_args) if @conf_args;
+}
+
+GetOptions(
+	'q|quiet+'	=> \$quiet,
+	'tree!'		=> \$tree,
+	'signoff!'	=> \$chk_signoff,
+	'patch!'	=> \$chk_patch,
+	'emacs!'	=> \$emacs,
+	'terse!'	=> \$terse,
+	'f|file!'	=> \$file,
+	'subjective!'	=> \$check,
+	'strict!'	=> \$check,
+	'ignore=s'	=> \@ignore,
+	'show-types!'	=> \$show_types,
+	'max-line-length=i' => \$max_line_length,
+	'root=s'	=> \$root,
+	'summary!'	=> \$summary,
+	'mailback!'	=> \$mailback,
+	'summary-file!'	=> \$summary_file,
+
+	'debug=s'	=> \%debug,
+	'test-only=s'	=> \$tst_only,
+	'h|help'	=> \$help,
+	'version'	=> \$help
+) or help(1);
+
+help(0) if ($help);
+
+my $exit = 0;
+
+if ($#ARGV < 0) {
+	print "$P: no input files\n";
+	exit(1);
+}
+
+@ignore = split(/,/, join(',',@ignore));
+foreach my $word (@ignore) {
+	$word =~ s/\s*\n?$//g;
+	$word =~ s/^\s*//g;
+	$word =~ s/\s+/ /g;
+	$word =~ tr/[a-z]/[A-Z]/;
+
+	next if ($word =~ m/^\s*#/);
+	next if ($word =~ m/^\s*$/);
+
+	$ignore_type{$word}++;
+}
+
+my $dbg_values = 0;
+my $dbg_possible = 0;
+my $dbg_type = 0;
+my $dbg_attr = 0;
+for my $key (keys %debug) {
+	## no critic
+	eval "\${dbg_$key} = '$debug{$key}';";
+	die "$@" if ($@);
+}
+
+my $rpt_cleaners = 0;
+
+if ($terse) {
+	$emacs = 1;
+	$quiet++;
+}
+
+if ($tree) {
+	if (defined $root) {
+		if (!top_of_kernel_tree($root)) {
+			die "$P: $root: --root does not point at a valid tree\n";
+		}
+	} else {
+		if (top_of_kernel_tree('.')) {
+			$root = '.';
+		} elsif ($0 =~ m@(.*)/scripts/[^/]*$@ &&
+						top_of_kernel_tree($1)) {
+			$root = $1;
+		}
+	}
+
+	if (!defined $root) {
+		print "Must be run from the top-level dir. of a kernel tree\n";
+		exit(2);
+	}
+}
+
+my $emitted_corrupt = 0;
+
+our $Ident	= qr{
+			[A-Za-z_][A-Za-z\d_]*
+			(?:\s*\#\#\s*[A-Za-z_][A-Za-z\d_]*)*
+		}x;
+our $Storage	= qr{extern|static|asmlinkage};
+our $Sparse	= qr{
+			__user|
+			__kernel|
+			__force|
+			__iomem|
+			__must_check|
+			__init_refok|
+			__kprobes|
+			__ref|
+			__rcu
+		}x;
+
+# Notes to $Attribute:
+# We need \b after 'init' otherwise 'initconst' will cause a false positive in a check
+our $Attribute	= qr{
+			const|
+			__percpu|
+			__nocast|
+			__safe|
+			__bitwise__|
+			__packed__|
+			__packed2__|
+			__naked|
+			__maybe_unused|
+			__always_unused|
+			__noreturn|
+			__used|
+			__cold|
+			__noclone|
+			__deprecated|
+			__read_mostly|
+			__kprobes|
+			__(?:mem|cpu|dev|)(?:initdata|initconst|init\b)|
+			____cacheline_aligned|
+			____cacheline_aligned_in_smp|
+			____cacheline_internodealigned_in_smp|
+			__weak
+		  }x;
+our $Modifier;
+our $Inline	= qr{inline|__always_inline|noinline};
+our $Member	= qr{->$Ident|\.$Ident|\[[^]]*\]};
+our $Lval	= qr{$Ident(?:$Member)*};
+
+our $Float_hex	= qr{(?i)0x[0-9a-f]+p-?[0-9]+[fl]?};
+our $Float_dec	= qr{(?i)(?:[0-9]+\.[0-9]*|[0-9]*\.[0-9]+)(?:e-?[0-9]+)?[fl]?};
+our $Float_int	= qr{(?i)[0-9]+e-?[0-9]+[fl]?};
+our $Float	= qr{$Float_hex|$Float_dec|$Float_int};
+our $Constant	= qr{$Float|(?i)(?:0x[0-9a-f]+|[0-9]+)[ul]*};
+our $Assignment	= qr{\*\=|/=|%=|\+=|-=|<<=|>>=|&=|\^=|\|=|=};
+our $Compare    = qr{<=|>=|==|!=|<|>};
+our $Operators	= qr{
+			<=|>=|==|!=|
+			=>|->|<<|>>|<|>|!|~|
+			&&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|%
+		  }x;
+
+our $NonptrType;
+our $Type;
+our $Declare;
+
+our $NON_ASCII_UTF8	= qr{
+	[\xC2-\xDF][\x80-\xBF]               # non-overlong 2-byte
+	|  \xE0[\xA0-\xBF][\x80-\xBF]        # excluding overlongs
+	| [\xE1-\xEC\xEE\xEF][\x80-\xBF]{2}  # straight 3-byte
+	|  \xED[\x80-\x9F][\x80-\xBF]        # excluding surrogates
+	|  \xF0[\x90-\xBF][\x80-\xBF]{2}     # planes 1-3
+	| [\xF1-\xF3][\x80-\xBF]{3}          # planes 4-15
+	|  \xF4[\x80-\x8F][\x80-\xBF]{2}     # plane 16
+}x;
+
+our $UTF8	= qr{
+	[\x09\x0A\x0D\x20-\x7E]              # ASCII
+	| $NON_ASCII_UTF8
+}x;
+
+our $typeTypedefs = qr{(?x:
+	(?:__)?(?:u|s|be|le)(?:8|16|32|64)|
+	atomic_t
+)};
+
+our $logFunctions = qr{(?x:
+	printk(?:_ratelimited|_once|)|
+	[a-z0-9]+_(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)|
+	WARN(?:_RATELIMIT|_ONCE|)|
+	panic|
+	MODULE_[A-Z_]+
+)};
+
+our $signature_tags = qr{(?xi:
+	Signed-off-by:|
+	Acked-by:|
+	Tested-by:|
+	Reviewed-by:|
+	Reported-by:|
+	Suggested-by:|
+	To:|
+	Cc:
+)};
+
+our @typeList = (
+	qr{void},
+	qr{(?:unsigned\s+)?char},
+	qr{(?:unsigned\s+)?short},
+	qr{(?:unsigned\s+)?int},
+	qr{(?:unsigned\s+)?long},
+	qr{(?:unsigned\s+)?long\s+int},
+	qr{(?:unsigned\s+)?long\s+long},
+	qr{(?:unsigned\s+)?long\s+long\s+int},
+	qr{unsigned},
+	qr{float},
+	qr{double},
+	qr{bool},
+	qr{struct\s+$Ident},
+	qr{union\s+$Ident},
+	qr{enum\s+$Ident},
+	qr{${Ident}_t},
+	qr{${Ident}_handler},
+	qr{${Ident}_handler_fn},
+);
+our @modifierList = (
+	qr{fastcall},
+);
+
+our $allowed_asm_includes = qr{(?x:
+	irq|
+	memory
+)};
+# memory.h: ARM has a custom one
+
+sub build_types {
+	my $mods = "(?x:  \n" . join("|\n  ", @modifierList) . "\n)";
+	my $all = "(?x:  \n" . join("|\n  ", @typeList) . "\n)";
+	$Modifier	= qr{(?:$Attribute|$Sparse|$mods)};
+	$NonptrType	= qr{
+			(?:$Modifier\s+|const\s+)*
+			(?:
+				(?:typeof|__typeof__)\s*\([^\)]*\)|
+				(?:$typeTypedefs\b)|
+				(?:${all}\b)
+			)
+			(?:\s+$Modifier|\s+const)*
+		  }x;
+	$Type	= qr{
+			$NonptrType
+			(?:(?:\s|\*|\[\])+\s*const|(?:\s|\*|\[\])+|(?:\s*\[\s*\])+)?
+			(?:\s+$Inline|\s+$Modifier)*
+		  }x;
+	$Declare	= qr{(?:$Storage\s+)?$Type};
+}
+build_types();
+
+
+our $Typecast	= qr{\s*(\(\s*$NonptrType\s*\)){0,1}\s*};
+
+# Using $balanced_parens, $LvalOrFunc, or $FuncArg
+# requires at least perl version v5.10.0
+# Any use must be runtime checked with $^V
+
+our $balanced_parens = qr/(\((?:[^\(\)]++|(?-1))*\))/;
+our $LvalOrFunc	= qr{($Lval)\s*($balanced_parens{0,1})\s*};
+our $FuncArg = qr{$Typecast{0,1}($LvalOrFunc|$Constant)};
+
+sub deparenthesize {
+	my ($string) = @_;
+	return "" if (!defined($string));
+	$string =~ s@^\s*\(\s*@@g;
+	$string =~ s@\s*\)\s*$@@g;
+	$string =~ s@\s+@ @g;
+	return $string;
+}
+
+$chk_signoff = 0 if ($file);
+
+my @rawlines = ();
+my @lines = ();
+my $vname;
+for my $filename (@ARGV) {
+	my $FILE;
+	if ($file) {
+		open($FILE, '-|', "diff -u /dev/null $filename") ||
+			die "$P: $filename: diff failed - $!\n";
+	} elsif ($filename eq '-') {
+		open($FILE, '<&STDIN');
+	} else {
+		open($FILE, '<', "$filename") ||
+			die "$P: $filename: open failed - $!\n";
+	}
+	if ($filename eq '-') {
+		$vname = 'Your patch';
+	} else {
+		$vname = $filename;
+	}
+	while (<$FILE>) {
+		chomp;
+		push(@rawlines, $_);
+	}
+	close($FILE);
+	if (!process($filename)) {
+		$exit = 1;
+	}
+	@rawlines = ();
+	@lines = ();
+}
+
+exit($exit);
+
+sub top_of_kernel_tree {
+	my ($root) = @_;
+
+	my @tree_check = (
+		"COPYING", "CREDITS", "Kbuild", "MAINTAINERS", "Makefile",
+		"README", "Documentation", "arch", "include", "drivers",
+		"fs", "init", "ipc", "kernel", "lib", "scripts",
+	);
+
+	foreach my $check (@tree_check) {
+		if (! -e $root . '/' . $check) {
+			return 0;
+		}
+	}
+	return 1;
+}
+
+sub parse_email {
+	my ($formatted_email) = @_;
+
+	my $name = "";
+	my $address = "";
+	my $comment = "";
+
+	if ($formatted_email =~ /^(.*)<(\S+\@\S+)>(.*)$/) {
+		$name = $1;
+		$address = $2;
+		$comment = $3 if defined $3;
+	} elsif ($formatted_email =~ /^\s*<(\S+\@\S+)>(.*)$/) {
+		$address = $1;
+		$comment = $2 if defined $2;
+	} elsif ($formatted_email =~ /(\S+\@\S+)(.*)$/) {
+		$address = $1;
+		$comment = $2 if defined $2;
+		$formatted_email =~ s/$address.*$//;
+		$name = $formatted_email;
+		$name =~ s/^\s+|\s+$//g;
+		$name =~ s/^\"|\"$//g;
+		# If there's a name left after stripping spaces and
+		# leading quotes, and the address doesn't have both
+		# leading and trailing angle brackets, the address
+		# is invalid. ie:
+		#   "joe smith joe@smith.com" bad
+		#   "joe smith <joe@smith.com" bad
+		if ($name ne "" && $address !~ /^<[^>]+>$/) {
+			$name = "";
+			$address = "";
+			$comment = "";
+		}
+	}
+
+	$name =~ s/^\s+|\s+$//g;
+	$name =~ s/^\"|\"$//g;
+	$address =~ s/^\s+|\s+$//g;
+	$address =~ s/^\<|\>$//g;
+
+	if ($name =~ /[^\w \-]/i) { ##has "must quote" chars
+		$name =~ s/(?<!\\)"/\\"/g; ##escape quotes
+		$name = "\"$name\"";
+	}
+
+	return ($name, $address, $comment);
+}
+
+sub format_email {
+	my ($name, $address) = @_;
+
+	my $formatted_email;
+
+	$name =~ s/^\s+|\s+$//g;
+	$name =~ s/^\"|\"$//g;
+	$address =~ s/^\s+|\s+$//g;
+
+	if ($name =~ /[^\w \-]/i) { ##has "must quote" chars
+		$name =~ s/(?<!\\)"/\\"/g; ##escape quotes
+		$name = "\"$name\"";
+	}
+
+	if ("$name" eq "") {
+		$formatted_email = "$address";
+	} else {
+		$formatted_email = "$name <$address>";
+	}
+
+	return $formatted_email;
+}
+
+sub which_conf {
+	my ($conf) = @_;
+
+	foreach my $path (split(/:/, ".:$ENV{HOME}:.scripts")) {
+		if (-e "$path/$conf") {
+			return "$path/$conf";
+		}
+	}
+
+	return "";
+}
+
+sub expand_tabs {
+	my ($str) = @_;
+
+	my $res = '';
+	my $n = 0;
+	for my $c (split(//, $str)) {
+		if ($c eq "\t") {
+			$res .= ' ';
+			$n++;
+			for (; ($n % 8) != 0; $n++) {
+				$res .= ' ';
+			}
+			next;
+		}
+		$res .= $c;
+		$n++;
+	}
+
+	return $res;
+}
+sub copy_spacing {
+	(my $res = shift) =~ tr/\t/ /c;
+	return $res;
+}
+
+sub line_stats {
+	my ($line) = @_;
+
+	# Drop the diff line leader and expand tabs
+	$line =~ s/^.//;
+	$line = expand_tabs($line);
+
+	# Pick the indent from the front of the line.
+	my ($white) = ($line =~ /^(\s*)/);
+
+	return (length($line), length($white));
+}
+
+my $sanitise_quote = '';
+
+sub sanitise_line_reset {
+	my ($in_comment) = @_;
+
+	if ($in_comment) {
+		$sanitise_quote = '*/';
+	} else {
+		$sanitise_quote = '';
+	}
+}
+sub sanitise_line {
+	my ($line) = @_;
+
+	my $res = '';
+	my $l = '';
+
+	my $qlen = 0;
+	my $off = 0;
+	my $c;
+
+	# Always copy over the diff marker.
+	$res = substr($line, 0, 1);
+
+	for ($off = 1; $off < length($line); $off++) {
+		$c = substr($line, $off, 1);
+
+		# Comments we are wacking completly including the begin
+		# and end, all to $;.
+		if ($sanitise_quote eq '' && substr($line, $off, 2) eq '/*') {
+			$sanitise_quote = '*/';
+
+			substr($res, $off, 2, "$;$;");
+			$off++;
+			next;
+		}
+		if ($sanitise_quote eq '*/' && substr($line, $off, 2) eq '*/') {
+			$sanitise_quote = '';
+			substr($res, $off, 2, "$;$;");
+			$off++;
+			next;
+		}
+		if ($sanitise_quote eq '' && substr($line, $off, 2) eq '//') {
+			$sanitise_quote = '//';
+
+			substr($res, $off, 2, $sanitise_quote);
+			$off++;
+			next;
+		}
+
+		# A \ in a string means ignore the next character.
+		if (($sanitise_quote eq "'" || $sanitise_quote eq '"') &&
+		    $c eq "\\") {
+			substr($res, $off, 2, 'XX');
+			$off++;
+			next;
+		}
+		# Regular quotes.
+		if ($c eq "'" || $c eq '"') {
+			if ($sanitise_quote eq '') {
+				$sanitise_quote = $c;
+
+				substr($res, $off, 1, $c);
+				next;
+			} elsif ($sanitise_quote eq $c) {
+				$sanitise_quote = '';
+			}
+		}
+
+		#print "c<$c> SQ<$sanitise_quote>\n";
+		if ($off != 0 && $sanitise_quote eq '*/' && $c ne "\t") {
+			substr($res, $off, 1, $;);
+		} elsif ($off != 0 && $sanitise_quote eq '//' && $c ne "\t") {
+			substr($res, $off, 1, $;);
+		} elsif ($off != 0 && $sanitise_quote && $c ne "\t") {
+			substr($res, $off, 1, 'X');
+		} else {
+			substr($res, $off, 1, $c);
+		}
+	}
+
+	if ($sanitise_quote eq '//') {
+		$sanitise_quote = '';
+	}
+
+	# The pathname on a #include may be surrounded by '<' and '>'.
+	if ($res =~ /^.\s*\#\s*include\s+\<(.*)\>/) {
+		my $clean = 'X' x length($1);
+		$res =~ s@\<.*\>@<$clean>@;
+
+	# The whole of a #error is a string.
+	} elsif ($res =~ /^.\s*\#\s*(?:error|warning)\s+(.*)\b/) {
+		my $clean = 'X' x length($1);
+		$res =~ s@(\#\s*(?:error|warning)\s+).*@$1$clean@;
+	}
+
+	return $res;
+}
+
+sub get_quoted_string {
+	my ($line, $rawline) = @_;
+
+	return "" if ($line !~ m/(\"[X]+\")/g);
+	return substr($rawline, $-[0], $+[0] - $-[0]);
+}
+
+sub ctx_statement_block {
+	my ($linenr, $remain, $off) = @_;
+	my $line = $linenr - 1;
+	my $blk = '';
+	my $soff = $off;
+	my $coff = $off - 1;
+	my $coff_set = 0;
+
+	my $loff = 0;
+
+	my $type = '';
+	my $level = 0;
+	my @stack = ();
+	my $p;
+	my $c;
+	my $len = 0;
+
+	my $remainder;
+	while (1) {
+		@stack = (['', 0]) if ($#stack == -1);
+
+		#warn "CSB: blk<$blk> remain<$remain>\n";
+		# If we are about to drop off the end, pull in more
+		# context.
+		if ($off >= $len) {
+			for (; $remain > 0; $line++) {
+				last if (!defined $lines[$line]);
+				next if ($lines[$line] =~ /^-/);
+				$remain--;
+				$loff = $len;
+				$blk .= $lines[$line] . "\n";
+				$len = length($blk);
+				$line++;
+				last;
+			}
+			# Bail if there is no further context.
+			#warn "CSB: blk<$blk> off<$off> len<$len>\n";
+			if ($off >= $len) {
+				last;
+			}
+			if ($level == 0 && substr($blk, $off) =~ /^.\s*#\s*define/) {
+				$level++;
+				$type = '#';
+			}
+		}
+		$p = $c;
+		$c = substr($blk, $off, 1);
+		$remainder = substr($blk, $off);
+
+		#warn "CSB: c<$c> type<$type> level<$level> remainder<$remainder> coff_set<$coff_set>\n";
+
+		# Handle nested #if/#else.
+		if ($remainder =~ /^#\s*(?:ifndef|ifdef|if)\s/) {
+			push(@stack, [ $type, $level ]);
+		} elsif ($remainder =~ /^#\s*(?:else|elif)\b/) {
+			($type, $level) = @{$stack[$#stack - 1]};
+		} elsif ($remainder =~ /^#\s*endif\b/) {
+			($type, $level) = @{pop(@stack)};
+		}
+
+		# Statement ends at the ';' or a close '}' at the
+		# outermost level.
+		if ($level == 0 && $c eq ';') {
+			last;
+		}
+
+		# An else is really a conditional as long as its not else if
+		if ($level == 0 && $coff_set == 0 &&
+				(!defined($p) || $p =~ /(?:\s|\}|\+)/) &&
+				$remainder =~ /^(else)(?:\s|{)/ &&
+				$remainder !~ /^else\s+if\b/) {
+			$coff = $off + length($1) - 1;
+			$coff_set = 1;
+			#warn "CSB: mark coff<$coff> soff<$soff> 1<$1>\n";
+			#warn "[" . substr($blk, $soff, $coff - $soff + 1) . "]\n";
+		}
+
+		if (($type eq '' || $type eq '(') && $c eq '(') {
+			$level++;
+			$type = '(';
+		}
+		if ($type eq '(' && $c eq ')') {
+			$level--;
+			$type = ($level != 0)? '(' : '';
+
+			if ($level == 0 && $coff < $soff) {
+				$coff = $off;
+				$coff_set = 1;
+				#warn "CSB: mark coff<$coff>\n";
+			}
+		}
+		if (($type eq '' || $type eq '{') && $c eq '{') {
+			$level++;
+			$type = '{';
+		}
+		if ($type eq '{' && $c eq '}') {
+			$level--;
+			$type = ($level != 0)? '{' : '';
+
+			if ($level == 0) {
+				if (substr($blk, $off + 1, 1) eq ';') {
+					$off++;
+				}
+				last;
+			}
+		}
+		# Preprocessor commands end at the newline unless escaped.
+		if ($type eq '#' && $c eq "\n" && $p ne "\\") {
+			$level--;
+			$type = '';
+			$off++;
+			last;
+		}
+		$off++;
+	}
+	# We are truly at the end, so shuffle to the next line.
+	if ($off == $len) {
+		$loff = $len + 1;
+		$line++;
+		$remain--;
+	}
+
+	my $statement = substr($blk, $soff, $off - $soff + 1);
+	my $condition = substr($blk, $soff, $coff - $soff + 1);
+
+	#warn "STATEMENT<$statement>\n";
+	#warn "CONDITION<$condition>\n";
+
+	#print "coff<$coff> soff<$off> loff<$loff>\n";
+
+	return ($statement, $condition,
+			$line, $remain + 1, $off - $loff + 1, $level);
+}
+
+sub statement_lines {
+	my ($stmt) = @_;
+
+	# Strip the diff line prefixes and rip blank lines at start and end.
+	$stmt =~ s/(^|\n)./$1/g;
+	$stmt =~ s/^\s*//;
+	$stmt =~ s/\s*$//;
+
+	my @stmt_lines = ($stmt =~ /\n/g);
+
+	return $#stmt_lines + 2;
+}
+
+sub statement_rawlines {
+	my ($stmt) = @_;
+
+	my @stmt_lines = ($stmt =~ /\n/g);
+
+	return $#stmt_lines + 2;
+}
+
+sub statement_block_size {
+	my ($stmt) = @_;
+
+	$stmt =~ s/(^|\n)./$1/g;
+	$stmt =~ s/^\s*{//;
+	$stmt =~ s/}\s*$//;
+	$stmt =~ s/^\s*//;
+	$stmt =~ s/\s*$//;
+
+	my @stmt_lines = ($stmt =~ /\n/g);
+	my @stmt_statements = ($stmt =~ /;/g);
+
+	my $stmt_lines = $#stmt_lines + 2;
+	my $stmt_statements = $#stmt_statements + 1;
+
+	if ($stmt_lines > $stmt_statements) {
+		return $stmt_lines;
+	} else {
+		return $stmt_statements;
+	}
+}
+
+sub ctx_statement_full {
+	my ($linenr, $remain, $off) = @_;
+	my ($statement, $condition, $level);
+
+	my (@chunks);
+
+	# Grab the first conditional/block pair.
+	($statement, $condition, $linenr, $remain, $off, $level) =
+				ctx_statement_block($linenr, $remain, $off);
+	#print "F: c<$condition> s<$statement> remain<$remain>\n";
+	push(@chunks, [ $condition, $statement ]);
+	if (!($remain > 0 && $condition =~ /^\s*(?:\n[+-])?\s*(?:if|else|do)\b/s)) {
+		return ($level, $linenr, @chunks);
+	}
+
+	# Pull in the following conditional/block pairs and see if they
+	# could continue the statement.
+	for (;;) {
+		($statement, $condition, $linenr, $remain, $off, $level) =
+				ctx_statement_block($linenr, $remain, $off);
+		#print "C: c<$condition> s<$statement> remain<$remain>\n";
+		last if (!($remain > 0 && $condition =~ /^(?:\s*\n[+-])*\s*(?:else|do)\b/s));
+		#print "C: push\n";
+		push(@chunks, [ $condition, $statement ]);
+	}
+
+	return ($level, $linenr, @chunks);
+}
+
+sub ctx_block_get {
+	my ($linenr, $remain, $outer, $open, $close, $off) = @_;
+	my $line;
+	my $start = $linenr - 1;
+	my $blk = '';
+	my @o;
+	my @c;
+	my @res = ();
+
+	my $level = 0;
+	my @stack = ($level);
+	for ($line = $start; $remain > 0; $line++) {
+		next if ($rawlines[$line] =~ /^-/);
+		$remain--;
+
+		$blk .= $rawlines[$line];
+
+		# Handle nested #if/#else.
+		if ($lines[$line] =~ /^.\s*#\s*(?:ifndef|ifdef|if)\s/) {
+			push(@stack, $level);
+		} elsif ($lines[$line] =~ /^.\s*#\s*(?:else|elif)\b/) {
+			$level = $stack[$#stack - 1];
+		} elsif ($lines[$line] =~ /^.\s*#\s*endif\b/) {
+			$level = pop(@stack);
+		}
+
+		foreach my $c (split(//, $lines[$line])) {
+			##print "C<$c>L<$level><$open$close>O<$off>\n";
+			if ($off > 0) {
+				$off--;
+				next;
+			}
+
+			if ($c eq $close && $level > 0) {
+				$level--;
+				last if ($level == 0);
+			} elsif ($c eq $open) {
+				$level++;
+			}
+		}
+
+		if (!$outer || $level <= 1) {
+			push(@res, $rawlines[$line]);
+		}
+
+		last if ($level == 0);
+	}
+
+	return ($level, @res);
+}
+sub ctx_block_outer {
+	my ($linenr, $remain) = @_;
+
+	my ($level, @r) = ctx_block_get($linenr, $remain, 1, '{', '}', 0);
+	return @r;
+}
+sub ctx_block {
+	my ($linenr, $remain) = @_;
+
+	my ($level, @r) = ctx_block_get($linenr, $remain, 0, '{', '}', 0);
+	return @r;
+}
+sub ctx_statement {
+	my ($linenr, $remain, $off) = @_;
+
+	my ($level, @r) = ctx_block_get($linenr, $remain, 0, '(', ')', $off);
+	return @r;
+}
+sub ctx_block_level {
+	my ($linenr, $remain) = @_;
+
+	return ctx_block_get($linenr, $remain, 0, '{', '}', 0);
+}
+sub ctx_statement_level {
+	my ($linenr, $remain, $off) = @_;
+
+	return ctx_block_get($linenr, $remain, 0, '(', ')', $off);
+}
+
+sub ctx_locate_comment {
+	my ($first_line, $end_line) = @_;
+
+	# Catch a comment on the end of the line itself.
+	my ($current_comment) = ($rawlines[$end_line - 1] =~ m@.*(/\*.*\*/)\s*(?:\\\s*)?$@);
+	return $current_comment if (defined $current_comment);
+
+	# Look through the context and try and figure out if there is a
+	# comment.
+	my $in_comment = 0;
+	$current_comment = '';
+	for (my $linenr = $first_line; $linenr < $end_line; $linenr++) {
+		my $line = $rawlines[$linenr - 1];
+		#warn "           $line\n";
+		if ($linenr == $first_line and $line =~ m@^.\s*\*@) {
+			$in_comment = 1;
+		}
+		if ($line =~ m@/\*@) {
+			$in_comment = 1;
+		}
+		if (!$in_comment && $current_comment ne '') {
+			$current_comment = '';
+		}
+		$current_comment .= $line . "\n" if ($in_comment);
+		if ($line =~ m@\*/@) {
+			$in_comment = 0;
+		}
+	}
+
+	chomp($current_comment);
+	return($current_comment);
+}
+sub ctx_has_comment {
+	my ($first_line, $end_line) = @_;
+	my $cmt = ctx_locate_comment($first_line, $end_line);
+
+	##print "LINE: $rawlines[$end_line - 1 ]\n";
+	##print "CMMT: $cmt\n";
+
+	return ($cmt ne '');
+}
+
+sub raw_line {
+	my ($linenr, $cnt) = @_;
+
+	my $offset = $linenr - 1;
+	$cnt++;
+
+	my $line;
+	while ($cnt) {
+		$line = $rawlines[$offset++];
+		next if (defined($line) && $line =~ /^-/);
+		$cnt--;
+	}
+
+	return $line;
+}
+
+sub cat_vet {
+	my ($vet) = @_;
+	my ($res, $coded);
+
+	$res = '';
+	while ($vet =~ /([^[:cntrl:]]*)([[:cntrl:]]|$)/g) {
+		$res .= $1;
+		if ($2 ne '') {
+			$coded = sprintf("^%c", unpack('C', $2) + 64);
+			$res .= $coded;
+		}
+	}
+	$res =~ s/$/\$/;
+
+	return $res;
+}
+
+my $av_preprocessor = 0;
+my $av_pending;
+my @av_paren_type;
+my $av_pend_colon;
+
+sub annotate_reset {
+	$av_preprocessor = 0;
+	$av_pending = '_';
+	@av_paren_type = ('E');
+	$av_pend_colon = 'O';
+}
+
+sub annotate_values {
+	my ($stream, $type) = @_;
+
+	my $res;
+	my $var = '_' x length($stream);
+	my $cur = $stream;
+
+	print "$stream\n" if ($dbg_values > 1);
+
+	while (length($cur)) {
+		@av_paren_type = ('E') if ($#av_paren_type < 0);
+		print " <" . join('', @av_paren_type) .
+				"> <$type> <$av_pending>" if ($dbg_values > 1);
+		if ($cur =~ /^(\s+)/o) {
+			print "WS($1)\n" if ($dbg_values > 1);
+			if ($1 =~ /\n/ && $av_preprocessor) {
+				$type = pop(@av_paren_type);
+				$av_preprocessor = 0;
+			}
+
+		} elsif ($cur =~ /^(\(\s*$Type\s*)\)/ && $av_pending eq '_') {
+			print "CAST($1)\n" if ($dbg_values > 1);
+			push(@av_paren_type, $type);
+			$type = 'c';
+
+		} elsif ($cur =~ /^($Type)\s*(?:$Ident|,|\)|\(|\s*$)/) {
+			print "DECLARE($1)\n" if ($dbg_values > 1);
+			$type = 'T';
+
+		} elsif ($cur =~ /^($Modifier)\s*/) {
+			print "MODIFIER($1)\n" if ($dbg_values > 1);
+			$type = 'T';
+
+		} elsif ($cur =~ /^(\#\s*define\s*$Ident)(\(?)/o) {
+			print "DEFINE($1,$2)\n" if ($dbg_values > 1);
+			$av_preprocessor = 1;
+			push(@av_paren_type, $type);
+			if ($2 ne '') {
+				$av_pending = 'N';
+			}
+			$type = 'E';
+
+		} elsif ($cur =~ /^(\#\s*(?:undef\s*$Ident|include\b))/o) {
+			print "UNDEF($1)\n" if ($dbg_values > 1);
+			$av_preprocessor = 1;
+			push(@av_paren_type, $type);
+
+		} elsif ($cur =~ /^(\#\s*(?:ifdef|ifndef|if))/o) {
+			print "PRE_START($1)\n" if ($dbg_values > 1);
+			$av_preprocessor = 1;
+
+			push(@av_paren_type, $type);
+			push(@av_paren_type, $type);
+			$type = 'E';
+
+		} elsif ($cur =~ /^(\#\s*(?:else|elif))/o) {
+			print "PRE_RESTART($1)\n" if ($dbg_values > 1);
+			$av_preprocessor = 1;
+
+			push(@av_paren_type, $av_paren_type[$#av_paren_type]);
+
+			$type = 'E';
+
+		} elsif ($cur =~ /^(\#\s*(?:endif))/o) {
+			print "PRE_END($1)\n" if ($dbg_values > 1);
+
+			$av_preprocessor = 1;
+
+			# Assume all arms of the conditional end as this
+			# one does, and continue as if the #endif was not here.
+			pop(@av_paren_type);
+			push(@av_paren_type, $type);
+			$type = 'E';
+
+		} elsif ($cur =~ /^(\\\n)/o) {
+			print "PRECONT($1)\n" if ($dbg_values > 1);
+
+		} elsif ($cur =~ /^(__attribute__)\s*\(?/o) {
+			print "ATTR($1)\n" if ($dbg_values > 1);
+			$av_pending = $type;
+			$type = 'N';
+
+		} elsif ($cur =~ /^(sizeof)\s*(\()?/o) {
+			print "SIZEOF($1)\n" if ($dbg_values > 1);
+			if (defined $2) {
+				$av_pending = 'V';
+			}
+			$type = 'N';
+
+		} elsif ($cur =~ /^(if|while|for)\b/o) {
+			print "COND($1)\n" if ($dbg_values > 1);
+			$av_pending = 'E';
+			$type = 'N';
+
+		} elsif ($cur =~/^(case)/o) {
+			print "CASE($1)\n" if ($dbg_values > 1);
+			$av_pend_colon = 'C';
+			$type = 'N';
+
+		} elsif ($cur =~/^(return|else|goto|typeof|__typeof__)\b/o) {
+			print "KEYWORD($1)\n" if ($dbg_values > 1);
+			$type = 'N';
+
+		} elsif ($cur =~ /^(\()/o) {
+			print "PAREN('$1')\n" if ($dbg_values > 1);
+			push(@av_paren_type, $av_pending);
+			$av_pending = '_';
+			$type = 'N';
+
+		} elsif ($cur =~ /^(\))/o) {
+			my $new_type = pop(@av_paren_type);
+			if ($new_type ne '_') {
+				$type = $new_type;
+				print "PAREN('$1') -> $type\n"
+							if ($dbg_values > 1);
+			} else {
+				print "PAREN('$1')\n" if ($dbg_values > 1);
+			}
+
+		} elsif ($cur =~ /^($Ident)\s*\(/o) {
+			print "FUNC($1)\n" if ($dbg_values > 1);
+			$type = 'V';
+			$av_pending = 'V';
+
+		} elsif ($cur =~ /^($Ident\s*):(?:\s*\d+\s*(,|=|;))?/) {
+			if (defined $2 && $type eq 'C' || $type eq 'T') {
+				$av_pend_colon = 'B';
+			} elsif ($type eq 'E') {
+				$av_pend_colon = 'L';
+			}
+			print "IDENT_COLON($1,$type>$av_pend_colon)\n" if ($dbg_values > 1);
+			$type = 'V';
+
+		} elsif ($cur =~ /^($Ident|$Constant)/o) {
+			print "IDENT($1)\n" if ($dbg_values > 1);
+			$type = 'V';
+
+		} elsif ($cur =~ /^($Assignment)/o) {
+			print "ASSIGN($1)\n" if ($dbg_values > 1);
+			$type = 'N';
+
+		} elsif ($cur =~/^(;|{|})/) {
+			print "END($1)\n" if ($dbg_values > 1);
+			$type = 'E';
+			$av_pend_colon = 'O';
+
+		} elsif ($cur =~/^(,)/) {
+			print "COMMA($1)\n" if ($dbg_values > 1);
+			$type = 'C';
+
+		} elsif ($cur =~ /^(\?)/o) {
+			print "QUESTION($1)\n" if ($dbg_values > 1);
+			$type = 'N';
+
+		} elsif ($cur =~ /^(:)/o) {
+			print "COLON($1,$av_pend_colon)\n" if ($dbg_values > 1);
+
+			substr($var, length($res), 1, $av_pend_colon);
+			if ($av_pend_colon eq 'C' || $av_pend_colon eq 'L') {
+				$type = 'E';
+			} else {
+				$type = 'N';
+			}
+			$av_pend_colon = 'O';
+
+		} elsif ($cur =~ /^(\[)/o) {
+			print "CLOSE($1)\n" if ($dbg_values > 1);
+			$type = 'N';
+
+		} elsif ($cur =~ /^(-(?![->])|\+(?!\+)|\*|\&\&|\&)/o) {
+			my $variant;
+
+			print "OPV($1)\n" if ($dbg_values > 1);
+			if ($type eq 'V') {
+				$variant = 'B';
+			} else {
+				$variant = 'U';
+			}
+
+			substr($var, length($res), 1, $variant);
+			$type = 'N';
+
+		} elsif ($cur =~ /^($Operators)/o) {
+			print "OP($1)\n" if ($dbg_values > 1);
+			if ($1 ne '++' && $1 ne '--') {
+				$type = 'N';
+			}
+
+		} elsif ($cur =~ /(^.)/o) {
+			print "C($1)\n" if ($dbg_values > 1);
+		}
+		if (defined $1) {
+			$cur = substr($cur, length($1));
+			$res .= $type x length($1);
+		}
+	}
+
+	return ($res, $var);
+}
+
+sub possible {
+	my ($possible, $line) = @_;
+	my $notPermitted = qr{(?:
+		^(?:
+			$Modifier|
+			$Storage|
+			$Type|
+			DEFINE_\S+
+		)$|
+		^(?:
+			goto|
+			return|
+			case|
+			else|
+			asm|__asm__|
+			do|
+			\#|
+			\#\#|
+		)(?:\s|$)|
+		^(?:typedef|struct|enum)\b
+	    )}x;
+	warn "CHECK<$possible> ($line)\n" if ($dbg_possible > 2);
+	if ($possible !~ $notPermitted) {
+		# Check for modifiers.
+		$possible =~ s/\s*$Storage\s*//g;
+		$possible =~ s/\s*$Sparse\s*//g;
+		if ($possible =~ /^\s*$/) {
+
+		} elsif ($possible =~ /\s/) {
+			$possible =~ s/\s*$Type\s*//g;
+			for my $modifier (split(' ', $possible)) {
+				if ($modifier !~ $notPermitted) {
+					warn "MODIFIER: $modifier ($possible) ($line)\n" if ($dbg_possible);
+					push(@modifierList, $modifier);
+				}
+			}
+
+		} else {
+			warn "POSSIBLE: $possible ($line)\n" if ($dbg_possible);
+			push(@typeList, $possible);
+		}
+		build_types();
+	} else {
+		warn "NOTPOSS: $possible ($line)\n" if ($dbg_possible > 1);
+	}
+}
+
+my $prefix = '';
+
+sub show_type {
+       return !defined $ignore_type{$_[0]};
+}
+
+sub report {
+	if (!show_type($_[1]) ||
+	    (defined $tst_only && $_[2] !~ /\Q$tst_only\E/)) {
+		return 0;
+	}
+	my $line;
+	if ($show_types) {
+		$line = "$prefix$_[0]:$_[1]: $_[2]\n";
+	} else {
+		$line = "$prefix$_[0]: $_[2]\n";
+	}
+	$line = (split('\n', $line))[0] . "\n" if ($terse);
+
+	push(our @report, $line);
+
+	return 1;
+}
+sub report_dump {
+	our @report;
+}
+
+sub ERROR {
+	if (report("ERROR", $_[0], $_[1])) {
+		our $clean = 0;
+		our $cnt_error++;
+	}
+}
+sub WARN {
+	if (report("WARNING", $_[0], $_[1])) {
+		our $clean = 0;
+		our $cnt_warn++;
+	}
+}
+sub CHK {
+	if ($check && report("CHECK", $_[0], $_[1])) {
+		our $clean = 0;
+		our $cnt_chk++;
+	}
+}
+
+sub check_absolute_file {
+	my ($absolute, $herecurr) = @_;
+	my $file = $absolute;
+
+	##print "absolute<$absolute>\n";
+
+	# See if any suffix of this path is a path within the tree.
+	while ($file =~ s@^[^/]*/@@) {
+		if (-f "$root/$file") {
+			##print "file<$file>\n";
+			last;
+		}
+	}
+	if (! -f _)  {
+		return 0;
+	}
+
+	# It is, so see if the prefix is acceptable.
+	my $prefix = $absolute;
+	substr($prefix, -length($file)) = '';
+
+	##print "prefix<$prefix>\n";
+	if ($prefix ne ".../") {
+		WARN("USE_RELATIVE_PATH",
+		     "use relative pathname instead of absolute in changelog text\n" . $herecurr);
+	}
+}
+
+sub pos_last_openparen {
+	my ($line) = @_;
+
+	my $pos = 0;
+
+	my $opens = $line =~ tr/\(/\(/;
+	my $closes = $line =~ tr/\)/\)/;
+
+	my $last_openparen = 0;
+
+	if (($opens == 0) || ($closes >= $opens)) {
+		return -1;
+	}
+
+	my $len = length($line);
+
+	for ($pos = 0; $pos < $len; $pos++) {
+		my $string = substr($line, $pos);
+		if ($string =~ /^($FuncArg|$balanced_parens)/) {
+			$pos += length($1) - 1;
+		} elsif (substr($line, $pos, 1) eq '(') {
+			$last_openparen = $pos;
+		} elsif (index($string, '(') == -1) {
+			last;
+		}
+	}
+
+	return $last_openparen + 1;
+}
+
+sub process {
+	my $filename = shift;
+
+	my $linenr=0;
+	my $prevline="";
+	my $prevrawline="";
+	my $stashline="";
+	my $stashrawline="";
+
+	my $length;
+	my $indent;
+	my $previndent=0;
+	my $stashindent=0;
+
+	our $clean = 1;
+	my $signoff = 0;
+	my $is_patch = 0;
+
+	my $in_header_lines = 1;
+	my $in_commit_log = 0;		#Scanning lines before patch
+
+	my $non_utf8_charset = 0;
+
+	our @report = ();
+	our $cnt_lines = 0;
+	our $cnt_error = 0;
+	our $cnt_warn = 0;
+	our $cnt_chk = 0;
+
+	# Trace the real file/line as we go.
+	my $realfile = '';
+	my $realline = 0;
+	my $realcnt = 0;
+	my $here = '';
+	my $in_comment = 0;
+	my $comment_edge = 0;
+	my $first_line = 0;
+	my $p1_prefix = '';
+
+	my $prev_values = 'E';
+
+	# suppression flags
+	my %suppress_ifbraces;
+	my %suppress_whiletrailers;
+	my %suppress_export;
+	my $suppress_statement = 0;
+
+	my %camelcase = ();
+
+	# Pre-scan the patch sanitizing the lines.
+	# Pre-scan the patch looking for any __setup documentation.
+	#
+	my @setup_docs = ();
+	my $setup_docs = 0;
+
+	sanitise_line_reset();
+	my $line;
+	foreach my $rawline (@rawlines) {
+		$linenr++;
+		$line = $rawline;
+
+		if ($rawline=~/^\+\+\+\s+(\S+)/) {
+			$setup_docs = 0;
+			if ($1 =~ m@Documentation/kernel-parameters.txt$@) {
+				$setup_docs = 1;
+			}
+			#next;
+		}
+		if ($rawline=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) {
+			$realline=$1-1;
+			if (defined $2) {
+				$realcnt=$3+1;
+			} else {
+				$realcnt=1+1;
+			}
+			$in_comment = 0;
+
+			# Guestimate if this is a continuing comment.  Run
+			# the context looking for a comment "edge".  If this
+			# edge is a close comment then we must be in a comment
+			# at context start.
+			my $edge;
+			my $cnt = $realcnt;
+			for (my $ln = $linenr + 1; $cnt > 0; $ln++) {
+				next if (defined $rawlines[$ln - 1] &&
+					 $rawlines[$ln - 1] =~ /^-/);
+				$cnt--;
+				#print "RAW<$rawlines[$ln - 1]>\n";
+				last if (!defined $rawlines[$ln - 1]);
+				if ($rawlines[$ln - 1] =~ m@(/\*|\*/)@ &&
+				    $rawlines[$ln - 1] !~ m@"[^"]*(?:/\*|\*/)[^"]*"@) {
+					($edge) = $1;
+					last;
+				}
+			}
+			if (defined $edge && $edge eq '*/') {
+				$in_comment = 1;
+			}
+
+			# Guestimate if this is a continuing comment.  If this
+			# is the start of a diff block and this line starts
+			# ' *' then it is very likely a comment.
+			if (!defined $edge &&
+			    $rawlines[$linenr] =~ m@^.\s*(?:\*\*+| \*)(?:\s|$)@)
+			{
+				$in_comment = 1;
+			}
+
+			##print "COMMENT:$in_comment edge<$edge> $rawline\n";
+			sanitise_line_reset($in_comment);
+
+		} elsif ($realcnt && $rawline =~ /^(?:\+| |$)/) {
+			# Standardise the strings and chars within the input to
+			# simplify matching -- only bother with positive lines.
+			$line = sanitise_line($rawline);
+		}
+		push(@lines, $line);
+
+		if ($realcnt > 1) {
+			$realcnt-- if ($line =~ /^(?:\+| |$)/);
+		} else {
+			$realcnt = 0;
+		}
+
+		#print "==>$rawline\n";
+		#print "-->$line\n";
+
+		if ($setup_docs && $line =~ /^\+/) {
+			push(@setup_docs, $line);
+		}
+	}
+
+	$prefix = '';
+
+	$realcnt = 0;
+	$linenr = 0;
+	foreach my $line (@lines) {
+		$linenr++;
+
+		my $rawline = $rawlines[$linenr - 1];
+
+#extract the line range in the file after the patch is applied
+		if ($line=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) {
+			$is_patch = 1;
+			$first_line = $linenr + 1;
+			$realline=$1-1;
+			if (defined $2) {
+				$realcnt=$3+1;
+			} else {
+				$realcnt=1+1;
+			}
+			annotate_reset();
+			$prev_values = 'E';
+
+			%suppress_ifbraces = ();
+			%suppress_whiletrailers = ();
+			%suppress_export = ();
+			$suppress_statement = 0;
+			next;
+
+# track the line number as we move through the hunk, note that
+# new versions of GNU diff omit the leading space on completely
+# blank context lines so we need to count that too.
+		} elsif ($line =~ /^( |\+|$)/) {
+			$realline++;
+			$realcnt-- if ($realcnt != 0);
+
+			# Measure the line length and indent.
+			($length, $indent) = line_stats($rawline);
+
+			# Track the previous line.
+			($prevline, $stashline) = ($stashline, $line);
+			($previndent, $stashindent) = ($stashindent, $indent);
+			($prevrawline, $stashrawline) = ($stashrawline, $rawline);
+
+			#warn "line<$line>\n";
+
+		} elsif ($realcnt == 1) {
+			$realcnt--;
+		}
+
+		my $hunk_line = ($realcnt != 0);
+
+#make up the handle for any error we report on this line
+		$prefix = "$filename:$realline: " if ($emacs && $file);
+		$prefix = "$filename:$linenr: " if ($emacs && !$file);
+
+		$here = "#$linenr: " if (!$file);
+		$here = "#$realline: " if ($file);
+
+		# extract the filename as it passes
+		if ($line =~ /^diff --git.*?(\S+)$/) {
+			$realfile = $1;
+			$realfile =~ s@^([^/]*)/@@;
+			$in_commit_log = 0;
+		} elsif ($line =~ /^\+\+\+\s+(\S+)/) {
+			$realfile = $1;
+			$realfile =~ s@^([^/]*)/@@;
+			$in_commit_log = 0;
+
+			$p1_prefix = $1;
+			if (!$file && $tree && $p1_prefix ne '' &&
+			    -e "$root/$p1_prefix") {
+				WARN("PATCH_PREFIX",
+				     "patch prefix '$p1_prefix' exists, appears to be a -p0 patch\n");
+			}
+
+			if ($realfile =~ m@^include/asm/@) {
+				ERROR("MODIFIED_INCLUDE_ASM",
+				      "do not modify files in include/asm, change architecture specific files in include/asm-<architecture>\n" . "$here$rawline\n");
+			}
+			next;
+		}
+
+		$here .= "FILE: $realfile:$realline:" if ($realcnt != 0);
+
+		my $hereline = "$here\n$rawline\n";
+		my $herecurr = "$here\n$rawline\n";
+		my $hereprev = "$here\n$prevrawline\n$rawline\n";
+
+		$cnt_lines++ if ($realcnt != 0);
+
+# Check for incorrect file permissions
+		if ($line =~ /^new (file )?mode.*[7531]\d{0,2}$/) {
+			my $permhere = $here . "FILE: $realfile\n";
+			if ($realfile !~ m@scripts/@ &&
+			    $realfile !~ /\.(py|pl|awk|sh)$/) {
+				ERROR("EXECUTE_PERMISSIONS",
+				      "do not set execute permissions for source files\n" . $permhere);
+			}
+		}
+
+# Check the patch for a signoff:
+		if ($line =~ /^\s*signed-off-by:/i) {
+			$signoff++;
+			$in_commit_log = 0;
+		}
+
+# Check signature styles
+		if (!$in_header_lines &&
+		    $line =~ /^(\s*)([a-z0-9_-]+by:|$signature_tags)(\s*)(.*)/i) {
+			my $space_before = $1;
+			my $sign_off = $2;
+			my $space_after = $3;
+			my $email = $4;
+			my $ucfirst_sign_off = ucfirst(lc($sign_off));
+
+			if ($sign_off !~ /$signature_tags/) {
+				WARN("BAD_SIGN_OFF",
+				     "Non-standard signature: $sign_off\n" . $herecurr);
+			}
+			if (defined $space_before && $space_before ne "") {
+				WARN("BAD_SIGN_OFF",
+				     "Do not use whitespace before $ucfirst_sign_off\n" . $herecurr);
+			}
+			if ($sign_off =~ /-by:$/i && $sign_off ne $ucfirst_sign_off) {
+				WARN("BAD_SIGN_OFF",
+				     "'$ucfirst_sign_off' is the preferred signature form\n" . $herecurr);
+			}
+			if (!defined $space_after || $space_after ne " ") {
+				WARN("BAD_SIGN_OFF",
+				     "Use a single space after $ucfirst_sign_off\n" . $herecurr);
+			}
+
+			my ($email_name, $email_address, $comment) = parse_email($email);
+			my $suggested_email = format_email(($email_name, $email_address));
+			if ($suggested_email eq "") {
+				ERROR("BAD_SIGN_OFF",
+				      "Unrecognized email address: '$email'\n" . $herecurr);
+			} else {
+				my $dequoted = $suggested_email;
+				$dequoted =~ s/^"//;
+				$dequoted =~ s/" </ </;
+				# Don't force email to have quotes
+				# Allow just an angle bracketed address
+				if ("$dequoted$comment" ne $email &&
+				    "<$email_address>$comment" ne $email &&
+				    "$suggested_email$comment" ne $email) {
+					WARN("BAD_SIGN_OFF",
+					     "email address '$email' might be better as '$suggested_email$comment'\n" . $herecurr);
+				}
+			}
+		}
+
+# Check for wrappage within a valid hunk of the file
+		if ($realcnt != 0 && $line !~ m{^(?:\+|-| |\\ No newline|$)}) {
+			ERROR("CORRUPTED_PATCH",
+			      "patch seems to be corrupt (line wrapped?)\n" .
+				$herecurr) if (!$emitted_corrupt++);
+		}
+
+# Check for absolute kernel paths.
+		if ($tree) {
+			while ($line =~ m{(?:^|\s)(/\S*)}g) {
+				my $file = $1;
+
+				if ($file =~ m{^(.*?)(?::\d+)+:?$} &&
+				    check_absolute_file($1, $herecurr)) {
+					#
+				} else {
+					check_absolute_file($file, $herecurr);
+				}
+			}
+		}
+
+# UTF-8 regex found at http://www.w3.org/International/questions/qa-forms-utf-8.en.php
+		if (($realfile =~ /^$/ || $line =~ /^\+/) &&
+		    $rawline !~ m/^$UTF8*$/) {
+			my ($utf8_prefix) = ($rawline =~ /^($UTF8*)/);
+
+			my $blank = copy_spacing($rawline);
+			my $ptr = substr($blank, 0, length($utf8_prefix)) . "^";
+			my $hereptr = "$hereline$ptr\n";
+
+			CHK("INVALID_UTF8",
+			    "Invalid UTF-8, patch and commit message should be encoded in UTF-8\n" . $hereptr);
+		}
+
+# Check if it's the start of a commit log
+# (not a header line and we haven't seen the patch filename)
+		if ($in_header_lines && $realfile =~ /^$/ &&
+		    $rawline !~ /^(commit\b|from\b|[\w-]+:).+$/i) {
+			$in_header_lines = 0;
+			$in_commit_log = 1;
+		}
+
+# Check if there is UTF-8 in a commit log when a mail header has explicitly
+# declined it, i.e defined some charset where it is missing.
+		if ($in_header_lines &&
+		    $rawline =~ /^Content-Type:.+charset="(.+)".*$/ &&
+		    $1 !~ /utf-8/i) {
+			$non_utf8_charset = 1;
+		}
+
+		if ($in_commit_log && $non_utf8_charset && $realfile =~ /^$/ &&
+		    $rawline =~ /$NON_ASCII_UTF8/) {
+			WARN("UTF8_BEFORE_PATCH",
+			    "8-bit UTF-8 used in possible commit log\n" . $herecurr);
+		}
+
+# ignore non-hunk lines and lines being removed
+		next if (!$hunk_line || $line =~ /^-/);
+
+#trailing whitespace
+		if ($line =~ /^\+.*\015/) {
+			my $herevet = "$here\n" . cat_vet($rawline) . "\n";
+			ERROR("DOS_LINE_ENDINGS",
+			      "DOS line endings\n" . $herevet);
+
+		} elsif ($rawline =~ /^\+.*\S\s+$/ || $rawline =~ /^\+\s+$/) {
+			my $herevet = "$here\n" . cat_vet($rawline) . "\n";
+			ERROR("TRAILING_WHITESPACE",
+			      "trailing whitespace\n" . $herevet);
+			$rpt_cleaners = 1;
+		}
+
+# check for Kconfig help text having a real description
+# Only applies when adding the entry originally, after that we do not have
+# sufficient context to determine whether it is indeed long enough.
+		if ($realfile =~ /Kconfig/ &&
+		    $line =~ /.\s*config\s+/) {
+			my $length = 0;
+			my $cnt = $realcnt;
+			my $ln = $linenr + 1;
+			my $f;
+			my $is_start = 0;
+			my $is_end = 0;
+			for (; $cnt > 0 && defined $lines[$ln - 1]; $ln++) {
+				$f = $lines[$ln - 1];
+				$cnt-- if ($lines[$ln - 1] !~ /^-/);
+				$is_end = $lines[$ln - 1] =~ /^\+/;
+
+				next if ($f =~ /^-/);
+
+				if ($lines[$ln - 1] =~ /.\s*(?:bool|tristate)\s*\"/) {
+					$is_start = 1;
+				} elsif ($lines[$ln - 1] =~ /.\s*(?:---)?help(?:---)?$/) {
+					$length = -1;
+				}
+
+				$f =~ s/^.//;
+				$f =~ s/#.*//;
+				$f =~ s/^\s+//;
+				next if ($f =~ /^$/);
+				if ($f =~ /^\s*config\s/) {
+					$is_end = 1;
+					last;
+				}
+				$length++;
+			}
+			WARN("CONFIG_DESCRIPTION",
+			     "please write a paragraph that describes the config symbol fully\n" . $herecurr) if ($is_start && $is_end && $length < 4);
+			#print "is_start<$is_start> is_end<$is_end> length<$length>\n";
+		}
+
+# discourage the addition of CONFIG_EXPERIMENTAL in Kconfig.
+		if ($realfile =~ /Kconfig/ &&
+		    $line =~ /.\s*depends on\s+.*\bEXPERIMENTAL\b/) {
+			WARN("CONFIG_EXPERIMENTAL",
+			     "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n");
+		}
+
+		if (($realfile =~ /Makefile.*/ || $realfile =~ /Kbuild.*/) &&
+		    ($line =~ /\+(EXTRA_[A-Z]+FLAGS).*/)) {
+			my $flag = $1;
+			my $replacement = {
+				'EXTRA_AFLAGS' =>   'asflags-y',
+				'EXTRA_CFLAGS' =>   'ccflags-y',
+				'EXTRA_CPPFLAGS' => 'cppflags-y',
+				'EXTRA_LDFLAGS' =>  'ldflags-y',
+			};
+
+			WARN("DEPRECATED_VARIABLE",
+			     "Use of $flag is deprecated, please use \`$replacement->{$flag} instead.\n" . $herecurr) if ($replacement->{$flag});
+		}
+
+# check we are in a valid source file if not then ignore this hunk
+		next if ($realfile !~ /\.(h|c|s|S|pl|sh)$/);
+
+#line length limit
+		if ($line =~ /^\+/ && $prevrawline !~ /\/\*\*/ &&
+		    $rawline !~ /^.\s*\*\s*\@$Ident\s/ &&
+		    !($line =~ /^\+\s*$logFunctions\s*\(\s*(?:(KERN_\S+\s*|[^"]*))?"[X\t]*"\s*(?:|,|\)\s*;)\s*$/ ||
+		    $line =~ /^\+\s*"[^"]*"\s*(?:\s*|,|\)\s*;)\s*$/) &&
+		    $length > $max_line_length)
+		{
+			WARN("LONG_LINE",
+			     "line over $max_line_length characters\n" . $herecurr);
+		}
+
+# Check for user-visible strings broken across lines, which breaks the ability
+# to grep for the string.  Limited to strings used as parameters (those
+# following an open parenthesis), which almost completely eliminates false
+# positives, as well as warning only once per parameter rather than once per
+# line of the string.  Make an exception when the previous string ends in a
+# newline (multiple lines in one string constant) or \n\t (common in inline
+# assembly to indent the instruction on the following line).
+		if ($line =~ /^\+\s*"/ &&
+		    $prevline =~ /"\s*$/ &&
+		    $prevline =~ /\(/ &&
+		    $prevrawline !~ /\\n(?:\\t)*"\s*$/) {
+			WARN("SPLIT_STRING",
+			     "quoted string split across lines\n" . $hereprev);
+		}
+
+# check for spaces before a quoted newline
+		if ($rawline =~ /^.*\".*\s\\n/) {
+			WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE",
+			     "unnecessary whitespace before a quoted newline\n" . $herecurr);
+		}
+
+# check for adding lines without a newline.
+		if ($line =~ /^\+/ && defined $lines[$linenr] && $lines[$linenr] =~ /^\\ No newline at end of file/) {
+			WARN("MISSING_EOF_NEWLINE",
+			     "adding a line without newline at end of file\n" . $herecurr);
+		}
+
+# Blackfin: use hi/lo macros
+		if ($realfile =~ m@arch/blackfin/.*\.S$@) {
+			if ($line =~ /\.[lL][[:space:]]*=.*&[[:space:]]*0x[fF][fF][fF][fF]/) {
+				my $herevet = "$here\n" . cat_vet($line) . "\n";
+				ERROR("LO_MACRO",
+				      "use the LO() macro, not (... & 0xFFFF)\n" . $herevet);
+			}
+			if ($line =~ /\.[hH][[:space:]]*=.*>>[[:space:]]*16/) {
+				my $herevet = "$here\n" . cat_vet($line) . "\n";
+				ERROR("HI_MACRO",
+				      "use the HI() macro, not (... >> 16)\n" . $herevet);
+			}
+		}
+
+# check we are in a valid source file C or perl if not then ignore this hunk
+		next if ($realfile !~ /\.(h|c|pl)$/);
+
+# at the beginning of a line any tabs must come first and anything
+# more than 8 must use tabs.
+		if ($rawline =~ /^\+\s* \t\s*\S/ ||
+		    $rawline =~ /^\+\s*        \s*/) {
+			my $herevet = "$here\n" . cat_vet($rawline) . "\n";
+			ERROR("CODE_INDENT",
+			      "code indent should use tabs where possible\n" . $herevet);
+			$rpt_cleaners = 1;
+		}
+
+# check for space before tabs.
+		if ($rawline =~ /^\+/ && $rawline =~ / \t/) {
+			my $herevet = "$here\n" . cat_vet($rawline) . "\n";
+			WARN("SPACE_BEFORE_TAB",
+			     "please, no space before tabs\n" . $herevet);
+		}
+
+# check for && or || at the start of a line
+		if ($rawline =~ /^\+\s*(&&|\|\|)/) {
+			CHK("LOGICAL_CONTINUATIONS",
+			    "Logical continuations should be on the previous line\n" . $hereprev);
+		}
+
+# check multi-line statement indentation matches previous line
+		if ($^V && $^V ge 5.10.0 &&
+		    $prevline =~ /^\+(\t*)(if \(|$Ident\().*(\&\&|\|\||,)\s*$/) {
+			$prevline =~ /^\+(\t*)(.*)$/;
+			my $oldindent = $1;
+			my $rest = $2;
+
+			my $pos = pos_last_openparen($rest);
+			if ($pos >= 0) {
+				$line =~ /^(\+| )([ \t]*)/;
+				my $newindent = $2;
+
+				my $goodtabindent = $oldindent .
+					"\t" x ($pos / 8) .
+					" "  x ($pos % 8);
+				my $goodspaceindent = $oldindent . " "  x $pos;
+
+				if ($newindent ne $goodtabindent &&
+				    $newindent ne $goodspaceindent) {
+					CHK("PARENTHESIS_ALIGNMENT",
+					    "Alignment should match open parenthesis\n" . $hereprev);
+				}
+			}
+		}
+
+		if ($line =~ /^\+.*\*[ \t]*\)[ \t]+/) {
+			CHK("SPACING",
+			    "No space is necessary after a cast\n" . $hereprev);
+		}
+
+		if ($realfile =~ m@^(drivers/net/|net/)@ &&
+		    $rawline =~ /^\+[ \t]*\/\*[ \t]*$/ &&
+		    $prevrawline =~ /^\+[ \t]*$/) {
+			WARN("NETWORKING_BLOCK_COMMENT_STYLE",
+			     "networking block comments don't use an empty /* line, use /* Comment...\n" . $hereprev);
+		}
+
+		if ($realfile =~ m@^(drivers/net/|net/)@ &&
+		    $rawline !~ m@^\+[ \t]*\*/[ \t]*$@ &&	#trailing */
+		    $rawline !~ m@^\+.*/\*.*\*/[ \t]*$@ &&	#inline /*...*/
+		    $rawline !~ m@^\+.*\*{2,}/[ \t]*$@ &&	#trailing **/
+		    $rawline =~ m@^\+[ \t]*.+\*\/[ \t]*$@) {	#non blank */
+			WARN("NETWORKING_BLOCK_COMMENT_STYLE",
+			     "networking block comments put the trailing */ on a separate line\n" . $herecurr);
+		}
+
+# check for spaces at the beginning of a line.
+# Exceptions:
+#  1) within comments
+#  2) indented preprocessor commands
+#  3) hanging labels
+		if ($rawline =~ /^\+ / && $line !~ /\+ *(?:$;|#|$Ident:)/)  {
+			my $herevet = "$here\n" . cat_vet($rawline) . "\n";
+			WARN("LEADING_SPACE",
+			     "please, no spaces at the start of a line\n" . $herevet);
+		}
+
+# check we are in a valid C source file if not then ignore this hunk
+		next if ($realfile !~ /\.(h|c)$/);
+
+# discourage the addition of CONFIG_EXPERIMENTAL in #if(def).
+		if ($line =~ /^\+\s*\#\s*if.*\bCONFIG_EXPERIMENTAL\b/) {
+			WARN("CONFIG_EXPERIMENTAL",
+			     "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n");
+		}
+
+# check for RCS/CVS revision markers
+		if ($rawline =~ /^\+.*\$(Revision|Log|Id)(?:\$|)/) {
+			WARN("CVS_KEYWORD",
+			     "CVS style keyword markers, these will _not_ be updated\n". $herecurr);
+		}
+
+# Blackfin: don't use __builtin_bfin_[cs]sync
+		if ($line =~ /__builtin_bfin_csync/) {
+			my $herevet = "$here\n" . cat_vet($line) . "\n";
+			ERROR("CSYNC",
+			      "use the CSYNC() macro in asm/blackfin.h\n" . $herevet);
+		}
+		if ($line =~ /__builtin_bfin_ssync/) {
+			my $herevet = "$here\n" . cat_vet($line) . "\n";
+			ERROR("SSYNC",
+			      "use the SSYNC() macro in asm/blackfin.h\n" . $herevet);
+		}
+
+# check for old HOTPLUG __dev<foo> section markings
+		if ($line =~ /\b(__dev(init|exit)(data|const|))\b/) {
+			WARN("HOTPLUG_SECTION",
+			     "Using $1 is unnecessary\n" . $herecurr);
+		}
+
+# Check for potential 'bare' types
+		my ($stat, $cond, $line_nr_next, $remain_next, $off_next,
+		    $realline_next);
+#print "LINE<$line>\n";
+		if ($linenr >= $suppress_statement &&
+		    $realcnt && $line =~ /.\s*\S/) {
+			($stat, $cond, $line_nr_next, $remain_next, $off_next) =
+				ctx_statement_block($linenr, $realcnt, 0);
+			$stat =~ s/\n./\n /g;
+			$cond =~ s/\n./\n /g;
+
+#print "linenr<$linenr> <$stat>\n";
+			# If this statement has no statement boundaries within
+			# it there is no point in retrying a statement scan
+			# until we hit end of it.
+			my $frag = $stat; $frag =~ s/;+\s*$//;
+			if ($frag !~ /(?:{|;)/) {
+#print "skip<$line_nr_next>\n";
+				$suppress_statement = $line_nr_next;
+			}
+
+			# Find the real next line.
+			$realline_next = $line_nr_next;
+			if (defined $realline_next &&
+			    (!defined $lines[$realline_next - 1] ||
+			     substr($lines[$realline_next - 1], $off_next) =~ /^\s*$/)) {
+				$realline_next++;
+			}
+
+			my $s = $stat;
+			$s =~ s/{.*$//s;
+
+			# Ignore goto labels.
+			if ($s =~ /$Ident:\*$/s) {
+
+			# Ignore functions being called
+			} elsif ($s =~ /^.\s*$Ident\s*\(/s) {
+
+			} elsif ($s =~ /^.\s*else\b/s) {
+
+			# declarations always start with types
+			} elsif ($prev_values eq 'E' && $s =~ /^.\s*(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?((?:\s*$Ident)+?)\b(?:\s+$Sparse)?\s*\**\s*(?:$Ident|\(\*[^\)]*\))(?:\s*$Modifier)?\s*(?:;|=|,|\()/s) {
+				my $type = $1;
+				$type =~ s/\s+/ /g;
+				possible($type, "A:" . $s);
+
+			# definitions in global scope can only start with types
+			} elsif ($s =~ /^.(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?($Ident)\b\s*(?!:)/s) {
+				possible($1, "B:" . $s);
+			}
+
+			# any (foo ... *) is a pointer cast, and foo is a type
+			while ($s =~ /\(($Ident)(?:\s+$Sparse)*[\s\*]+\s*\)/sg) {
+				possible($1, "C:" . $s);
+			}
+
+			# Check for any sort of function declaration.
+			# int foo(something bar, other baz);
+			# void (*store_gdt)(x86_descr_ptr *);
+			if ($prev_values eq 'E' && $s =~ /^(.(?:typedef\s*)?(?:(?:$Storage|$Inline)\s*)*\s*$Type\s*(?:\b$Ident|\(\*\s*$Ident\))\s*)\(/s) {
+				my ($name_len) = length($1);
+
+				my $ctx = $s;
+				substr($ctx, 0, $name_len + 1, '');
+				$ctx =~ s/\)[^\)]*$//;
+
+				for my $arg (split(/\s*,\s*/, $ctx)) {
+					if ($arg =~ /^(?:const\s+)?($Ident)(?:\s+$Sparse)*\s*\**\s*(:?\b$Ident)?$/s || $arg =~ /^($Ident)$/s) {
+
+						possible($1, "D:" . $s);
+					}
+				}
+			}
+
+		}
+
+#
+# Checks which may be anchored in the context.
+#
+
+# Check for switch () and associated case and default
+# statements should be at the same indent.
+		if ($line=~/\bswitch\s*\(.*\)/) {
+			my $err = '';
+			my $sep = '';
+			my @ctx = ctx_block_outer($linenr, $realcnt);
+			shift(@ctx);
+			for my $ctx (@ctx) {
+				my ($clen, $cindent) = line_stats($ctx);
+				if ($ctx =~ /^\+\s*(case\s+|default:)/ &&
+							$indent != $cindent) {
+					$err .= "$sep$ctx\n";
+					$sep = '';
+				} else {
+					$sep = "[...]\n";
+				}
+			}
+			if ($err ne '') {
+				ERROR("SWITCH_CASE_INDENT_LEVEL",
+				      "switch and case should be at the same indent\n$hereline$err");
+			}
+		}
+
+# if/while/etc brace do not go on next line, unless defining a do while loop,
+# or if that brace on the next line is for something else
+		if ($line =~ /(.*)\b((?:if|while|for|switch)\s*\(|do\b|else\b)/ && $line !~ /^.\s*\#/) {
+			my $pre_ctx = "$1$2";
+
+			my ($level, @ctx) = ctx_statement_level($linenr, $realcnt, 0);
+
+			if ($line =~ /^\+\t{6,}/) {
+				WARN("DEEP_INDENTATION",
+				     "Too many leading tabs - consider code refactoring\n" . $herecurr);
+			}
+
+			my $ctx_cnt = $realcnt - $#ctx - 1;
+			my $ctx = join("\n", @ctx);
+
+			my $ctx_ln = $linenr;
+			my $ctx_skip = $realcnt;
+
+			while ($ctx_skip > $ctx_cnt || ($ctx_skip == $ctx_cnt &&
+					defined $lines[$ctx_ln - 1] &&
+					$lines[$ctx_ln - 1] =~ /^-/)) {
+				##print "SKIP<$ctx_skip> CNT<$ctx_cnt>\n";
+				$ctx_skip-- if (!defined $lines[$ctx_ln - 1] || $lines[$ctx_ln - 1] !~ /^-/);
+				$ctx_ln++;
+			}
+
+			#print "realcnt<$realcnt> ctx_cnt<$ctx_cnt>\n";
+			#print "pre<$pre_ctx>\nline<$line>\nctx<$ctx>\nnext<$lines[$ctx_ln - 1]>\n";
+
+			if ($ctx !~ /{\s*/ && defined($lines[$ctx_ln -1]) && $lines[$ctx_ln - 1] =~ /^\+\s*{/) {
+				ERROR("OPEN_BRACE",
+				      "that open brace { should be on the previous line\n" .
+					"$here\n$ctx\n$rawlines[$ctx_ln - 1]\n");
+			}
+			if ($level == 0 && $pre_ctx !~ /}\s*while\s*\($/ &&
+			    $ctx =~ /\)\s*\;\s*$/ &&
+			    defined $lines[$ctx_ln - 1])
+			{
+				my ($nlength, $nindent) = line_stats($lines[$ctx_ln - 1]);
+				if ($nindent > $indent) {
+					WARN("TRAILING_SEMICOLON",
+					     "trailing semicolon indicates no statements, indent implies otherwise\n" .
+						"$here\n$ctx\n$rawlines[$ctx_ln - 1]\n");
+				}
+			}
+		}
+
+# Check relative indent for conditionals and blocks.
+		if ($line =~ /\b(?:(?:if|while|for)\s*\(|do\b)/ && $line !~ /^.\s*#/ && $line !~ /\}\s*while\s*/) {
+			($stat, $cond, $line_nr_next, $remain_next, $off_next) =
+				ctx_statement_block($linenr, $realcnt, 0)
+					if (!defined $stat);
+			my ($s, $c) = ($stat, $cond);
+
+			substr($s, 0, length($c), '');
+
+			# Make sure we remove the line prefixes as we have
+			# none on the first line, and are going to readd them
+			# where necessary.
+			$s =~ s/\n./\n/gs;
+
+			# Find out how long the conditional actually is.
+			my @newlines = ($c =~ /\n/gs);
+			my $cond_lines = 1 + $#newlines;
+
+			# We want to check the first line inside the block
+			# starting at the end of the conditional, so remove:
+			#  1) any blank line termination
+			#  2) any opening brace { on end of the line
+			#  3) any do (...) {
+			my $continuation = 0;
+			my $check = 0;
+			$s =~ s/^.*\bdo\b//;
+			$s =~ s/^\s*{//;
+			if ($s =~ s/^\s*\\//) {
+				$continuation = 1;
+			}
+			if ($s =~ s/^\s*?\n//) {
+				$check = 1;
+				$cond_lines++;
+			}
+
+			# Also ignore a loop construct at the end of a
+			# preprocessor statement.
+			if (($prevline =~ /^.\s*#\s*define\s/ ||
+			    $prevline =~ /\\\s*$/) && $continuation == 0) {
+				$check = 0;
+			}
+
+			my $cond_ptr = -1;
+			$continuation = 0;
+			while ($cond_ptr != $cond_lines) {
+				$cond_ptr = $cond_lines;
+
+				# If we see an #else/#elif then the code
+				# is not linear.
+				if ($s =~ /^\s*\#\s*(?:else|elif)/) {
+					$check = 0;
+				}
+
+				# Ignore:
+				#  1) blank lines, they should be at 0,
+				#  2) preprocessor lines, and
+				#  3) labels.
+				if ($continuation ||
+				    $s =~ /^\s*?\n/ ||
+				    $s =~ /^\s*#\s*?/ ||
+				    $s =~ /^\s*$Ident\s*:/) {
+					$continuation = ($s =~ /^.*?\\\n/) ? 1 : 0;
+					if ($s =~ s/^.*?\n//) {
+						$cond_lines++;
+					}
+				}
+			}
+
+			my (undef, $sindent) = line_stats("+" . $s);
+			my $stat_real = raw_line($linenr, $cond_lines);
+
+			# Check if either of these lines are modified, else
+			# this is not this patch's fault.
+			if (!defined($stat_real) ||
+			    $stat !~ /^\+/ && $stat_real !~ /^\+/) {
+				$check = 0;
+			}
+			if (defined($stat_real) && $cond_lines > 1) {
+				$stat_real = "[...]\n$stat_real";
+			}
+
+			#print "line<$line> prevline<$prevline> indent<$indent> sindent<$sindent> check<$check> continuation<$continuation> s<$s> cond_lines<$cond_lines> stat_real<$stat_real> stat<$stat>\n";
+
+			if ($check && (($sindent % 8) != 0 ||
+			    ($sindent <= $indent && $s ne ''))) {
+				WARN("SUSPECT_CODE_INDENT",
+				     "suspect code indent for conditional statements ($indent, $sindent)\n" . $herecurr . "$stat_real\n");
+			}
+		}
+
+		# Track the 'values' across context and added lines.
+		my $opline = $line; $opline =~ s/^./ /;
+		my ($curr_values, $curr_vars) =
+				annotate_values($opline . "\n", $prev_values);
+		$curr_values = $prev_values . $curr_values;
+		if ($dbg_values) {
+			my $outline = $opline; $outline =~ s/\t/ /g;
+			print "$linenr > .$outline\n";
+			print "$linenr > $curr_values\n";
+			print "$linenr >  $curr_vars\n";
+		}
+		$prev_values = substr($curr_values, -1);
+
+#ignore lines not being added
+		if ($line=~/^[^\+]/) {next;}
+
+# TEST: allow direct testing of the type matcher.
+		if ($dbg_type) {
+			if ($line =~ /^.\s*$Declare\s*$/) {
+				ERROR("TEST_TYPE",
+				      "TEST: is type\n" . $herecurr);
+			} elsif ($dbg_type > 1 && $line =~ /^.+($Declare)/) {
+				ERROR("TEST_NOT_TYPE",
+				      "TEST: is not type ($1 is)\n". $herecurr);
+			}
+			next;
+		}
+# TEST: allow direct testing of the attribute matcher.
+		if ($dbg_attr) {
+			if ($line =~ /^.\s*$Modifier\s*$/) {
+				ERROR("TEST_ATTR",
+				      "TEST: is attr\n" . $herecurr);
+			} elsif ($dbg_attr > 1 && $line =~ /^.+($Modifier)/) {
+				ERROR("TEST_NOT_ATTR",
+				      "TEST: is not attr ($1 is)\n". $herecurr);
+			}
+			next;
+		}
+
+# check for initialisation to aggregates open brace on the next line
+		if ($line =~ /^.\s*{/ &&
+		    $prevline =~ /(?:^|[^=])=\s*$/) {
+			ERROR("OPEN_BRACE",
+			      "that open brace { should be on the previous line\n" . $hereprev);
+		}
+
+#
+# Checks which are anchored on the added line.
+#
+
+# check for malformed paths in #include statements (uses RAW line)
+		if ($rawline =~ m{^.\s*\#\s*include\s+[<"](.*)[">]}) {
+			my $path = $1;
+			if ($path =~ m{//}) {
+				ERROR("MALFORMED_INCLUDE",
+				      "malformed #include filename\n" . $herecurr);
+			}
+			if ($path =~ "^uapi/" && $realfile =~ m@\binclude/uapi/@) {
+				ERROR("UAPI_INCLUDE",
+				      "No #include in ...include/uapi/... should use a uapi/ path prefix\n" . $herecurr);
+			}
+		}
+
+# no C99 // comments
+		if ($line =~ m{//}) {
+			ERROR("C99_COMMENTS",
+			      "do not use C99 // comments\n" . $herecurr);
+		}
+		# Remove C99 comments.
+		$line =~ s@//.*@@;
+		$opline =~ s@//.*@@;
+
+# EXPORT_SYMBOL should immediately follow the thing it is exporting, consider
+# the whole statement.
+#print "APW <$lines[$realline_next - 1]>\n";
+		if (defined $realline_next &&
+		    exists $lines[$realline_next - 1] &&
+		    !defined $suppress_export{$realline_next} &&
+		    ($lines[$realline_next - 1] =~ /EXPORT_SYMBOL.*\((.*)\)/ ||
+		     $lines[$realline_next - 1] =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) {
+			# Handle definitions which produce identifiers with
+			# a prefix:
+			#   XXX(foo);
+			#   EXPORT_SYMBOL(something_foo);
+			my $name = $1;
+			if ($stat =~ /^(?:.\s*}\s*\n)?.([A-Z_]+)\s*\(\s*($Ident)/ &&
+			    $name =~ /^${Ident}_$2/) {
+#print "FOO C name<$name>\n";
+				$suppress_export{$realline_next} = 1;
+
+			} elsif ($stat !~ /(?:
+				\n.}\s*$|
+				^.DEFINE_$Ident\(\Q$name\E\)|
+				^.DECLARE_$Ident\(\Q$name\E\)|
+				^.LIST_HEAD\(\Q$name\E\)|
+				^.(?:$Storage\s+)?$Type\s*\(\s*\*\s*\Q$name\E\s*\)\s*\(|
+				\b\Q$name\E(?:\s+$Attribute)*\s*(?:;|=|\[|\()
+			    )/x) {
+#print "FOO A<$lines[$realline_next - 1]> stat<$stat> name<$name>\n";
+				$suppress_export{$realline_next} = 2;
+			} else {
+				$suppress_export{$realline_next} = 1;
+			}
+		}
+		if (!defined $suppress_export{$linenr} &&
+		    $prevline =~ /^.\s*$/ &&
+		    ($line =~ /EXPORT_SYMBOL.*\((.*)\)/ ||
+		     $line =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) {
+#print "FOO B <$lines[$linenr - 1]>\n";
+			$suppress_export{$linenr} = 2;
+		}
+		if (defined $suppress_export{$linenr} &&
+		    $suppress_export{$linenr} == 2) {
+			WARN("EXPORT_SYMBOL",
+			     "EXPORT_SYMBOL(foo); should immediately follow its function/variable\n" . $herecurr);
+		}
+
+# check for global initialisers.
+		if ($line =~ /^.$Type\s*$Ident\s*(?:\s+$Modifier)*\s*=\s*(0|NULL|false)\s*;/) {
+			ERROR("GLOBAL_INITIALISERS",
+			      "do not initialise globals to 0 or NULL\n" .
+				$herecurr);
+		}
+# check for static initialisers.
+		if ($line =~ /\bstatic\s.*=\s*(0|NULL|false)\s*;/) {
+			ERROR("INITIALISED_STATIC",
+			      "do not initialise statics to 0 or NULL\n" .
+				$herecurr);
+		}
+
+# check for static const char * arrays.
+		if ($line =~ /\bstatic\s+const\s+char\s*\*\s*(\w+)\s*\[\s*\]\s*=\s*/) {
+			WARN("STATIC_CONST_CHAR_ARRAY",
+			     "static const char * array should probably be static const char * const\n" .
+				$herecurr);
+               }
+
+# check for static char foo[] = "bar" declarations.
+		if ($line =~ /\bstatic\s+char\s+(\w+)\s*\[\s*\]\s*=\s*"/) {
+			WARN("STATIC_CONST_CHAR_ARRAY",
+			     "static char array declaration should probably be static const char\n" .
+				$herecurr);
+               }
+
+# check for declarations of struct pci_device_id
+		if ($line =~ /\bstruct\s+pci_device_id\s+\w+\s*\[\s*\]\s*\=\s*\{/) {
+			WARN("DEFINE_PCI_DEVICE_TABLE",
+			     "Use DEFINE_PCI_DEVICE_TABLE for struct pci_device_id\n" . $herecurr);
+		}
+
+# check for new typedefs, only function parameters and sparse annotations
+# make sense.
+		if ($line =~ /\btypedef\s/ &&
+		    $line !~ /\btypedef\s+$Type\s*\(\s*\*?$Ident\s*\)\s*\(/ &&
+		    $line !~ /\btypedef\s+$Type\s+$Ident\s*\(/ &&
+		    $line !~ /\b$typeTypedefs\b/ &&
+		    $line !~ /\b__bitwise(?:__|)\b/) {
+			WARN("NEW_TYPEDEFS",
+			     "do not add new typedefs\n" . $herecurr);
+		}
+
+# * goes on variable not on type
+		# (char*[ const])
+		while ($line =~ m{(\($NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)\))}g) {
+			#print "AA<$1>\n";
+			my ($from, $to) = ($2, $2);
+
+			# Should start with a space.
+			$to =~ s/^(\S)/ $1/;
+			# Should not end with a space.
+			$to =~ s/\s+$//;
+			# '*'s should not have spaces between.
+			while ($to =~ s/\*\s+\*/\*\*/) {
+			}
+
+			#print "from<$from> to<$to>\n";
+			if ($from ne $to) {
+				ERROR("POINTER_LOCATION",
+				      "\"(foo$from)\" should be \"(foo$to)\"\n" .  $herecurr);
+			}
+		}
+		while ($line =~ m{(\b$NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)($Ident))}g) {
+			#print "BB<$1>\n";
+			my ($from, $to, $ident) = ($2, $2, $3);
+
+			# Should start with a space.
+			$to =~ s/^(\S)/ $1/;
+			# Should not end with a space.
+			$to =~ s/\s+$//;
+			# '*'s should not have spaces between.
+			while ($to =~ s/\*\s+\*/\*\*/) {
+			}
+			# Modifiers should have spaces.
+			$to =~ s/(\b$Modifier$)/$1 /;
+
+			#print "from<$from> to<$to> ident<$ident>\n";
+			if ($from ne $to && $ident !~ /^$Modifier$/) {
+				ERROR("POINTER_LOCATION",
+				      "\"foo${from}bar\" should be \"foo${to}bar\"\n" .  $herecurr);
+			}
+		}
+
+# # no BUG() or BUG_ON()
+# 		if ($line =~ /\b(BUG|BUG_ON)\b/) {
+# 			print "Try to use WARN_ON & Recovery code rather than BUG() or BUG_ON()\n";
+# 			print "$herecurr";
+# 			$clean = 0;
+# 		}
+
+		if ($line =~ /\bLINUX_VERSION_CODE\b/) {
+			WARN("LINUX_VERSION_CODE",
+			     "LINUX_VERSION_CODE should be avoided, code should be for the version to which it is merged\n" . $herecurr);
+		}
+
+# check for uses of printk_ratelimit
+		if ($line =~ /\bprintk_ratelimit\s*\(/) {
+			WARN("PRINTK_RATELIMITED",
+"Prefer printk_ratelimited or pr_<level>_ratelimited to printk_ratelimit\n" . $herecurr);
+		}
+
+# printk should use KERN_* levels.  Note that follow on printk's on the
+# same line do not need a level, so we use the current block context
+# to try and find and validate the current printk.  In summary the current
+# printk includes all preceding printk's which have no newline on the end.
+# we assume the first bad printk is the one to report.
+		if ($line =~ /\bprintk\((?!KERN_)\s*"/) {
+			my $ok = 0;
+			for (my $ln = $linenr - 1; $ln >= $first_line; $ln--) {
+				#print "CHECK<$lines[$ln - 1]\n";
+				# we have a preceding printk if it ends
+				# with "\n" ignore it, else it is to blame
+				if ($lines[$ln - 1] =~ m{\bprintk\(}) {
+					if ($rawlines[$ln - 1] !~ m{\\n"}) {
+						$ok = 1;
+					}
+					last;
+				}
+			}
+			if ($ok == 0) {
+				WARN("PRINTK_WITHOUT_KERN_LEVEL",
+				     "printk() should include KERN_ facility level\n" . $herecurr);
+			}
+		}
+
+		if ($line =~ /\bprintk\s*\(\s*KERN_([A-Z]+)/) {
+			my $orig = $1;
+			my $level = lc($orig);
+			$level = "warn" if ($level eq "warning");
+			my $level2 = $level;
+			$level2 = "dbg" if ($level eq "debug");
+			WARN("PREFER_PR_LEVEL",
+			     "Prefer netdev_$level2(netdev, ... then dev_$level2(dev, ... then pr_$level(...  to printk(KERN_$orig ...\n" . $herecurr);
+		}
+
+		if ($line =~ /\bpr_warning\s*\(/) {
+			WARN("PREFER_PR_LEVEL",
+			     "Prefer pr_warn(... to pr_warning(...\n" . $herecurr);
+		}
+
+		if ($line =~ /\bdev_printk\s*\(\s*KERN_([A-Z]+)/) {
+			my $orig = $1;
+			my $level = lc($orig);
+			$level = "warn" if ($level eq "warning");
+			$level = "dbg" if ($level eq "debug");
+			WARN("PREFER_DEV_LEVEL",
+			     "Prefer dev_$level(... to dev_printk(KERN_$orig, ...\n" . $herecurr);
+		}
+
+# function brace can't be on same line, except for #defines of do while,
+# or if closed on same line
+		if (($line=~/$Type\s*$Ident\(.*\).*\s{/) and
+		    !($line=~/\#\s*define.*do\s{/) and !($line=~/}/)) {
+			ERROR("OPEN_BRACE",
+			      "open brace '{' following function declarations go on the next line\n" . $herecurr);
+		}
+
+# open braces for enum, union and struct go on the same line.
+		if ($line =~ /^.\s*{/ &&
+		    $prevline =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?\s*$/) {
+			ERROR("OPEN_BRACE",
+			      "open brace '{' following $1 go on the same line\n" . $hereprev);
+		}
+
+# missing space after union, struct or enum definition
+		if ($line =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?(?:\s+$Ident)?[=\{]/) {
+		    WARN("SPACING",
+			 "missing space after $1 definition\n" . $herecurr);
+		}
+
+# check for spacing round square brackets; allowed:
+#  1. with a type on the left -- int [] a;
+#  2. at the beginning of a line for slice initialisers -- [0...10] = 5,
+#  3. inside a curly brace -- = { [0...10] = 5 }
+		while ($line =~ /(.*?\s)\[/g) {
+			my ($where, $prefix) = ($-[1], $1);
+			if ($prefix !~ /$Type\s+$/ &&
+			    ($where != 0 || $prefix !~ /^.\s+$/) &&
+			    $prefix !~ /[{,]\s+$/) {
+				ERROR("BRACKET_SPACE",
+				      "space prohibited before open square bracket '['\n" . $herecurr);
+			}
+		}
+
+# check for spaces between functions and their parentheses.
+		while ($line =~ /($Ident)\s+\(/g) {
+			my $name = $1;
+			my $ctx_before = substr($line, 0, $-[1]);
+			my $ctx = "$ctx_before$name";
+
+			# Ignore those directives where spaces _are_ permitted.
+			if ($name =~ /^(?:
+				if|for|while|switch|return|case|
+				volatile|__volatile__|
+				__attribute__|format|__extension__|
+				asm|__asm__)$/x)
+			{
+
+			# cpp #define statements have non-optional spaces, ie
+			# if there is a space between the name and the open
+			# parenthesis it is simply not a parameter group.
+			} elsif ($ctx_before =~ /^.\s*\#\s*define\s*$/) {
+
+			# cpp #elif statement condition may start with a (
+			} elsif ($ctx =~ /^.\s*\#\s*elif\s*$/) {
+
+			# If this whole things ends with a type its most
+			# likely a typedef for a function.
+			} elsif ($ctx =~ /$Type$/) {
+
+			} else {
+				WARN("SPACING",
+				     "space prohibited between function name and open parenthesis '('\n" . $herecurr);
+			}
+		}
+
+# check for whitespace before a non-naked semicolon
+		if ($line =~ /^\+.*\S\s+;/) {
+			WARN("SPACING",
+			     "space prohibited before semicolon\n" . $herecurr);
+		}
+
+# Check operator spacing.
+		if (!($line=~/\#\s*include/)) {
+			my $ops = qr{
+				<<=|>>=|<=|>=|==|!=|
+				\+=|-=|\*=|\/=|%=|\^=|\|=|&=|
+				=>|->|<<|>>|<|>|=|!|~|
+				&&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|%|
+				\?|:
+			}x;
+			my @elements = split(/($ops|;)/, $opline);
+			my $off = 0;
+
+			my $blank = copy_spacing($opline);
+
+			for (my $n = 0; $n < $#elements; $n += 2) {
+				$off += length($elements[$n]);
+
+				# Pick up the preceding and succeeding characters.
+				my $ca = substr($opline, 0, $off);
+				my $cc = '';
+				if (length($opline) >= ($off + length($elements[$n + 1]))) {
+					$cc = substr($opline, $off + length($elements[$n + 1]));
+				}
+				my $cb = "$ca$;$cc";
+
+				my $a = '';
+				$a = 'V' if ($elements[$n] ne '');
+				$a = 'W' if ($elements[$n] =~ /\s$/);
+				$a = 'C' if ($elements[$n] =~ /$;$/);
+				$a = 'B' if ($elements[$n] =~ /(\[|\()$/);
+				$a = 'O' if ($elements[$n] eq '');
+				$a = 'E' if ($ca =~ /^\s*$/);
+
+				my $op = $elements[$n + 1];
+
+				my $c = '';
+				if (defined $elements[$n + 2]) {
+					$c = 'V' if ($elements[$n + 2] ne '');
+					$c = 'W' if ($elements[$n + 2] =~ /^\s/);
+					$c = 'C' if ($elements[$n + 2] =~ /^$;/);
+					$c = 'B' if ($elements[$n + 2] =~ /^(\)|\]|;)/);
+					$c = 'O' if ($elements[$n + 2] eq '');
+					$c = 'E' if ($elements[$n + 2] =~ /^\s*\\$/);
+				} else {
+					$c = 'E';
+				}
+
+				my $ctx = "${a}x${c}";
+
+				my $at = "(ctx:$ctx)";
+
+				my $ptr = substr($blank, 0, $off) . "^";
+				my $hereptr = "$hereline$ptr\n";
+
+				# Pull out the value of this operator.
+				my $op_type = substr($curr_values, $off + 1, 1);
+
+				# Get the full operator variant.
+				my $opv = $op . substr($curr_vars, $off, 1);
+
+				# Ignore operators passed as parameters.
+				if ($op_type ne 'V' &&
+				    $ca =~ /\s$/ && $cc =~ /^\s*,/) {
+
+#				# Ignore comments
+#				} elsif ($op =~ /^$;+$/) {
+
+				# ; should have either the end of line or a space or \ after it
+				} elsif ($op eq ';') {
+					if ($ctx !~ /.x[WEBC]/ &&
+					    $cc !~ /^\\/ && $cc !~ /^;/) {
+						ERROR("SPACING",
+						      "space required after that '$op' $at\n" . $hereptr);
+					}
+
+				# // is a comment
+				} elsif ($op eq '//') {
+
+				# No spaces for:
+				#   ->
+				#   :   when part of a bitfield
+				} elsif ($op eq '->' || $opv eq ':B') {
+					if ($ctx =~ /Wx.|.xW/) {
+						ERROR("SPACING",
+						      "spaces prohibited around that '$op' $at\n" . $hereptr);
+					}
+
+				# , must have a space on the right.
+				} elsif ($op eq ',') {
+					if ($ctx !~ /.x[WEC]/ && $cc !~ /^}/) {
+						ERROR("SPACING",
+						      "space required after that '$op' $at\n" . $hereptr);
+					}
+
+				# '*' as part of a type definition -- reported already.
+				} elsif ($opv eq '*_') {
+					#warn "'*' is part of type\n";
+
+				# unary operators should have a space before and
+				# none after.  May be left adjacent to another
+				# unary operator, or a cast
+				} elsif ($op eq '!' || $op eq '~' ||
+					 $opv eq '*U' || $opv eq '-U' ||
+					 $opv eq '&U' || $opv eq '&&U') {
+					if ($ctx !~ /[WEBC]x./ && $ca !~ /(?:\)|!|~|\*|-|\&|\||\+\+|\-\-|\{)$/) {
+						ERROR("SPACING",
+						      "space required before that '$op' $at\n" . $hereptr);
+					}
+					if ($op eq '*' && $cc =~/\s*$Modifier\b/) {
+						# A unary '*' may be const
+
+					} elsif ($ctx =~ /.xW/) {
+						ERROR("SPACING",
+						      "space prohibited after that '$op' $at\n" . $hereptr);
+					}
+
+				# unary ++ and unary -- are allowed no space on one side.
+				} elsif ($op eq '++' or $op eq '--') {
+					if ($ctx !~ /[WEOBC]x[^W]/ && $ctx !~ /[^W]x[WOBEC]/) {
+						ERROR("SPACING",
+						      "space required one side of that '$op' $at\n" . $hereptr);
+					}
+					if ($ctx =~ /Wx[BE]/ ||
+					    ($ctx =~ /Wx./ && $cc =~ /^;/)) {
+						ERROR("SPACING",
+						      "space prohibited before that '$op' $at\n" . $hereptr);
+					}
+					if ($ctx =~ /ExW/) {
+						ERROR("SPACING",
+						      "space prohibited after that '$op' $at\n" . $hereptr);
+					}
+
+
+				# << and >> may either have or not have spaces both sides
+				} elsif ($op eq '<<' or $op eq '>>' or
+					 $op eq '&' or $op eq '^' or $op eq '|' or
+					 $op eq '+' or $op eq '-' or
+					 $op eq '*' or $op eq '/' or
+					 $op eq '%')
+				{
+					if ($ctx =~ /Wx[^WCE]|[^WCE]xW/) {
+						ERROR("SPACING",
+						      "need consistent spacing around '$op' $at\n" .
+							$hereptr);
+					}
+
+				# A colon needs no spaces before when it is
+				# terminating a case value or a label.
+				} elsif ($opv eq ':C' || $opv eq ':L') {
+					if ($ctx =~ /Wx./) {
+						ERROR("SPACING",
+						      "space prohibited before that '$op' $at\n" . $hereptr);
+					}
+
+				# All the others need spaces both sides.
+				} elsif ($ctx !~ /[EWC]x[CWE]/) {
+					my $ok = 0;
+
+					# Ignore email addresses <foo@bar>
+					if (($op eq '<' &&
+					     $cc =~ /^\S+\@\S+>/) ||
+					    ($op eq '>' &&
+					     $ca =~ /<\S+\@\S+$/))
+					{
+					    	$ok = 1;
+					}
+
+					# Ignore ?:
+					if (($opv eq ':O' && $ca =~ /\?$/) ||
+					    ($op eq '?' && $cc =~ /^:/)) {
+					    	$ok = 1;
+					}
+
+					if ($ok == 0) {
+						ERROR("SPACING",
+						      "spaces required around that '$op' $at\n" . $hereptr);
+					}
+				}
+				$off += length($elements[$n + 1]);
+			}
+		}
+
+# check for multiple assignments
+		if ($line =~ /^.\s*$Lval\s*=\s*$Lval\s*=(?!=)/) {
+			CHK("MULTIPLE_ASSIGNMENTS",
+			    "multiple assignments should be avoided\n" . $herecurr);
+		}
+
+## # check for multiple declarations, allowing for a function declaration
+## # continuation.
+## 		if ($line =~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Ident.*/ &&
+## 		    $line !~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Type\s*$Ident.*/) {
+##
+## 			# Remove any bracketed sections to ensure we do not
+## 			# falsly report the parameters of functions.
+## 			my $ln = $line;
+## 			while ($ln =~ s/\([^\(\)]*\)//g) {
+## 			}
+## 			if ($ln =~ /,/) {
+## 				WARN("MULTIPLE_DECLARATION",
+##				     "declaring multiple variables together should be avoided\n" . $herecurr);
+## 			}
+## 		}
+
+#need space before brace following if, while, etc
+		if (($line =~ /\(.*\){/ && $line !~ /\($Type\){/) ||
+		    $line =~ /do{/) {
+			ERROR("SPACING",
+			      "space required before the open brace '{'\n" . $herecurr);
+		}
+
+# closing brace should have a space following it when it has anything
+# on the line
+		if ($line =~ /}(?!(?:,|;|\)))\S/) {
+			ERROR("SPACING",
+			      "space required after that close brace '}'\n" . $herecurr);
+		}
+
+# check spacing on square brackets
+		if ($line =~ /\[\s/ && $line !~ /\[\s*$/) {
+			ERROR("SPACING",
+			      "space prohibited after that open square bracket '['\n" . $herecurr);
+		}
+		if ($line =~ /\s\]/) {
+			ERROR("SPACING",
+			      "space prohibited before that close square bracket ']'\n" . $herecurr);
+		}
+
+# check spacing on parentheses
+		if ($line =~ /\(\s/ && $line !~ /\(\s*(?:\\)?$/ &&
+		    $line !~ /for\s*\(\s+;/) {
+			ERROR("SPACING",
+			      "space prohibited after that open parenthesis '('\n" . $herecurr);
+		}
+		if ($line =~ /(\s+)\)/ && $line !~ /^.\s*\)/ &&
+		    $line !~ /for\s*\(.*;\s+\)/ &&
+		    $line !~ /:\s+\)/) {
+			ERROR("SPACING",
+			      "space prohibited before that close parenthesis ')'\n" . $herecurr);
+		}
+
+#goto labels aren't indented, allow a single space however
+		if ($line=~/^.\s+[A-Za-z\d_]+:(?![0-9]+)/ and
+		   !($line=~/^. [A-Za-z\d_]+:/) and !($line=~/^.\s+default:/)) {
+			WARN("INDENTED_LABEL",
+			     "labels should not be indented\n" . $herecurr);
+		}
+
+# Return is not a function.
+		if (defined($stat) && $stat =~ /^.\s*return(\s*)(\(.*);/s) {
+			my $spacing = $1;
+			my $value = $2;
+
+			# Flatten any parentheses
+			$value =~ s/\(/ \(/g;
+			$value =~ s/\)/\) /g;
+			while ($value =~ s/\[[^\[\]]*\]/1/ ||
+			       $value !~ /(?:$Ident|-?$Constant)\s*
+					     $Compare\s*
+					     (?:$Ident|-?$Constant)/x &&
+			       $value =~ s/\([^\(\)]*\)/1/) {
+			}
+#print "value<$value>\n";
+			if ($value =~ /^\s*(?:$Ident|-?$Constant)\s*$/) {
+				ERROR("RETURN_PARENTHESES",
+				      "return is not a function, parentheses are not required\n" . $herecurr);
+
+			} elsif ($spacing !~ /\s+/) {
+				ERROR("SPACING",
+				      "space required before the open parenthesis '('\n" . $herecurr);
+			}
+		}
+# Return of what appears to be an errno should normally be -'ve
+		if ($line =~ /^.\s*return\s*(E[A-Z]*)\s*;/) {
+			my $name = $1;
+			if ($name ne 'EOF' && $name ne 'ERROR') {
+				WARN("USE_NEGATIVE_ERRNO",
+				     "return of an errno should typically be -ve (return -$1)\n" . $herecurr);
+			}
+		}
+
+# Need a space before open parenthesis after if, while etc
+		if ($line=~/\b(if|while|for|switch)\(/) {
+			ERROR("SPACING", "space required before the open parenthesis '('\n" . $herecurr);
+		}
+
+# Check for illegal assignment in if conditional -- and check for trailing
+# statements after the conditional.
+		if ($line =~ /do\s*(?!{)/) {
+			($stat, $cond, $line_nr_next, $remain_next, $off_next) =
+				ctx_statement_block($linenr, $realcnt, 0)
+					if (!defined $stat);
+			my ($stat_next) = ctx_statement_block($line_nr_next,
+						$remain_next, $off_next);
+			$stat_next =~ s/\n./\n /g;
+			##print "stat<$stat> stat_next<$stat_next>\n";
+
+			if ($stat_next =~ /^\s*while\b/) {
+				# If the statement carries leading newlines,
+				# then count those as offsets.
+				my ($whitespace) =
+					($stat_next =~ /^((?:\s*\n[+-])*\s*)/s);
+				my $offset =
+					statement_rawlines($whitespace) - 1;
+
+				$suppress_whiletrailers{$line_nr_next +
+								$offset} = 1;
+			}
+		}
+		if (!defined $suppress_whiletrailers{$linenr} &&
+		    $line =~ /\b(?:if|while|for)\s*\(/ && $line !~ /^.\s*#/) {
+			my ($s, $c) = ($stat, $cond);
+
+			if ($c =~ /\bif\s*\(.*[^<>!=]=[^=].*/s) {
+				ERROR("ASSIGN_IN_IF",
+				      "do not use assignment in if condition\n" . $herecurr);
+			}
+
+			# Find out what is on the end of the line after the
+			# conditional.
+			substr($s, 0, length($c), '');
+			$s =~ s/\n.*//g;
+			$s =~ s/$;//g; 	# Remove any comments
+			if (length($c) && $s !~ /^\s*{?\s*\\*\s*$/ &&
+			    $c !~ /}\s*while\s*/ && !($c =~ /while/ && $s eq ";"))
+			{
+				# Find out how long the conditional actually is.
+				my @newlines = ($c =~ /\n/gs);
+				my $cond_lines = 1 + $#newlines;
+				my $stat_real = '';
+
+				$stat_real = raw_line($linenr, $cond_lines)
+							. "\n" if ($cond_lines);
+				if (defined($stat_real) && $cond_lines > 1) {
+					$stat_real = "[...]\n$stat_real";
+				}
+
+				ERROR("TRAILING_STATEMENTS",
+				      "trailing statements should be on next line\n" . $herecurr . $stat_real);
+			}
+		}
+
+# Check for bitwise tests written as boolean
+		if ($line =~ /
+			(?:
+				(?:\[|\(|\&\&|\|\|)
+				\s*0[xX][0-9]+\s*
+				(?:\&\&|\|\|)
+			|
+				(?:\&\&|\|\|)
+				\s*0[xX][0-9]+\s*
+				(?:\&\&|\|\||\)|\])
+			)/x)
+		{
+			WARN("HEXADECIMAL_BOOLEAN_TEST",
+			     "boolean test with hexadecimal, perhaps just 1 \& or \|?\n" . $herecurr);
+		}
+
+# if and else should not have general statements after it
+		if ($line =~ /^.\s*(?:}\s*)?else\b(.*)/) {
+			my $s = $1;
+			$s =~ s/$;//g; 	# Remove any comments
+			if ($s !~ /^\s*(?:\sif|(?:{|)\s*\\?\s*$)/) {
+				ERROR("TRAILING_STATEMENTS",
+				      "trailing statements should be on next line\n" . $herecurr);
+			}
+		}
+# if should not continue a brace
+		if ($line =~ /}\s*if\b/) {
+			ERROR("TRAILING_STATEMENTS",
+			      "trailing statements should be on next line\n" .
+				$herecurr);
+		}
+# case and default should not have general statements after them
+		if ($line =~ /^.\s*(?:case\s*.*|default\s*):/g &&
+		    $line !~ /\G(?:
+			(?:\s*$;*)(?:\s*{)?(?:\s*$;*)(?:\s*\\)?\s*$|
+			\s*return\s+
+		    )/xg)
+		{
+			ERROR("TRAILING_STATEMENTS",
+			      "trailing statements should be on next line\n" . $herecurr);
+		}
+
+		# Check for }<nl>else {, these must be at the same
+		# indent level to be relevant to each other.
+		if ($prevline=~/}\s*$/ and $line=~/^.\s*else\s*/ and
+						$previndent == $indent) {
+			ERROR("ELSE_AFTER_BRACE",
+			      "else should follow close brace '}'\n" . $hereprev);
+		}
+
+		#if ($prevline=~/}\s*$/ and $line=~/^.\s*while\s*/ and
+		#				$previndent == $indent) {
+		#	my ($s, $c) = ctx_statement_block($linenr, $realcnt, 0);
+
+		#	# Find out what is on the end of the line after the
+		#	# conditional.
+		#	substr($s, 0, length($c), '');
+		#	$s =~ s/\n.*//g;
+
+		#	if ($s =~ /^\s*;/) {
+		#		ERROR("WHILE_AFTER_BRACE",
+		#		      "while should follow close brace '}'\n" . $hereprev);
+		#	}
+		#}
+
+#CamelCase
+		while ($line =~ m{($Constant|$Lval)}g) {
+			my $var = $1;
+			if ($var !~ /$Constant/ &&
+			    $var =~ /[A-Z]\w*[a-z]|[a-z]\w*[A-Z]/ &&
+			    $var !~ /"^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ &&
+			    !defined $camelcase{$var} &&
+			    $var !~ /[A-Z][A-Z0-9_]*x[A-Z0-9_]*\b/) {
+				$camelcase{$var} = 1;
+				#print "Camelcase line <<$line>> <<$var>>\n";
+				WARN("CAMELCASE",
+				     "Avoid CamelCase: <$var>\n" . $herecurr);
+			}
+		}
+
+#no spaces allowed after \ in define
+		if ($line=~/\#\s*define.*\\\s$/) {
+			WARN("WHITESPACE_AFTER_LINE_CONTINUATION",
+			     "Whitepspace after \\ makes next lines useless\n" . $herecurr);
+		}
+
+#warn if <asm/foo.h> is #included and <linux/foo.h> is available (uses RAW line)
+		if ($tree && $rawline =~ m{^.\s*\#\s*include\s*\<asm\/(.*)\.h\>}) {
+			my $file = "$1.h";
+			my $checkfile = "include/linux/$file";
+			if (-f "$root/$checkfile" &&
+			    $realfile ne $checkfile &&
+			    $1 !~ /$allowed_asm_includes/)
+			{
+				if ($realfile =~ m{^arch/}) {
+					CHK("ARCH_INCLUDE_LINUX",
+					    "Consider using #include <linux/$file> instead of <asm/$file>\n" . $herecurr);
+				} else {
+					WARN("INCLUDE_LINUX",
+					     "Use #include <linux/$file> instead of <asm/$file>\n" . $herecurr);
+				}
+			}
+		}
+
+# multi-statement macros should be enclosed in a do while loop, grab the
+# first statement and ensure its the whole macro if its not enclosed
+# in a known good container
+		if ($realfile !~ m@/vmlinux.lds.h$@ &&
+		    $line =~ /^.\s*\#\s*define\s*$Ident(\()?/) {
+			my $ln = $linenr;
+			my $cnt = $realcnt;
+			my ($off, $dstat, $dcond, $rest);
+			my $ctx = '';
+			($dstat, $dcond, $ln, $cnt, $off) =
+				ctx_statement_block($linenr, $realcnt, 0);
+			$ctx = $dstat;
+			#print "dstat<$dstat> dcond<$dcond> cnt<$cnt> off<$off>\n";
+			#print "LINE<$lines[$ln-1]> len<" . length($lines[$ln-1]) . "\n";
+
+			$dstat =~ s/^.\s*\#\s*define\s+$Ident(?:\([^\)]*\))?\s*//;
+			$dstat =~ s/$;//g;
+			$dstat =~ s/\\\n.//g;
+			$dstat =~ s/^\s*//s;
+			$dstat =~ s/\s*$//s;
+
+			# Flatten any parentheses and braces
+			while ($dstat =~ s/\([^\(\)]*\)/1/ ||
+			       $dstat =~ s/\{[^\{\}]*\}/1/ ||
+			       $dstat =~ s/\[[^\[\]]*\]/1/)
+			{
+			}
+
+			# Flatten any obvious string concatentation.
+			while ($dstat =~ s/("X*")\s*$Ident/$1/ ||
+			       $dstat =~ s/$Ident\s*("X*")/$1/)
+			{
+			}
+
+			my $exceptions = qr{
+				$Declare|
+				module_param_named|
+				MODULE_PARM_DESC|
+				DECLARE_PER_CPU|
+				DEFINE_PER_CPU|
+				__typeof__\(|
+				union|
+				struct|
+				\.$Ident\s*=\s*|
+				^\"|\"$
+			}x;
+			#print "REST<$rest> dstat<$dstat> ctx<$ctx>\n";
+			if ($dstat ne '' &&
+			    $dstat !~ /^(?:$Ident|-?$Constant),$/ &&			# 10, // foo(),
+			    $dstat !~ /^(?:$Ident|-?$Constant);$/ &&			# foo();
+			    $dstat !~ /^[!~-]?(?:$Ident|$Constant)$/ &&		# 10 // foo() // !foo // ~foo // -foo
+			    $dstat !~ /^'X'$/ &&					# character constants
+			    $dstat !~ /$exceptions/ &&
+			    $dstat !~ /^\.$Ident\s*=/ &&				# .foo =
+			    $dstat !~ /^(?:\#\s*$Ident|\#\s*$Constant)\s*$/ &&		# stringification #foo
+			    $dstat !~ /^do\s*$Constant\s*while\s*$Constant;?$/ &&	# do {...} while (...); // do {...} while (...)
+			    $dstat !~ /^for\s*$Constant$/ &&				# for (...)
+			    $dstat !~ /^for\s*$Constant\s+(?:$Ident|-?$Constant)$/ &&	# for (...) bar()
+			    $dstat !~ /^do\s*{/ &&					# do {...
+			    $dstat !~ /^\({/)						# ({...
+			{
+				$ctx =~ s/\n*$//;
+				my $herectx = $here . "\n";
+				my $cnt = statement_rawlines($ctx);
+
+				for (my $n = 0; $n < $cnt; $n++) {
+					$herectx .= raw_line($linenr, $n) . "\n";
+				}
+
+				if ($dstat =~ /;/) {
+					ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE",
+					      "Macros with multiple statements should be enclosed in a do - while loop\n" . "$herectx");
+				} else {
+					ERROR("COMPLEX_MACRO",
+					      "Macros with complex values should be enclosed in parenthesis\n" . "$herectx");
+				}
+			}
+
+# check for line continuations outside of #defines, preprocessor #, and asm
+
+		} else {
+			if ($prevline !~ /^..*\\$/ &&
+			    $line !~ /^\+\s*\#.*\\$/ &&		# preprocessor
+			    $line !~ /^\+.*\b(__asm__|asm)\b.*\\$/ &&	# asm
+			    $line =~ /^\+.*\\$/) {
+				WARN("LINE_CONTINUATIONS",
+				     "Avoid unnecessary line continuations\n" . $herecurr);
+			}
+		}
+
+# do {} while (0) macro tests:
+# single-statement macros do not need to be enclosed in do while (0) loop,
+# macro should not end with a semicolon
+		if ($^V && $^V ge 5.10.0 &&
+		    $realfile !~ m@/vmlinux.lds.h$@ &&
+		    $line =~ /^.\s*\#\s*define\s+$Ident(\()?/) {
+			my $ln = $linenr;
+			my $cnt = $realcnt;
+			my ($off, $dstat, $dcond, $rest);
+			my $ctx = '';
+			($dstat, $dcond, $ln, $cnt, $off) =
+				ctx_statement_block($linenr, $realcnt, 0);
+			$ctx = $dstat;
+
+			$dstat =~ s/\\\n.//g;
+
+			if ($dstat =~ /^\+\s*#\s*define\s+$Ident\s*${balanced_parens}\s*do\s*{(.*)\s*}\s*while\s*\(\s*0\s*\)\s*([;\s]*)\s*$/) {
+				my $stmts = $2;
+				my $semis = $3;
+
+				$ctx =~ s/\n*$//;
+				my $cnt = statement_rawlines($ctx);
+				my $herectx = $here . "\n";
+
+				for (my $n = 0; $n < $cnt; $n++) {
+					$herectx .= raw_line($linenr, $n) . "\n";
+				}
+
+				if (($stmts =~ tr/;/;/) == 1 &&
+				    $stmts !~ /^\s*(if|while|for|switch)\b/) {
+					WARN("SINGLE_STATEMENT_DO_WHILE_MACRO",
+					     "Single statement macros should not use a do {} while (0) loop\n" . "$herectx");
+				}
+				if (defined $semis && $semis ne "") {
+					WARN("DO_WHILE_MACRO_WITH_TRAILING_SEMICOLON",
+					     "do {} while (0) macros should not be semicolon terminated\n" . "$herectx");
+				}
+			}
+		}
+
+# make sure symbols are always wrapped with VMLINUX_SYMBOL() ...
+# all assignments may have only one of the following with an assignment:
+#	.
+#	ALIGN(...)
+#	VMLINUX_SYMBOL(...)
+		if ($realfile eq 'vmlinux.lds.h' && $line =~ /(?:(?:^|\s)$Ident\s*=|=\s*$Ident(?:\s|$))/) {
+			WARN("MISSING_VMLINUX_SYMBOL",
+			     "vmlinux.lds.h needs VMLINUX_SYMBOL() around C-visible symbols\n" . $herecurr);
+		}
+
+# check for redundant bracing round if etc
+		if ($line =~ /(^.*)\bif\b/ && $1 !~ /else\s*$/) {
+			my ($level, $endln, @chunks) =
+				ctx_statement_full($linenr, $realcnt, 1);
+			#if ($#chunks > 0) {
+			#	print "chunks<$#chunks> linenr<$linenr> endln<$endln> level<$level>\n";
+			#	my $count = 0;
+			#	for my $chunk (@chunks) {
+			#		my ($cond, $block) = @{$chunk};
+			#		print "APW: count<$count> <<$cond>><<$block>>\n";
+			#		$count++;
+			#	}
+			#}
+			if ($#chunks > 0 && $level == 0) {
+				my @allowed = ();
+				my $allow = 0;
+				my $seen = 0;
+				my $herectx = $here . "\n";
+				my $ln = $linenr - 1;
+				for my $chunk (@chunks) {
+					my ($cond, $block) = @{$chunk};
+
+					# If the condition carries leading newlines, then count those as offsets.
+					my ($whitespace) = ($cond =~ /^((?:\s*\n[+-])*\s*)/s);
+					my $offset = statement_rawlines($whitespace) - 1;
+
+					$allowed[$allow] = 0;
+					#print "COND<$cond> whitespace<$whitespace> offset<$offset>\n";
+
+					# We have looked at and allowed this specific line.
+					$suppress_ifbraces{$ln + $offset} = 1;
+
+					$herectx .= "$rawlines[$ln + $offset]\n[...]\n";
+					$ln += statement_rawlines($block) - 1;
+
+					substr($block, 0, length($cond), '');
+
+					$seen++ if ($block =~ /^\s*{/);
+
+					#print "cond<$cond> block<$block> allowed<$allowed[$allow]>\n";
+					#if (statement_lines($cond) > 1) {
+					#	#print "APW: ALLOWED: cond<$cond>\n";
+					#	$allowed[$allow] = 1;
+					#}
+					#if ($block =~/\b(?:if|for|while)\b/) {
+					#	#print "APW: ALLOWED: block<$block>\n";
+					#	$allowed[$allow] = 1;
+					#}
+					#if (statement_block_size($block) > 1) {
+					#	#print "APW: ALLOWED: lines block<$block>\n";
+					#	$allowed[$allow] = 1;
+					#}
+					#$allow++;
+				}
+				if (!$seen) {
+					ERROR("BRACES",
+					      "braces {} are necessary for all arms of this statement\n" . $herectx);
+				}
+				#if ($seen) {
+				#	my $sum_allowed = 0;
+				#	foreach (@allowed) {
+				#		$sum_allowed += $_;
+				#	}
+				#	if ($sum_allowed == 0) {
+				#		WARN("BRACES",
+				#		     "braces {} are not necessary for any arm of this statement\n" . $herectx);
+				#	} elsif ($sum_allowed != $allow &&
+				#		 $seen != $allow) {
+				#		CHK("BRACES",
+				#		    "braces {} should be used on all arms of this statement\n" . $herectx);
+				#	}
+				#}
+			}
+		}
+		if (!defined $suppress_ifbraces{$linenr - 1} &&
+					$line =~ /\b(if|while|for|else)\b/) {
+			my $allowed = 0;
+
+			# Check the pre-context.
+			if (substr($line, 0, $-[0]) =~ /(#\s*)$/) {
+				#print "APW: ALLOWED: pre<$1>\n";
+				$allowed = 1;
+			}
+
+			my ($level, $endln, @chunks) =
+				ctx_statement_full($linenr, $realcnt, $-[0]);
+
+			# Check the condition.
+			my ($cond, $block) = @{$chunks[0]};
+			#print "CHECKING<$linenr> cond<$cond> block<$block>\n";
+			if (defined $cond) {
+				substr($block, 0, length($cond), '');
+			}
+			if ($cond =~ /\bwhile/ && $block =~ /^;/) {
+				#print "APW: ALLOWED: block<$block>";
+				$allowed = 1;
+			}
+			#if ($block =~/\b(?:if|for|while)\b/) {
+			#	print "APW: ALLOWED: block<$block>\n";
+			#	$allowed = 1;
+			#}
+			
+			# Check the post-context.
+			if (defined $chunks[1]) {
+				my ($cond, $block) = @{$chunks[1]};
+				if (defined $cond) {
+					substr($block, 0, length($cond), '');
+				}
+				if ($block =~ /^\s*\{/) {
+					#print "APW: ALLOWED: chunk-1 block<$block>\n";
+					#$allowed = 1;
+				}
+			}
+			if ($level == 0 && !($block =~ /^\s*\{/) && !$allowed) {
+				my $herectx = $here . "\n";
+				my $cnt = statement_rawlines($block);
+
+				for (my $n = 0; $n < $cnt; $n++) {
+					$herectx .= raw_line($linenr, $n) . "\n";
+				}
+
+				WARN("BRACES",
+				     "braces {} are needed for every statement block\n" . $herectx);
+			}
+		}
+
+# check for unnecessary blank lines around braces
+		if (($line =~ /^.\s*}\s*$/ && $prevline =~ /^.\s*$/)) {
+			CHK("BRACES",
+			    "Blank lines aren't necessary before a close brace '}'\n" . $hereprev);
+		}
+		if (($line =~ /^.\s*$/ && $prevline =~ /^..*{\s*$/)) {
+			CHK("BRACES",
+			    "Blank lines aren't necessary after an open brace '{'\n" . $hereprev);
+		}
+
+# no volatiles please
+		my $asm_volatile = qr{\b(__asm__|asm)\s+(__volatile__|volatile)\b};
+		if ($line =~ /\bvolatile\b/ && $line !~ /$asm_volatile/) {
+			WARN("VOLATILE",
+			     "Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt\n" . $herecurr);
+		}
+
+# warn about #if 0
+		if ($line =~ /^.\s*\#\s*if\s+0\b/) {
+			CHK("REDUNDANT_CODE",
+			    "if this code is redundant consider removing it\n" .
+				$herecurr);
+		}
+
+# check for needless "if (<foo>) fn(<foo>)" uses
+		if ($prevline =~ /\bif\s*\(\s*($Lval)\s*\)/) {
+			my $expr = '\s*\(\s*' . quotemeta($1) . '\s*\)\s*;';
+			if ($line =~ /\b(kfree|usb_free_urb|debugfs_remove(?:_recursive)?)$expr/) {
+				WARN('NEEDLESS_IF',
+				     "$1(NULL) is safe this check is probably not required\n" . $hereprev);
+			}
+		}
+
+# prefer usleep_range over udelay
+		if ($line =~ /\budelay\s*\(\s*(\d+)\s*\)/) {
+			# ignore udelay's < 10, however
+			if (! ($1 < 10) ) {
+				CHK("USLEEP_RANGE",
+				    "usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt\n" . $line);
+			}
+		}
+
+# warn about unexpectedly long msleep's
+		if ($line =~ /\bmsleep\s*\((\d+)\);/) {
+			if ($1 < 20) {
+				WARN("MSLEEP",
+				     "msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.txt\n" . $line);
+			}
+		}
+
+# warn about #ifdefs in C files
+#		if ($line =~ /^.\s*\#\s*if(|n)def/ && ($realfile =~ /\.c$/)) {
+#			print "#ifdef in C files should be avoided\n";
+#			print "$herecurr";
+#			$clean = 0;
+#		}
+
+# warn about spacing in #ifdefs
+		if ($line =~ /^.\s*\#\s*(ifdef|ifndef|elif)\s\s+/) {
+			ERROR("SPACING",
+			      "exactly one space required after that #$1\n" . $herecurr);
+		}
+
+# check for spinlock_t definitions without a comment.
+		if ($line =~ /^.\s*(struct\s+mutex|spinlock_t)\s+\S+;/ ||
+		    $line =~ /^.\s*(DEFINE_MUTEX)\s*\(/) {
+			my $which = $1;
+			if (!ctx_has_comment($first_line, $linenr)) {
+				CHK("UNCOMMENTED_DEFINITION",
+				    "$1 definition without comment\n" . $herecurr);
+			}
+		}
+# check for memory barriers without a comment.
+		if ($line =~ /\b(mb|rmb|wmb|read_barrier_depends|smp_mb|smp_rmb|smp_wmb|smp_read_barrier_depends)\(/) {
+			if (!ctx_has_comment($first_line, $linenr)) {
+				CHK("MEMORY_BARRIER",
+				    "memory barrier without comment\n" . $herecurr);
+			}
+		}
+# check of hardware specific defines
+		if ($line =~ m@^.\s*\#\s*if.*\b(__i386__|__powerpc64__|__sun__|__s390x__)\b@ && $realfile !~ m@include/asm-@) {
+			CHK("ARCH_DEFINES",
+			    "architecture specific defines should be avoided\n" .  $herecurr);
+		}
+
+# Check that the storage class is at the beginning of a declaration
+		if ($line =~ /\b$Storage\b/ && $line !~ /^.\s*$Storage\b/) {
+			WARN("STORAGE_CLASS",
+			     "storage class should be at the beginning of the declaration\n" . $herecurr)
+		}
+
+# check the location of the inline attribute, that it is between
+# storage class and type.
+		if ($line =~ /\b$Type\s+$Inline\b/ ||
+		    $line =~ /\b$Inline\s+$Storage\b/) {
+			ERROR("INLINE_LOCATION",
+			      "inline keyword should sit between storage class and type\n" . $herecurr);
+		}
+
+# Check for __inline__ and __inline, prefer inline
+		if ($line =~ /\b(__inline__|__inline)\b/) {
+			WARN("INLINE",
+			     "plain inline is preferred over $1\n" . $herecurr);
+		}
+
+# Check for __attribute__ format(printf, prefer __printf
+		if ($line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf/) {
+			WARN("PREFER_PRINTF",
+			     "__printf(string-index, first-to-check) is preferred over __attribute__((format(printf, string-index, first-to-check)))\n" . $herecurr);
+		}
+
+# Check for __attribute__ format(scanf, prefer __scanf
+		if ($line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\b/) {
+			WARN("PREFER_SCANF",
+			     "__scanf(string-index, first-to-check) is preferred over __attribute__((format(scanf, string-index, first-to-check)))\n" . $herecurr);
+		}
+
+# check for sizeof(&)
+		if ($line =~ /\bsizeof\s*\(\s*\&/) {
+			WARN("SIZEOF_ADDRESS",
+			     "sizeof(& should be avoided\n" . $herecurr);
+		}
+
+# check for sizeof without parenthesis
+		if ($line =~ /\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/) {
+			WARN("SIZEOF_PARENTHESIS",
+			     "sizeof $1 should be sizeof($1)\n" . $herecurr);
+		}
+
+# check for line continuations in quoted strings with odd counts of "
+		if ($rawline =~ /\\$/ && $rawline =~ tr/"/"/ % 2) {
+			WARN("LINE_CONTINUATIONS",
+			     "Avoid line continuations in quoted strings\n" . $herecurr);
+		}
+
+# check for struct spinlock declarations
+		if ($line =~ /^.\s*\bstruct\s+spinlock\s+\w+\s*;/) {
+			WARN("USE_SPINLOCK_T",
+			     "struct spinlock should be spinlock_t\n" . $herecurr);
+		}
+
+# check for seq_printf uses that could be seq_puts
+		if ($line =~ /\bseq_printf\s*\(/) {
+			my $fmt = get_quoted_string($line, $rawline);
+			if ($fmt !~ /[^\\]\%/) {
+				WARN("PREFER_SEQ_PUTS",
+				     "Prefer seq_puts to seq_printf\n" . $herecurr);
+			}
+		}
+
+# Check for misused memsets
+		if ($^V && $^V ge 5.10.0 &&
+		    defined $stat &&
+		    $stat =~ /^\+(?:.*?)\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*$FuncArg\s*\)/s) {
+
+			my $ms_addr = $2;
+			my $ms_val = $7;
+			my $ms_size = $12;
+
+			if ($ms_size =~ /^(0x|)0$/i) {
+				ERROR("MEMSET",
+				      "memset to 0's uses 0 as the 2nd argument, not the 3rd\n" . "$here\n$stat\n");
+			} elsif ($ms_size =~ /^(0x|)1$/i) {
+				WARN("MEMSET",
+				     "single byte memset is suspicious. Swapped 2nd/3rd argument?\n" . "$here\n$stat\n");
+			}
+		}
+
+# typecasts on min/max could be min_t/max_t
+		if ($^V && $^V ge 5.10.0 &&
+		    defined $stat &&
+		    $stat =~ /^\+(?:.*?)\b(min|max)\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\)/) {
+			if (defined $2 || defined $7) {
+				my $call = $1;
+				my $cast1 = deparenthesize($2);
+				my $arg1 = $3;
+				my $cast2 = deparenthesize($7);
+				my $arg2 = $8;
+				my $cast;
+
+				if ($cast1 ne "" && $cast2 ne "" && $cast1 ne $cast2) {
+					$cast = "$cast1 or $cast2";
+				} elsif ($cast1 ne "") {
+					$cast = $cast1;
+				} else {
+					$cast = $cast2;
+				}
+				WARN("MINMAX",
+				     "$call() should probably be ${call}_t($cast, $arg1, $arg2)\n" . "$here\n$stat\n");
+			}
+		}
+
+# check usleep_range arguments
+		if ($^V && $^V ge 5.10.0 &&
+		    defined $stat &&
+		    $stat =~ /^\+(?:.*?)\busleep_range\s*\(\s*($FuncArg)\s*,\s*($FuncArg)\s*\)/) {
+			my $min = $1;
+			my $max = $7;
+			if ($min eq $max) {
+				WARN("USLEEP_RANGE",
+				     "usleep_range should not use min == max args; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n");
+			} elsif ($min =~ /^\d+$/ && $max =~ /^\d+$/ &&
+				 $min > $max) {
+				WARN("USLEEP_RANGE",
+				     "usleep_range args reversed, use min then max; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n");
+			}
+		}
+
+# check for new externs in .c files.
+		if ($realfile =~ /\.c$/ && defined $stat &&
+		    $stat =~ /^.\s*(?:extern\s+)?$Type\s+($Ident)(\s*)\(/s)
+		{
+			my $function_name = $1;
+			my $paren_space = $2;
+
+			my $s = $stat;
+			if (defined $cond) {
+				substr($s, 0, length($cond), '');
+			}
+			if ($s =~ /^\s*;/ &&
+			    $function_name ne 'uninitialized_var')
+			{
+				WARN("AVOID_EXTERNS",
+				     "externs should be avoided in .c files\n" .  $herecurr);
+			}
+
+			if ($paren_space =~ /\n/) {
+				WARN("FUNCTION_ARGUMENTS",
+				     "arguments for function declarations should follow identifier\n" . $herecurr);
+			}
+
+		} elsif ($realfile =~ /\.c$/ && defined $stat &&
+		    $stat =~ /^.\s*extern\s+/)
+		{
+			WARN("AVOID_EXTERNS",
+			     "externs should be avoided in .c files\n" .  $herecurr);
+		}
+
+# checks for new __setup's
+		if ($rawline =~ /\b__setup\("([^"]*)"/) {
+			my $name = $1;
+
+			if (!grep(/$name/, @setup_docs)) {
+				CHK("UNDOCUMENTED_SETUP",
+				    "__setup appears un-documented -- check Documentation/kernel-parameters.txt\n" . $herecurr);
+			}
+		}
+
+# check for pointless casting of kmalloc return
+		if ($line =~ /\*\s*\)\s*[kv][czm]alloc(_node){0,1}\b/) {
+			WARN("UNNECESSARY_CASTS",
+			     "unnecessary cast may hide bugs, see http://c-faq.com/malloc/mallocnocast.html\n" . $herecurr);
+		}
+
+# check for krealloc arg reuse
+		if ($^V && $^V ge 5.10.0 &&
+		    $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*krealloc\s*\(\s*\1\s*,/) {
+			WARN("KREALLOC_ARG_REUSE",
+			     "Reusing the krealloc arg is almost always a bug\n" . $herecurr);
+		}
+
+# check for alloc argument mismatch
+		if ($line =~ /\b(kcalloc|kmalloc_array)\s*\(\s*sizeof\b/) {
+			WARN("ALLOC_ARRAY_ARGS",
+			     "$1 uses number as first arg, sizeof is generally wrong\n" . $herecurr);
+		}
+
+# check for multiple semicolons
+		if ($line =~ /;\s*;\s*$/) {
+			WARN("ONE_SEMICOLON",
+			     "Statements terminations use 1 semicolon\n" . $herecurr);
+		}
+
+# check for switch/default statements without a break;
+		if ($^V && $^V ge 5.10.0 &&
+		    defined $stat &&
+		    $stat =~ /^\+[$;\s]*(?:case[$;\s]+\w+[$;\s]*:[$;\s]*|)*[$;\s]*\bdefault[$;\s]*:[$;\s]*;/g) {
+			my $ctx = '';
+			my $herectx = $here . "\n";
+			my $cnt = statement_rawlines($stat);
+			for (my $n = 0; $n < $cnt; $n++) {
+				$herectx .= raw_line($linenr, $n) . "\n";
+			}
+			WARN("DEFAULT_NO_BREAK",
+			     "switch default: should use break\n" . $herectx);
+		}
+
+# check for gcc specific __FUNCTION__
+		if ($line =~ /__FUNCTION__/) {
+			WARN("USE_FUNC",
+			     "__func__ should be used instead of gcc specific __FUNCTION__\n"  . $herecurr);
+		}
+
+# check for use of yield()
+		if ($line =~ /\byield\s*\(\s*\)/) {
+			WARN("YIELD",
+			     "Using yield() is generally wrong. See yield() kernel-doc (sched/core.c)\n"  . $herecurr);
+		}
+
+# check for semaphores initialized locked
+		if ($line =~ /^.\s*sema_init.+,\W?0\W?\)/) {
+			WARN("CONSIDER_COMPLETION",
+			     "consider using a completion\n" . $herecurr);
+		}
+
+# recommend kstrto* over simple_strto* and strict_strto*
+		if ($line =~ /\b((simple|strict)_(strto(l|ll|ul|ull)))\s*\(/) {
+			WARN("CONSIDER_KSTRTO",
+			     "$1 is obsolete, use k$3 instead\n" . $herecurr);
+		}
+
+# check for __initcall(), use device_initcall() explicitly please
+		if ($line =~ /^.\s*__initcall\s*\(/) {
+			WARN("USE_DEVICE_INITCALL",
+			     "please use device_initcall() instead of __initcall()\n" . $herecurr);
+		}
+
+# check for various ops structs, ensure they are const.
+		my $struct_ops = qr{acpi_dock_ops|
+				address_space_operations|
+				backlight_ops|
+				block_device_operations|
+				dentry_operations|
+				dev_pm_ops|
+				dma_map_ops|
+				extent_io_ops|
+				file_lock_operations|
+				file_operations|
+				hv_ops|
+				ide_dma_ops|
+				intel_dvo_dev_ops|
+				item_operations|
+				iwl_ops|
+				kgdb_arch|
+				kgdb_io|
+				kset_uevent_ops|
+				lock_manager_operations|
+				microcode_ops|
+				mtrr_ops|
+				neigh_ops|
+				nlmsvc_binding|
+				pci_raw_ops|
+				pipe_buf_operations|
+				platform_hibernation_ops|
+				platform_suspend_ops|
+				proto_ops|
+				rpc_pipe_ops|
+				seq_operations|
+				snd_ac97_build_ops|
+				soc_pcmcia_socket_ops|
+				stacktrace_ops|
+				sysfs_ops|
+				tty_operations|
+				usb_mon_operations|
+				wd_ops}x;
+		if ($line !~ /\bconst\b/ &&
+		    $line =~ /\bstruct\s+($struct_ops)\b/) {
+			WARN("CONST_STRUCT",
+			     "struct $1 should normally be const\n" .
+				$herecurr);
+		}
+
+# use of NR_CPUS is usually wrong
+# ignore definitions of NR_CPUS and usage to define arrays as likely right
+		if ($line =~ /\bNR_CPUS\b/ &&
+		    $line !~ /^.\s*\s*#\s*if\b.*\bNR_CPUS\b/ &&
+		    $line !~ /^.\s*\s*#\s*define\b.*\bNR_CPUS\b/ &&
+		    $line !~ /^.\s*$Declare\s.*\[[^\]]*NR_CPUS[^\]]*\]/ &&
+		    $line !~ /\[[^\]]*\.\.\.[^\]]*NR_CPUS[^\]]*\]/ &&
+		    $line !~ /\[[^\]]*NR_CPUS[^\]]*\.\.\.[^\]]*\]/)
+		{
+			WARN("NR_CPUS",
+			     "usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc\n" . $herecurr);
+		}
+
+# check for %L{u,d,i} in strings
+		my $string;
+		while ($line =~ /(?:^|")([X\t]*)(?:"|$)/g) {
+			$string = substr($rawline, $-[1], $+[1] - $-[1]);
+			$string =~ s/%%/__/g;
+			if ($string =~ /(?<!%)%L[udi]/) {
+				WARN("PRINTF_L",
+				     "\%Ld/%Lu are not-standard C, use %lld/%llu\n" . $herecurr);
+				last;
+			}
+		}
+
+# whine mightly about in_atomic
+		if ($line =~ /\bin_atomic\s*\(/) {
+			if ($realfile =~ m@^drivers/@) {
+				ERROR("IN_ATOMIC",
+				      "do not use in_atomic in drivers\n" . $herecurr);
+			} elsif ($realfile !~ m@^kernel/@) {
+				WARN("IN_ATOMIC",
+				     "use of in_atomic() is incorrect outside core kernel code\n" . $herecurr);
+			}
+		}
+
+# check for lockdep_set_novalidate_class
+		if ($line =~ /^.\s*lockdep_set_novalidate_class\s*\(/ ||
+		    $line =~ /__lockdep_no_validate__\s*\)/ ) {
+			if ($realfile !~ m@^kernel/lockdep@ &&
+			    $realfile !~ m@^include/linux/lockdep@ &&
+			    $realfile !~ m@^drivers/base/core@) {
+				ERROR("LOCKDEP",
+				      "lockdep_no_validate class is reserved for device->mutex.\n" . $herecurr);
+			}
+		}
+
+		if ($line =~ /debugfs_create_file.*S_IWUGO/ ||
+		    $line =~ /DEVICE_ATTR.*S_IWUGO/ ) {
+			WARN("EXPORTED_WORLD_WRITABLE",
+			     "Exporting world writable files is usually an error. Consider more restrictive permissions.\n" . $herecurr);
+		}
+	}
+
+	# If we have no input at all, then there is nothing to report on
+	# so just keep quiet.
+	if ($#rawlines == -1) {
+		exit(0);
+	}
+
+	# In mailback mode only produce a report in the negative, for
+	# things that appear to be patches.
+	if ($mailback && ($clean == 1 || !$is_patch)) {
+		exit(0);
+	}
+
+	# This is not a patch, and we are are in 'no-patch' mode so
+	# just keep quiet.
+	if (!$chk_patch && !$is_patch) {
+		exit(0);
+	}
+
+	if (!$is_patch) {
+		ERROR("NOT_UNIFIED_DIFF",
+		      "Does not appear to be a unified-diff format patch\n");
+	}
+	if ($is_patch && $chk_signoff && $signoff == 0) {
+		ERROR("MISSING_SIGN_OFF",
+		      "Missing Signed-off-by: line(s)\n");
+	}
+
+	print report_dump();
+	if ($summary && !($clean == 1 && $quiet == 1)) {
+		print "$filename " if ($summary_file);
+		print "total: $cnt_error errors, $cnt_warn warnings, " .
+			(($check)? "$cnt_chk checks, " : "") .
+			"$cnt_lines lines checked\n";
+		print "\n" if ($quiet == 0);
+	}
+
+	if ($quiet == 0) {
+
+		if ($^V lt 5.10.0) {
+			print("NOTE: perl $^V is not modern enough to detect all possible issues.\n");
+			print("An upgrade to at least perl v5.10.0 is suggested.\n\n");
+		}
+
+		# If there were whitespace errors which cleanpatch can fix
+		# then suggest that.
+		if ($rpt_cleaners) {
+			print "NOTE: whitespace errors detected, you may wish to use scripts/cleanpatch or\n";
+			print "      scripts/cleanfile\n\n";
+			$rpt_cleaners = 0;
+		}
+	}
+
+	if ($quiet == 0 && keys %ignore_type) {
+	    print "NOTE: Ignored message types:";
+	    foreach my $ignore (sort keys %ignore_type) {
+		print " $ignore";
+	    }
+	    print "\n\n";
+	}
+
+	if ($clean == 1 && $quiet == 0) {
+		print "$vname has no obvious style problems and is ready for submission.\n"
+	}
+	if ($clean == 0 && $quiet == 0) {
+		print << "EOM";
+$vname has style problems, please review.
+
+If any of these errors are false positives, please report
+them to the maintainer, see CHECKPATCH in MAINTAINERS.
+EOM
+	}
+
+	return $clean;
+}
diff --git a/libopencm3/scripts/data/lpc43xx/README b/libopencm3/scripts/data/lpc43xx/README
new file mode 100644
index 0000000..b768936
--- /dev/null
+++ b/libopencm3/scripts/data/lpc43xx/README
@@ -0,0 +1,23 @@
+These files contain information derived from the LPC43xx user manual (UM10503).
+They are intended to be used by scripts for the generation of header files and
+functions.
+
+Each line describes a field within a register.  The comma separated values are:
+	register name (as found in include/lpc43xx/*.h),
+	bit position,
+	length in bits,
+	field name,
+	description/comment (may be empty if not specified in data sheet),
+	reset value (may be empty if not specified in data sheet),
+	access (may be empty if not specified in data sheet)
+
+The access field may consist of any of the following codes:
+	r:   read only
+	rw:  read/write
+	rwc: read/write one to clear
+	rwo: read/write once
+	rws: read/write one to set
+	w:   write only
+	ws:  write one to set
+
+Descriptions containing commas are quoted.
diff --git a/libopencm3/scripts/data/lpc43xx/adc.yaml b/libopencm3/scripts/data/lpc43xx/adc.yaml
new file mode 100644
index 0000000..9256e2a
--- /dev/null
+++ b/libopencm3/scripts/data/lpc43xx/adc.yaml
@@ -0,0 +1,607 @@
+!!omap
+- ADC0_CR:
+    fields: !!omap
+    - SEL:
+        access: rw
+        description: Selects which of the ADCn_[7:0] inputs are to be sampled and
+          converted
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - CLKDIV:
+        access: rw
+        description: The ADC clock is divided by the CLKDIV value plus one to produce
+          the clock for the A/D converter
+        lsb: 8
+        reset_value: '0'
+        width: 8
+    - BURST:
+        access: rw
+        description: Controls Burst mode
+        lsb: 16
+        reset_value: '0'
+        width: 1
+    - CLKS:
+        access: rw
+        description: This field selects the number of clocks used for each conversion
+          in Burst mode and the number of bits of accuracy of the result in the LS
+          bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).
+        lsb: 17
+        reset_value: '0'
+        width: 3
+    - PDN:
+        access: rw
+        description: Power mode
+        lsb: 21
+        reset_value: '0'
+        width: 1
+    - START:
+        access: rw
+        description: Controls the start of an A/D conversion when the BURST bit is
+          0
+        lsb: 24
+        reset_value: '0'
+        width: 3
+    - EDGE:
+        access: rw
+        description: Controls rising or falling edge on the selected signal for the
+          start of a conversion
+        lsb: 27
+        reset_value: '0'
+        width: 1
+- ADC1_CR:
+    fields: !!omap
+    - SEL:
+        access: rw
+        description: Selects which of the ADCn_[7:0] inputs are to be sampled and
+          converted
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - CLKDIV:
+        access: rw
+        description: The ADC clock is divided by the CLKDIV value plus one to produce
+          the clock for the A/D converter
+        lsb: 8
+        reset_value: '0'
+        width: 8
+    - BURST:
+        access: rw
+        description: Controls Burst mode
+        lsb: 16
+        reset_value: '0'
+        width: 1
+    - CLKS:
+        access: rw
+        description: This field selects the number of clocks used for each conversion
+          in Burst mode and the number of bits of accuracy of the result in the LS
+          bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).
+        lsb: 17
+        reset_value: '0'
+        width: 3
+    - PDN:
+        access: rw
+        description: Power mode
+        lsb: 21
+        reset_value: '0'
+        width: 1
+    - START:
+        access: rw
+        description: Controls the start of an A/D conversion when the BURST bit is
+          0
+        lsb: 24
+        reset_value: '0'
+        width: 3
+    - EDGE:
+        access: rw
+        description: Controls rising or falling edge on the selected signal for the
+          start of a conversion
+        lsb: 27
+        reset_value: '0'
+        width: 1
+- ADC0_GDR:
+    fields: !!omap
+    - V_VREF:
+        access: r
+        description: When DONE is 1, this field contains a binary fraction representing
+          the voltage on the ADCn pin selected by the SEL field, divided by the reference
+          voltage on the VDDA pin
+        lsb: 6
+        reset_value: '0'
+        width: 10
+    - CHN:
+        access: r
+        description: These bits contain the channel from which the LS bits were converted
+        lsb: 24
+        reset_value: '0'
+        width: 3
+    - OVERRUN:
+        access: r
+        description: This bit is 1 in burst mode if the results of one or more conversions
+          was (were) lost and overwritten before the conversion that produced the
+          result in the V_VREF bits
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - DONE:
+        access: r
+        description: This bit is set to 1 when an analog-to-digital conversion completes.
+          It is cleared when this register is read and when the AD0/1CR register is
+          written
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- ADC1_GDR:
+    fields: !!omap
+    - V_VREF:
+        access: r
+        description: When DONE is 1, this field contains a binary fraction representing
+          the voltage on the ADCn pin selected by the SEL field, divided by the reference
+          voltage on the VDDA pin
+        lsb: 6
+        reset_value: '0'
+        width: 10
+    - CHN:
+        access: r
+        description: These bits contain the channel from which the LS bits were converted
+        lsb: 24
+        reset_value: '0'
+        width: 3
+    - OVERRUN:
+        access: r
+        description: This bit is 1 in burst mode if the results of one or more conversions
+          was (were) lost and overwritten before the conversion that produced the
+          result in the V_VREF bits
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - DONE:
+        access: r
+        description: This bit is set to 1 when an analog-to-digital conversion completes.
+          It is cleared when this register is read and when the AD0/1CR register is
+          written
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- ADC0_INTEN:
+    fields: !!omap
+    - ADINTEN:
+        access: rw
+        description: These bits allow control over which A/D channels generate interrupts
+          for conversion completion
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - ADGINTEN:
+        access: rw
+        description: When 1, enables the global DONE flag in ADDR to generate an interrupt.
+          When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate
+          interrupts.
+        lsb: 8
+        reset_value: '1'
+        width: 1
+- ADC1_INTEN:
+    fields: !!omap
+    - ADINTEN:
+        access: rw
+        description: These bits allow control over which A/D channels generate interrupts
+          for conversion completion
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - ADGINTEN:
+        access: rw
+        description: When 1, enables the global DONE flag in ADDR to generate an interrupt.
+          When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate
+          interrupts.
+        lsb: 8
+        reset_value: '1'
+        width: 1
+- ADC0_DR0:
+    fields: !!omap
+    - V_VREF:
+        access: r
+        description: When DONE is 1, this field contains a binary fraction representing
+          the voltage on the ADC0 pin divided by the reference voltage on the VDDA
+          pin
+        lsb: 6
+        reset_value: '0'
+        width: 10
+    - OVERRUN:
+        access: r
+        description: This bit is 1 in burst mode if the results of one or more conversions
+          was (were) lost and overwritten before the conversion that produced the
+          result in the V_VREF bits in this register.
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - DONE:
+        access: r
+        description: This bit is set to 1 when an A/D conversion completes.
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- ADC1_DR0:
+    fields: !!omap
+    - V_VREF:
+        access: r
+        description: When DONE is 1, this field contains a binary fraction representing
+          the voltage on the ADC0 pin divided by the reference voltage on the VDDA
+          pin
+        lsb: 6
+        reset_value: '0'
+        width: 10
+    - OVERRUN:
+        access: r
+        description: This bit is 1 in burst mode if the results of one or more conversions
+          was (were) lost and overwritten before the conversion that produced the
+          result in the V_VREF bits in this register.
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - DONE:
+        access: r
+        description: This bit is set to 1 when an A/D conversion completes.
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- ADC0_DR1:
+    fields: !!omap
+    - V_VREF:
+        access: r
+        description: When DONE is 1, this field contains a binary fraction representing
+          the voltage on the ADC1 pin divided by the reference voltage on the VDDA
+          pin
+        lsb: 6
+        reset_value: '0'
+        width: 10
+    - OVERRUN:
+        access: r
+        description: This bit is 1 in burst mode if the results of one or more conversions
+          was (were) lost and overwritten before the conversion that produced the
+          result in the V_VREF bits in this register.
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - DONE:
+        access: r
+        description: This bit is set to 1 when an A/D conversion completes.
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- ADC1_DR1:
+    fields: !!omap
+    - V_VREF:
+        access: r
+        description: When DONE is 1, this field contains a binary fraction representing
+          the voltage on the ADC1 pin divided by the reference voltage on the VDDA
+          pin
+        lsb: 6
+        reset_value: '0'
+        width: 10
+    - OVERRUN:
+        access: r
+        description: This bit is 1 in burst mode if the results of one or more conversions
+          was (were) lost and overwritten before the conversion that produced the
+          result in the V_VREF bits in this register.
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - DONE:
+        access: r
+        description: This bit is set to 1 when an A/D conversion completes.
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- ADC0_DR2:
+    fields: !!omap
+    - V_VREF:
+        access: r
+        description: When DONE is 1, this field contains a binary fraction representing
+          the voltage on the ADC2 pin divided by the reference voltage on the VDDA
+          pin
+        lsb: 6
+        reset_value: '0'
+        width: 10
+    - OVERRUN:
+        access: r
+        description: This bit is 1 in burst mode if the results of one or more conversions
+          was (were) lost and overwritten before the conversion that produced the
+          result in the V_VREF bits in this register.
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - DONE:
+        access: r
+        description: This bit is set to 1 when an A/D conversion completes.
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- ADC1_DR2:
+    fields: !!omap
+    - V_VREF:
+        access: r
+        description: When DONE is 1, this field contains a binary fraction representing
+          the voltage on the ADC2 pin divided by the reference voltage on the VDDA
+          pin
+        lsb: 6
+        reset_value: '0'
+        width: 10
+    - OVERRUN:
+        access: r
+        description: This bit is 1 in burst mode if the results of one or more conversions
+          was (were) lost and overwritten before the conversion that produced the
+          result in the V_VREF bits in this register.
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - DONE:
+        access: r
+        description: This bit is set to 1 when an A/D conversion completes.
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- ADC0_DR3:
+    fields: !!omap
+    - V_VREF:
+        access: r
+        description: When DONE is 1, this field contains a binary fraction representing
+          the voltage on the ADC3 pin divided by the reference voltage on the VDDA
+          pin
+        lsb: 6
+        reset_value: '0'
+        width: 10
+    - OVERRUN:
+        access: r
+        description: This bit is 1 in burst mode if the results of one or more conversions
+          was (were) lost and overwritten before the conversion that produced the
+          result in the V_VREF bits in this register.
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - DONE:
+        access: r
+        description: This bit is set to 1 when an A/D conversion completes.
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- ADC1_DR3:
+    fields: !!omap
+    - V_VREF:
+        access: r
+        description: When DONE is 1, this field contains a binary fraction representing
+          the voltage on the ADC3 pin divided by the reference voltage on the VDDA
+          pin
+        lsb: 6
+        reset_value: '0'
+        width: 10
+    - OVERRUN:
+        access: r
+        description: This bit is 1 in burst mode if the results of one or more conversions
+          was (were) lost and overwritten before the conversion that produced the
+          result in the V_VREF bits in this register.
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - DONE:
+        access: r
+        description: This bit is set to 1 when an A/D conversion completes.
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- ADC0_DR4:
+    fields: !!omap
+    - V_VREF:
+        access: r
+        description: When DONE is 1, this field contains a binary fraction representing
+          the voltage on the ADC4 pin divided by the reference voltage on the VDDA
+          pin
+        lsb: 6
+        reset_value: '0'
+        width: 10
+    - OVERRUN:
+        access: r
+        description: This bit is 1 in burst mode if the results of one or more conversions
+          was (were) lost and overwritten before the conversion that produced the
+          result in the V_VREF bits in this register.
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - DONE:
+        access: r
+        description: This bit is set to 1 when an A/D conversion completes.
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- ADC1_DR4:
+    fields: !!omap
+    - V_VREF:
+        access: r
+        description: When DONE is 1, this field contains a binary fraction representing
+          the voltage on the ADC4 pin divided by the reference voltage on the VDDA
+          pin
+        lsb: 6
+        reset_value: '0'
+        width: 10
+    - OVERRUN:
+        access: r
+        description: This bit is 1 in burst mode if the results of one or more conversions
+          was (were) lost and overwritten before the conversion that produced the
+          result in the V_VREF bits in this register.
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - DONE:
+        access: r
+        description: This bit is set to 1 when an A/D conversion completes.
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- ADC0_DR5:
+    fields: !!omap
+    - V_VREF:
+        access: r
+        description: When DONE is 1, this field contains a binary fraction representing
+          the voltage on the ADC5 pin divided by the reference voltage on the VDDA
+          pin
+        lsb: 6
+        reset_value: '0'
+        width: 10
+    - OVERRUN:
+        access: r
+        description: This bit is 1 in burst mode if the results of one or more conversions
+          was (were) lost and overwritten before the conversion that produced the
+          result in the V_VREF bits in this register.
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - DONE:
+        access: r
+        description: This bit is set to 1 when an A/D conversion completes.
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- ADC1_DR5:
+    fields: !!omap
+    - V_VREF:
+        access: r
+        description: When DONE is 1, this field contains a binary fraction representing
+          the voltage on the ADC5 pin divided by the reference voltage on the VDDA
+          pin
+        lsb: 6
+        reset_value: '0'
+        width: 10
+    - OVERRUN:
+        access: r
+        description: This bit is 1 in burst mode if the results of one or more conversions
+          was (were) lost and overwritten before the conversion that produced the
+          result in the V_VREF bits in this register.
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - DONE:
+        access: r
+        description: This bit is set to 1 when an A/D conversion completes.
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- ADC0_DR6:
+    fields: !!omap
+    - V_VREF:
+        access: r
+        description: When DONE is 1, this field contains a binary fraction representing
+          the voltage on the ADC6 pin divided by the reference voltage on the VDDA
+          pin
+        lsb: 6
+        reset_value: '0'
+        width: 10
+    - OVERRUN:
+        access: r
+        description: This bit is 1 in burst mode if the results of one or more conversions
+          was (were) lost and overwritten before the conversion that produced the
+          result in the V_VREF bits in this register.
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - DONE:
+        access: r
+        description: This bit is set to 1 when an A/D conversion completes.
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- ADC1_DR6:
+    fields: !!omap
+    - V_VREF:
+        access: r
+        description: When DONE is 1, this field contains a binary fraction representing
+          the voltage on the ADC6 pin divided by the reference voltage on the VDDA
+          pin
+        lsb: 6
+        reset_value: '0'
+        width: 10
+    - OVERRUN:
+        access: r
+        description: This bit is 1 in burst mode if the results of one or more conversions
+          was (were) lost and overwritten before the conversion that produced the
+          result in the V_VREF bits in this register.
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - DONE:
+        access: r
+        description: This bit is set to 1 when an A/D conversion completes.
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- ADC0_DR7:
+    fields: !!omap
+    - V_VREF:
+        access: r
+        description: When DONE is 1, this field contains a binary fraction representing
+          the voltage on the ADC7 pin divided by the reference voltage on the VDDA
+          pin
+        lsb: 6
+        reset_value: '0'
+        width: 10
+    - OVERRUN:
+        access: r
+        description: This bit is 1 in burst mode if the results of one or more conversions
+          was (were) lost and overwritten before the conversion that produced the
+          result in the V_VREF bits in this register.
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - DONE:
+        access: r
+        description: This bit is set to 1 when an A/D conversion completes.
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- ADC1_DR7:
+    fields: !!omap
+    - V_VREF:
+        access: r
+        description: When DONE is 1, this field contains a binary fraction representing
+          the voltage on the ADC7 pin divided by the reference voltage on the VDDA
+          pin
+        lsb: 6
+        reset_value: '0'
+        width: 10
+    - OVERRUN:
+        access: r
+        description: This bit is 1 in burst mode if the results of one or more conversions
+          was (were) lost and overwritten before the conversion that produced the
+          result in the V_VREF bits in this register.
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - DONE:
+        access: r
+        description: This bit is set to 1 when an A/D conversion completes.
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- ADC0_STAT:
+    fields: !!omap
+    - DONE:
+        access: r
+        description: These bits mirror the DONE status flags that appear in the result
+          register for each A/D channel.
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - OVERRUN:
+        access: r
+        description: These bits mirror the OVERRRUN status flags that appear in the
+          result register for each A/D channel.
+        lsb: 8
+        reset_value: '0'
+        width: 8
+    - ADINT:
+        access: r
+        description: This bit is the A/D interrupt flag. It is one when any of the
+          individual A/D channel Done flags is asserted and enabled to contribute
+          to the A/D interrupt via the ADINTEN register.
+        lsb: 16
+        reset_value: '0'
+        width: 1
diff --git a/libopencm3/scripts/data/lpc43xx/atimer.yaml b/libopencm3/scripts/data/lpc43xx/atimer.yaml
new file mode 100644
index 0000000..010a25d
--- /dev/null
+++ b/libopencm3/scripts/data/lpc43xx/atimer.yaml
@@ -0,0 +1,71 @@
+!!omap
+- ATIMER_DOWNCOUNTER:
+    fields: !!omap
+    - CVAL:
+        access: rw
+        description: When equal to zero an interrupt is raised
+        lsb: 0
+        reset_value: '0'
+        width: 16
+- ATIMER_PRESET:
+    fields: !!omap
+    - PRESETVAL:
+        access: rw
+        description: Value loaded in DOWNCOUNTER when DOWNCOUNTER equals zero
+        lsb: 0
+        reset_value: '0'
+        width: 16
+- ATIMER_CLR_EN:
+    fields: !!omap
+    - CLR_EN:
+        access: w
+        description: Writing a 1 to this bit clears the interrupt enable bit in the
+          ENABLE register
+        lsb: 0
+        reset_value: '0'
+        width: 1
+- ATIMER_SET_EN:
+    fields: !!omap
+    - SET_EN:
+        access: w
+        description: Writing a 1 to this bit sets the interrupt enable bit in the
+          ENABLE register
+        lsb: 0
+        reset_value: '0'
+        width: 1
+- ATIMER_STATUS:
+    fields: !!omap
+    - STAT:
+        access: r
+        description: A 1 in this bit shows that the STATUS interrupt has been raised
+        lsb: 0
+        reset_value: '0'
+        width: 1
+- ATIMER_ENABLE:
+    fields: !!omap
+    - ENA:
+        access: r
+        description: A 1 in this bit shows that the STATUS interrupt has been enabled
+          and that the STATUS interrupt request signal is asserted when STAT = 1 in
+          the STATUS register
+        lsb: 0
+        reset_value: '0'
+        width: 1
+- ATIMER_CLR_STAT:
+    fields: !!omap
+    - CSTAT:
+        access: w
+        description: Writing a 1 to this bit clears the STATUS interrupt bit in the
+          STATUS register
+        lsb: 0
+        reset_value: '0'
+        width: 1
+- ATIMER_SET_STAT:
+    fields: !!omap
+    - SSTAT:
+        access: w
+        description: Writing a 1 to this bit sets the STATUS interrupt bit in the
+          STATUS register
+        lsb: 0
+        reset_value: '0'
+        width: 1
diff --git a/libopencm3/scripts/data/lpc43xx/ccu.yaml b/libopencm3/scripts/data/lpc43xx/ccu.yaml
new file mode 100644
index 0000000..b2d225f
--- /dev/null
+++ b/libopencm3/scripts/data/lpc43xx/ccu.yaml
@@ -0,0 +1,2391 @@
+!!omap
+- CCU1_PM:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Initiate power-down mode
+        lsb: 0
+        reset_value: '0'
+        width: 1
+- CCU1_BASE_STAT:
+    fields: !!omap
+    - BASE_APB3_CLK_IND:
+        access: r
+        description: Base clock indicator for BASE_APB3_CLK
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - BASE_APB1_CLK_IND:
+        access: r
+        description: Base clock indicator for BASE_APB1_CLK
+        lsb: 1
+        reset_value: '1'
+        width: 1
+    - BASE_SPIFI_CLK_IND:
+        access: r
+        description: Base clock indicator for BASE_SPIFI_CLK
+        lsb: 2
+        reset_value: '1'
+        width: 1
+    - BASE_M4_CLK_IND:
+        access: r
+        description: Base clock indicator for BASE_M4_CLK
+        lsb: 3
+        reset_value: '1'
+        width: 1
+    - BASE_PERIPH_CLK_IND:
+        access: r
+        description: Base clock indicator for BASE_PERIPH_CLK
+        lsb: 6
+        reset_value: '1'
+        width: 1
+    - BASE_USB0_CLK_IND:
+        access: r
+        description: Base clock indicator for BASE_USB0_CLK
+        lsb: 7
+        reset_value: '1'
+        width: 1
+    - BASE_USB1_CLK_IND:
+        access: r
+        description: Base clock indicator for BASE_USB1_CLK
+        lsb: 8
+        reset_value: '1'
+        width: 1
+    - BASE_SPI_CLK_IND:
+        access: r
+        description: Base clock indicator for BASE_SPI_CLK
+        lsb: 9
+        reset_value: '1'
+        width: 1
+- CCU1_CLK_APB3_BUS_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_APB3_BUS_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_APB3_I2C1_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_APB3_I2C1_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_APB3_DAC_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_APB3_DAC_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_APB3_ADC0_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_APB3_ADC0_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_APB3_ADC1_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_APB3_ADC1_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_APB3_CAN0_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_APB3_CAN0_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_APB1_BUS_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_APB1_BUS_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_APB1_MOTOCONPWM_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_APB1_MOTOCONPWM_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_APB1_I2C0_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_APB1_I2C0_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_APB1_I2S_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_APB1_I2S_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_APB1_CAN1_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_APB1_CAN1_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_SPIFI_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_SPIFI_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_BUS_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_BUS_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_SPIFI_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_SPIFI_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_GPIO_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_GPIO_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_LCD_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_LCD_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_ETHERNET_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_ETHERNET_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_USB0_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_USB0_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_EMC_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_EMC_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_SDIO_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_SDIO_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_DMA_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_DMA_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_M4CORE_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_M4CORE_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_SCT_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_SCT_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_USB1_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_USB1_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_EMCDIV_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - DIV:
+        access: rw
+        description: Clock divider value
+        lsb: 5
+        reset_value: '0'
+        width: 3
+- CCU1_CLK_M4_EMCDIV_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_M0APP_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_M0APP_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_VADC_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_VADC_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_WWDT_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_WWDT_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_USART0_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_USART0_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_UART1_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_UART1_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_SSP0_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_SSP0_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_TIMER0_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_TIMER0_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_TIMER1_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_TIMER1_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_SCU_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_SCU_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_CREG_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_CREG_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_RITIMER_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_RITIMER_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_USART2_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_USART2_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_USART3_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_USART3_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_TIMER2_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_TIMER2_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_TIMER3_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_TIMER3_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_SSP1_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_SSP1_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_QEI_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_M4_QEI_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_PERIPH_BUS_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_PERIPH_BUS_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_PERIPH_CORE_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_PERIPH_CORE_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_PERIPH_SGPIO_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_PERIPH_SGPIO_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_USB0_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_USB0_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_USB1_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_USB1_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_SPI_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_SPI_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_VADC_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU1_CLK_VADC_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU2_PM:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Initiate power-down mode
+        lsb: 0
+        reset_value: '0'
+        width: 1
+- CCU2_BASE_STAT:
+    fields: !!omap
+    - BASE_UART3_CLK_IND:
+        access: r
+        description: Base clock indicator for BASE_UART3_CLK
+        lsb: 1
+        reset_value: '1'
+        width: 1
+    - BASE_UART2_CLK_IND:
+        access: r
+        description: Base clock indicator for BASE_UART2_CLK
+        lsb: 2
+        reset_value: '1'
+        width: 1
+    - BASE_UART1_CLK_IND:
+        access: r
+        description: Base clock indicator for BASE_UART1_CLK
+        lsb: 3
+        reset_value: '1'
+        width: 1
+    - BASE_UART0_CLK_IND:
+        access: r
+        description: Base clock indicator for BASE_UART0_CLK
+        lsb: 4
+        reset_value: '1'
+        width: 1
+    - BASE_SSP1_CLK_IND:
+        access: r
+        description: Base clock indicator for BASE_SSP1_CLK
+        lsb: 5
+        reset_value: '1'
+        width: 1
+    - BASE_SSP0_CLK_IND:
+        access: r
+        description: Base clock indicator for BASE_SSP0_CLK
+        lsb: 6
+        reset_value: '1'
+        width: 1
+- CCU2_CLK_APLL_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU2_CLK_APLL_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU2_CLK_APB2_USART3_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU2_CLK_APB2_USART3_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU2_CLK_APB2_USART2_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU2_CLK_APB2_USART2_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU2_CLK_APB0_UART1_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU2_CLK_APB0_UART1_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU2_CLK_APB0_USART0_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU2_CLK_APB0_USART0_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU2_CLK_APB2_SSP1_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU2_CLK_APB2_SSP1_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU2_CLK_APB0_SSP0_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU2_CLK_APB0_SSP0_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU2_CLK_SDIO_CFG:
+    fields: !!omap
+    - RUN:
+        access: rw
+        description: Run enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: rw
+        description: Auto (AHB disable mechanism) enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: rw
+        description: Wake-up mechanism enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- CCU2_CLK_SDIO_STAT:
+    fields: !!omap
+    - RUN:
+        access: r
+        description: Run enable status
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - AUTO:
+        access: r
+        description: Auto (AHB disable mechanism) enable status
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP:
+        access: r
+        description: Wake-up mechanism enable status
+        lsb: 2
+        reset_value: '0'
+        width: 1
diff --git a/libopencm3/scripts/data/lpc43xx/cgu.yaml b/libopencm3/scripts/data/lpc43xx/cgu.yaml
new file mode 100644
index 0000000..f55b8d0
--- /dev/null
+++ b/libopencm3/scripts/data/lpc43xx/cgu.yaml
@@ -0,0 +1,937 @@
+!!omap
+- CGU_FREQ_MON:
+    fields: !!omap
+    - RCNT:
+        access: rw
+        description: 9-bit reference clock-counter value
+        lsb: 0
+        reset_value: '0'
+        width: 9
+    - FCNT:
+        access: r
+        description: 14-bit selected clock-counter value
+        lsb: 9
+        reset_value: '0'
+        width: 14
+    - MEAS:
+        access: rw
+        description: Measure frequency
+        lsb: 23
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock-source selection for the clock to be measured
+        lsb: 24
+        reset_value: '0'
+        width: 5
+- CGU_XTAL_OSC_CTRL:
+    fields: !!omap
+    - ENABLE:
+        access: rw
+        description: Oscillator-pad enable
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - BYPASS:
+        access: rw
+        description: Configure crystal operation or external-clock input pin XTAL1
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - HF:
+        access: rw
+        description: Select frequency range
+        lsb: 2
+        reset_value: '1'
+        width: 1
+- CGU_PLL0USB_STAT:
+    fields: !!omap
+    - LOCK:
+        access: r
+        description: PLL0 lock indicator
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - FR:
+        access: r
+        description: PLL0 free running indicator
+        lsb: 1
+        reset_value: '0'
+        width: 1
+- CGU_PLL0USB_CTRL:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: PLL0 power down
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - BYPASS:
+        access: rw
+        description: Input clock bypass control
+        lsb: 1
+        reset_value: '1'
+        width: 1
+    - DIRECTI:
+        access: rw
+        description: PLL0 direct input
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - DIRECTO:
+        access: rw
+        description: PLL0 direct output
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - CLKEN:
+        access: rw
+        description: PLL0 clock enable
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - FRM:
+        access: rw
+        description: Free running mode
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_PLL0USB_MDIV:
+    fields: !!omap
+    - MDEC:
+        access: rw
+        description: Decoded M-divider coefficient value
+        lsb: 0
+        reset_value: '0x5B6A'
+        width: 17
+    - SELP:
+        access: rw
+        description: Bandwidth select P value
+        lsb: 17
+        reset_value: '0x1C'
+        width: 5
+    - SELI:
+        access: rw
+        description: Bandwidth select I value
+        lsb: 22
+        reset_value: '0x17'
+        width: 6
+    - SELR:
+        access: rw
+        description: Bandwidth select R value
+        lsb: 28
+        reset_value: '0x0'
+        width: 4
+- CGU_PLL0USB_NP_DIV:
+    fields: !!omap
+    - PDEC:
+        access: rw
+        description: Decoded P-divider coefficient value
+        lsb: 0
+        reset_value: '0x02'
+        width: 7
+    - NDEC:
+        access: rw
+        description: Decoded N-divider coefficient value
+        lsb: 12
+        reset_value: '0xB1'
+        width: 10
+- CGU_PLL0AUDIO_STAT:
+    fields: !!omap
+    - LOCK:
+        access: r
+        description: PLL0 lock indicator
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - FR:
+        access: r
+        description: PLL0 free running indicator
+        lsb: 1
+        reset_value: '0'
+        width: 1
+- CGU_PLL0AUDIO_CTRL:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: PLL0 power down
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - BYPASS:
+        access: rw
+        description: Input clock bypass control
+        lsb: 1
+        reset_value: '1'
+        width: 1
+    - DIRECTI:
+        access: rw
+        description: PLL0 direct input
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - DIRECTO:
+        access: rw
+        description: PLL0 direct output
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - CLKEN:
+        access: rw
+        description: PLL0 clock enable
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - FRM:
+        access: rw
+        description: Free running mode
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - PLLFRACT_REQ:
+        access: rw
+        description: Fractional PLL word write request
+        lsb: 12
+        reset_value: '0'
+        width: 1
+    - SEL_EXT:
+        access: rw
+        description: Select fractional divider
+        lsb: 13
+        reset_value: '0'
+        width: 1
+    - MOD_PD:
+        access: rw
+        description: Sigma-Delta modulator power-down
+        lsb: 14
+        reset_value: '1'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_PLL0AUDIO_MDIV:
+    fields: !!omap
+    - MDEC:
+        access: rw
+        description: Decoded M-divider coefficient value
+        lsb: 0
+        reset_value: '0x5B6A'
+        width: 17
+- CGU_PLL0AUDIO_NP_DIV:
+    fields: !!omap
+    - PDEC:
+        access: rw
+        description: Decoded P-divider coefficient value
+        lsb: 0
+        reset_value: '0x02'
+        width: 7
+    - NDEC:
+        access: rw
+        description: Decoded N-divider coefficient value
+        lsb: 12
+        reset_value: '0xB1'
+        width: 10
+- CGU_PLLAUDIO_FRAC:
+    fields: !!omap
+    - PLLFRACT_CTRL:
+        access: rw
+        description: PLL fractional divider control word
+        lsb: 0
+        reset_value: '0x00'
+        width: 22
+- CGU_PLL1_STAT:
+    fields: !!omap
+    - LOCK:
+        access: r
+        description: PLL1 lock indicator
+        lsb: 0
+        reset_value: '0'
+        width: 1
+- CGU_PLL1_CTRL:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: PLL1 power down
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - BYPASS:
+        access: rw
+        description: Input clock bypass control
+        lsb: 1
+        reset_value: '1'
+        width: 1
+    - FBSEL:
+        access: rw
+        description: PLL feedback select
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - DIRECT:
+        access: rw
+        description: PLL direct CCO output
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - PSEL:
+        access: rw
+        description: Post-divider division ratio P
+        lsb: 8
+        reset_value: '0x1'
+        width: 2
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - NSEL:
+        access: rw
+        description: Pre-divider division ratio N
+        lsb: 12
+        reset_value: '0x2'
+        width: 2
+    - MSEL:
+        access: rw
+        description: Feedback-divider division ratio (M)
+        lsb: 16
+        reset_value: '0x18'
+        width: 8
+    - CLK_SEL:
+        access: rw
+        description: Clock-source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_IDIVA_CTRL:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Integer divider power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - IDIV:
+        access: rw
+        description: Integer divider A divider value (1/(IDIV + 1))
+        lsb: 2
+        reset_value: '0x0'
+        width: 2
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_IDIVB_CTRL:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Integer divider power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - IDIV:
+        access: rw
+        description: Integer divider B divider value (1/(IDIV + 1))
+        lsb: 2
+        reset_value: '0x0'
+        width: 4
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_IDIVC_CTRL:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Integer divider power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - IDIV:
+        access: rw
+        description: Integer divider C divider value (1/(IDIV + 1))
+        lsb: 2
+        reset_value: '0x0'
+        width: 4
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_IDIVD_CTRL:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Integer divider power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - IDIV:
+        access: rw
+        description: Integer divider D divider value (1/(IDIV + 1))
+        lsb: 2
+        reset_value: '0x0'
+        width: 4
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_IDIVE_CTRL:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Integer divider power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - IDIV:
+        access: rw
+        description: Integer divider E divider value (1/(IDIV + 1))
+        lsb: 2
+        reset_value: '0x00'
+        width: 8
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_SAFE_CLK:
+    fields: !!omap
+    - PD:
+        access: r
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: r
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: r
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_USB0_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x07'
+        width: 5
+- CGU_BASE_PERIPH_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_USB1_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_M4_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_SPIFI_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_SPI_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_PHY_RX_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_PHY_TX_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_APB1_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_APB3_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_LCD_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_VADC_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_SDIO_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_SSP0_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_SSP1_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_UART0_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_UART1_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_UART2_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_UART3_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_OUT_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_APLL_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_CGU_OUT0_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
+- CGU_BASE_CGU_OUT1_CLK:
+    fields: !!omap
+    - PD:
+        access: rw
+        description: Output stage power down
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - AUTOBLOCK:
+        access: rw
+        description: Block clock automatically during frequency change
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CLK_SEL:
+        access: rw
+        description: Clock source selection
+        lsb: 24
+        reset_value: '0x01'
+        width: 5
diff --git a/libopencm3/scripts/data/lpc43xx/creg.yaml b/libopencm3/scripts/data/lpc43xx/creg.yaml
new file mode 100644
index 0000000..3fb8ab7
--- /dev/null
+++ b/libopencm3/scripts/data/lpc43xx/creg.yaml
@@ -0,0 +1,312 @@
+!!omap
+- CREG_CREG0:
+    fields: !!omap
+    - EN1KHZ:
+        access: rw
+        description: Enable 1 kHz output
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EN32KHZ:
+        access: rw
+        description: Enable 32 kHz output
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - RESET32KHZ:
+        access: rw
+        description: 32 kHz oscillator reset
+        lsb: 2
+        reset_value: '1'
+        width: 1
+    - PD32KHZ:
+        access: rw
+        description: 32 kHz power control
+        lsb: 3
+        reset_value: '1'
+        width: 1
+    - USB0PHY:
+        access: rw
+        description: USB0 PHY power control
+        lsb: 5
+        reset_value: '1'
+        width: 1
+    - ALARMCTRL:
+        access: rw
+        description: RTC_ALARM pin output control
+        lsb: 6
+        reset_value: '0'
+        width: 2
+    - BODLVL1:
+        access: rw
+        description: BOD trip level to generate an interrupt
+        lsb: 8
+        reset_value: '0x3'
+        width: 2
+    - BODLVL2:
+        access: rw
+        description: BOD trip level to generate a reset
+        lsb: 10
+        reset_value: '0x3'
+        width: 2
+    - SAMPLECTRL:
+        access: rw
+        description: SAMPLE pin input/output control
+        lsb: 12
+        reset_value: '0'
+        width: 2
+    - WAKEUP0CTRL:
+        access: rw
+        description: WAKEUP0 pin input/output control
+        lsb: 14
+        reset_value: '0'
+        width: 2
+    - WAKEUP1CTRL:
+        access: rw
+        description: WAKEUP1 pin input/output control
+        lsb: 16
+        reset_value: '0'
+        width: 2
+- CREG_M4MEMMAP:
+    fields: !!omap
+    - M4MAP:
+        access: rw
+        description: Shadow address when accessing memory at address 0x00000000
+        lsb: 12
+        reset_value: '0x10400000'
+        width: 20
+- CREG_CREG5:
+    fields: !!omap
+    - M4TAPSEL:
+        access: rw
+        description: JTAG debug select for M4 core
+        lsb: 6
+        reset_value: '1'
+        width: 1
+    - M0APPTAPSEL:
+        access: rw
+        description: JTAG debug select for M0 co-processor
+        lsb: 9
+        reset_value: '1'
+        width: 1
+- CREG_DMAMUX:
+    fields: !!omap
+    - DMAMUXPER0:
+        access: rw
+        description: Select DMA to peripheral connection for DMA peripheral 0
+        lsb: 0
+        reset_value: '0'
+        width: 2
+    - DMAMUXPER1:
+        access: rw
+        description: Select DMA to peripheral connection for DMA peripheral 1
+        lsb: 2
+        reset_value: '0'
+        width: 2
+    - DMAMUXPER2:
+        access: rw
+        description: Select DMA to peripheral connection for DMA peripheral 2
+        lsb: 4
+        reset_value: '0'
+        width: 2
+    - DMAMUXPER3:
+        access: rw
+        description: Select DMA to peripheral connection for DMA peripheral 3
+        lsb: 6
+        reset_value: '0'
+        width: 2
+    - DMAMUXPER4:
+        access: rw
+        description: Select DMA to peripheral connection for DMA peripheral 4
+        lsb: 8
+        reset_value: '0'
+        width: 2
+    - DMAMUXPER5:
+        access: rw
+        description: Select DMA to peripheral connection for DMA peripheral 5
+        lsb: 10
+        reset_value: '0'
+        width: 2
+    - DMAMUXPER6:
+        access: rw
+        description: Select DMA to peripheral connection for DMA peripheral 6
+        lsb: 12
+        reset_value: '0'
+        width: 2
+    - DMAMUXPER7:
+        access: rw
+        description: Select DMA to peripheral connection for DMA peripheral 7
+        lsb: 14
+        reset_value: '0'
+        width: 2
+    - DMAMUXPER8:
+        access: rw
+        description: Select DMA to peripheral connection for DMA peripheral 8
+        lsb: 16
+        reset_value: '0'
+        width: 2
+    - DMAMUXPER9:
+        access: rw
+        description: Select DMA to peripheral connection for DMA peripheral 9
+        lsb: 18
+        reset_value: '0'
+        width: 2
+    - DMAMUXPER10:
+        access: rw
+        description: Select DMA to peripheral connection for DMA peripheral 10
+        lsb: 20
+        reset_value: '0'
+        width: 2
+    - DMAMUXPER11:
+        access: rw
+        description: Select DMA to peripheral connection for DMA peripheral 11
+        lsb: 22
+        reset_value: '0'
+        width: 2
+    - DMAMUXPER12:
+        access: rw
+        description: Select DMA to peripheral connection for DMA peripheral 12
+        lsb: 24
+        reset_value: '0'
+        width: 2
+    - DMAMUXPER13:
+        access: rw
+        description: Select DMA to peripheral connection for DMA peripheral 13
+        lsb: 26
+        reset_value: '0'
+        width: 2
+    - DMAMUXPER14:
+        access: rw
+        description: Select DMA to peripheral connection for DMA peripheral 14
+        lsb: 28
+        reset_value: '0'
+        width: 2
+    - DMAMUXPER15:
+        access: rw
+        description: Select DMA to peripheral connection for DMA peripheral 15
+        lsb: 30
+        reset_value: '0'
+        width: 2
+- CREG_FLASHCFGA:
+    fields: !!omap
+    - FLASHTIM:
+        access: rw
+        description: Flash access time. The value of this field plus 1 gives the number
+          of BASE_M4_CLK clocks used for a flash access
+        lsb: 12
+        reset_value: ''
+        width: 4
+    - POW:
+        access: rw
+        description: Flash bank A power control
+        lsb: 31
+        reset_value: '1'
+        width: 1
+- CREG_FLASHCFGB:
+    fields: !!omap
+    - FLASHTIM:
+        access: rw
+        description: Flash access time. The value of this field plus 1 gives the number
+          of BASE_M4_CLK clocks used for a flash access
+        lsb: 12
+        reset_value: ''
+        width: 4
+    - POW:
+        access: rw
+        description: Flash bank B power control
+        lsb: 31
+        reset_value: '1'
+        width: 1
+- CREG_ETBCFG:
+    fields: !!omap
+    - ETB:
+        access: rw
+        description: Select SRAM interface
+        lsb: 0
+        reset_value: '1'
+        width: 1
+- CREG_CREG6:
+    fields: !!omap
+    - ETHMODE:
+        access: rw
+        description: Selects the Ethernet mode. Reset the ethernet after changing
+          the PHY interface
+        lsb: 0
+        reset_value: ''
+        width: 3
+    - CTOUTCTRL:
+        access: rw
+        description: Selects the functionality of the SCT outputs
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - I2S0_TX_SCK_IN_SEL:
+        access: rw
+        description: I2S0_TX_SCK input select
+        lsb: 12
+        reset_value: '0'
+        width: 1
+    - I2S0_RX_SCK_IN_SEL:
+        access: rw
+        description: I2S0_RX_SCK input select
+        lsb: 13
+        reset_value: '0'
+        width: 1
+    - I2S1_TX_SCK_IN_SEL:
+        access: rw
+        description: I2S1_TX_SCK input select
+        lsb: 14
+        reset_value: '0'
+        width: 1
+    - I2S1_RX_SCK_IN_SEL:
+        access: rw
+        description: I2S1_RX_SCK input select
+        lsb: 15
+        reset_value: '0'
+        width: 1
+    - EMC_CLK_SEL:
+        access: rw
+        description: EMC_CLK divided clock select
+        lsb: 16
+        reset_value: '0'
+        width: 1
+- CREG_M4TXEVENT:
+    fields: !!omap
+    - TXEVCLR:
+        access: rw
+        description: Cortex-M4 TXEV event
+        lsb: 0
+        reset_value: '0'
+        width: 1
+- CREG_M0TXEVENT:
+    fields: !!omap
+    - TXEVCLR:
+        access: rw
+        description: Cortex-M0 TXEV event
+        lsb: 0
+        reset_value: '0'
+        width: 1
+- CREG_M0APPMEMMAP:
+    fields: !!omap
+    - M0APPMAP:
+        access: rw
+        description: Shadow address when accessing memory at address 0x00000000
+        lsb: 12
+        reset_value: '0x20000000'
+        width: 20
+- CREG_USB0FLADJ:
+    fields: !!omap
+    - FLTV:
+        access: rw
+        description: Frame length timing value
+        lsb: 0
+        reset_value: '0x20'
+        width: 6
+- CREG_USB1FLADJ:
+    fields: !!omap
+    - FLTV:
+        access: rw
+        description: Frame length timing value
+        lsb: 0
+        reset_value: '0x20'
+        width: 6
diff --git a/libopencm3/scripts/data/lpc43xx/csv2yaml.py b/libopencm3/scripts/data/lpc43xx/csv2yaml.py
new file mode 100755
index 0000000..1ec9a41
--- /dev/null
+++ b/libopencm3/scripts/data/lpc43xx/csv2yaml.py
@@ -0,0 +1,37 @@
+#!/usr/bin/env python
+
+import sys
+import yaml
+import csv
+from collections import OrderedDict
+import yaml_odict
+ 
+def convert_file(fname):
+    reader = csv.reader(open(fname, 'r'))
+
+    registers = OrderedDict()
+    for register_name, lsb, width, field_name, description, reset_value, access in reader:
+        if register_name not in registers:
+            registers[register_name] = {
+                'fields': OrderedDict(),
+            }
+
+        register = registers[register_name]
+        fields = register['fields']
+        if field_name in fields:
+            raise RuntimeError('Duplicate field name "%s" in register "%s"' %
+                    field_name, register_name)
+        else:
+            fields[field_name] = {
+                'lsb': int(lsb),
+                'width': int(width),
+                'description': description,
+                'reset_value': reset_value,
+                'access': access,
+            }
+
+    with open(fname.replace('.csv', '.yaml'), 'w') as out_file:
+        yaml.dump(registers, out_file, default_flow_style=False)
+
+for fname in sys.argv[1:]:
+    convert_file(fname)
diff --git a/libopencm3/scripts/data/lpc43xx/eventrouter.yaml b/libopencm3/scripts/data/lpc43xx/eventrouter.yaml
new file mode 100644
index 0000000..677b0d9
--- /dev/null
+++ b/libopencm3/scripts/data/lpc43xx/eventrouter.yaml
@@ -0,0 +1,959 @@
+!!omap
+- EVENTROUTER_HILO:
+    fields: !!omap
+    - WAKEUP0_L:
+        access: rw
+        description: Level detect mode for WAKEUP0 event
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - WAKEUP1_L:
+        access: rw
+        description: Level detect mode for WAKEUP1 event
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP2_L:
+        access: rw
+        description: Level detect mode for WAKEUP2 event
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - WAKEUP3_L:
+        access: rw
+        description: Level detect mode for WAKEUP3 event
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - ATIMER_L:
+        access: rw
+        description: Level detect mode for alarm timer event
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - RTC_L:
+        access: rw
+        description: Level detect mode for RTC event
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - BOD_L:
+        access: rw
+        description: Level detect mode for BOD event
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - WWDT_L:
+        access: rw
+        description: Level detect mode for WWDT event
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - ETH_L:
+        access: rw
+        description: Level detect mode for Ethernet event
+        lsb: 8
+        reset_value: '0'
+        width: 1
+    - USB0_L:
+        access: rw
+        description: Level detect mode for USB0 event
+        lsb: 9
+        reset_value: '0'
+        width: 1
+    - USB1_L:
+        access: rw
+        description: Level detect mode for USB1 event
+        lsb: 10
+        reset_value: '0'
+        width: 1
+    - SDMMC_L:
+        access: rw
+        description: Level detect mode for SD/MMC event
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CAN_L:
+        access: rw
+        description: Level detect mode for C_CAN event
+        lsb: 12
+        reset_value: '0'
+        width: 1
+    - TIM2_L:
+        access: rw
+        description: Level detect mode for combined timer output 2 event
+        lsb: 13
+        reset_value: '0'
+        width: 1
+    - TIM6_L:
+        access: rw
+        description: Level detect mode for combined timer output 6 event
+        lsb: 14
+        reset_value: '0'
+        width: 1
+    - QEI_L:
+        access: rw
+        description: Level detect mode for QEI event
+        lsb: 15
+        reset_value: '0'
+        width: 1
+    - TIM14_L:
+        access: rw
+        description: Level detect mode for combined timer output 14 event
+        lsb: 16
+        reset_value: '0'
+        width: 1
+    - RESET_L:
+        access: rw
+        description: Level detect mode for Reset
+        lsb: 19
+        reset_value: '0'
+        width: 1
+- EVENTROUTER_EDGE:
+    fields: !!omap
+    - WAKEUP0_E:
+        access: rw
+        description: Edge/Level detect mode for WAKEUP0 event
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - WAKEUP1_E:
+        access: rw
+        description: Edge/Level detect mode for WAKEUP1 event
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP2_E:
+        access: rw
+        description: Edge/Level detect mode for WAKEUP2 event
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - WAKEUP3_E:
+        access: rw
+        description: Edge/Level detect mode for WAKEUP3 event
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - ATIMER_E:
+        access: rw
+        description: Edge/Level detect mode for alarm timer event
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - RTC_E:
+        access: rw
+        description: Edge/Level detect mode for RTC event
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - BOD_E:
+        access: rw
+        description: Edge/Level detect mode for BOD event
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - WWDT_E:
+        access: rw
+        description: Edge/Level detect mode for WWDT event
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - ETH_E:
+        access: rw
+        description: Edge/Level detect mode for Ethernet event
+        lsb: 8
+        reset_value: '0'
+        width: 1
+    - USB0_E:
+        access: rw
+        description: Edge/Level detect mode for USB0 event
+        lsb: 9
+        reset_value: '0'
+        width: 1
+    - USB1_E:
+        access: rw
+        description: Edge/Level detect mode for USB1 event
+        lsb: 10
+        reset_value: '0'
+        width: 1
+    - SDMMC_E:
+        access: rw
+        description: Edge/Level detect mode for SD/MMC event
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CAN_E:
+        access: rw
+        description: Edge/Level detect mode for C_CAN event
+        lsb: 12
+        reset_value: '0'
+        width: 1
+    - TIM2_E:
+        access: rw
+        description: Edge/Level detect mode for combined timer output 2 event
+        lsb: 13
+        reset_value: '0'
+        width: 1
+    - TIM6_E:
+        access: rw
+        description: Edge/Level detect mode for combined timer output 6 event
+        lsb: 14
+        reset_value: '0'
+        width: 1
+    - QEI_E:
+        access: rw
+        description: Edge/Level detect mode for QEI event
+        lsb: 15
+        reset_value: '0'
+        width: 1
+    - TIM14_E:
+        access: rw
+        description: Edge/Level detect mode for combined timer output 14 event
+        lsb: 16
+        reset_value: '0'
+        width: 1
+    - RESET_E:
+        access: rw
+        description: Edge/Level detect mode for Reset
+        lsb: 19
+        reset_value: '0'
+        width: 1
+- EVENTROUTER_CLR_EN:
+    fields: !!omap
+    - WAKEUP0_CLREN:
+        access: w
+        description: Writing a 1 to this bit clears the event enable bit 0 in the
+          ENABLE register
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - WAKEUP1_CLREN:
+        access: w
+        description: Writing a 1 to this bit clears the event enable bit 1 in the
+          ENABLE register
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP2_CLREN:
+        access: w
+        description: Writing a 1 to this bit clears the event enable bit 2 in the
+          ENABLE register
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - WAKEUP3_CLREN:
+        access: w
+        description: Writing a 1 to this bit clears the event enable bit 3 in the
+          ENABLE register
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - ATIMER_CLREN:
+        access: w
+        description: Writing a 1 to this bit clears the event enable bit 4 in the
+          ENABLE register
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - RTC_CLREN:
+        access: w
+        description: Writing a 1 to this bit clears the event enable bit 5 in the
+          ENABLE register
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - BOD_CLREN:
+        access: w
+        description: Writing a 1 to this bit clears the event enable bit 6 in the
+          ENABLE register
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - WWDT_CLREN:
+        access: w
+        description: Writing a 1 to this bit clears the event enable bit 7 in the
+          ENABLE register
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - ETH_CLREN:
+        access: w
+        description: Writing a 1 to this bit clears the event enable bit 8 in the
+          ENABLE register
+        lsb: 8
+        reset_value: '0'
+        width: 1
+    - USB0_CLREN:
+        access: w
+        description: Writing a 1 to this bit clears the event enable bit 9 in the
+          ENABLE register
+        lsb: 9
+        reset_value: '0'
+        width: 1
+    - USB1_CLREN:
+        access: w
+        description: Writing a 1 to this bit clears the event enable bit 10 in the
+          ENABLE register
+        lsb: 10
+        reset_value: '0'
+        width: 1
+    - SDMCC_CLREN:
+        access: w
+        description: Writing a 1 to this bit clears the event enable bit 11 in the
+          ENABLE register
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CAN_CLREN:
+        access: w
+        description: Writing a 1 to this bit clears the event enable bit 12 in the
+          ENABLE register
+        lsb: 12
+        reset_value: '0'
+        width: 1
+    - TIM2_CLREN:
+        access: w
+        description: Writing a 1 to this bit clears the event enable bit 13 in the
+          ENABLE register
+        lsb: 13
+        reset_value: '0'
+        width: 1
+    - TIM6_CLREN:
+        access: w
+        description: Writing a 1 to this bit clears the event enable bit 14 in the
+          ENABLE register
+        lsb: 14
+        reset_value: '0'
+        width: 1
+    - QEI_CLREN:
+        access: w
+        description: Writing a 1 to this bit clears the event enable bit 15 in the
+          ENABLE register
+        lsb: 15
+        reset_value: '0'
+        width: 1
+    - TIM14_CLREN:
+        access: w
+        description: Writing a 1 to this bit clears the event enable bit 16 in the
+          ENABLE register
+        lsb: 16
+        reset_value: '0'
+        width: 1
+    - RESET_CLREN:
+        access: w
+        description: Writing a 1 to this bit clears the event enable bit 19 in the
+          ENABLE register
+        lsb: 19
+        reset_value: '0'
+        width: 1
+- EVENTROUTER_SET_EN:
+    fields: !!omap
+    - WAKEUP0_SETEN:
+        access: w
+        description: Writing a 1 to this bit sets the event enable bit 0 in the ENABLE
+          register
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - WAKEUP1_SETEN:
+        access: w
+        description: Writing a 1 to this bit sets the event enable bit 1 in the ENABLE
+          register
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP2_SETEN:
+        access: w
+        description: Writing a 1 to this bit sets the event enable bit 2 in the ENABLE
+          register
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - WAKEUP3_SETEN:
+        access: w
+        description: Writing a 1 to this bit sets the event enable bit 3 in the ENABLE
+          register
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - ATIMER_SETEN:
+        access: w
+        description: Writing a 1 to this bit sets the event enable bit 4 in the ENABLE
+          register
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - RTC_SETEN:
+        access: w
+        description: Writing a 1 to this bit sets the event enable bit 5 in the ENABLE
+          register
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - BOD_SETEN:
+        access: w
+        description: Writing a 1 to this bit sets the event enable bit 6 in the ENABLE
+          register
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - WWDT_SETEN:
+        access: w
+        description: Writing a 1 to this bit sets the event enable bit 7 in the ENABLE
+          register
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - ETH_SETEN:
+        access: w
+        description: Writing a 1 to this bit sets the event enable bit 8 in the ENABLE
+          register
+        lsb: 8
+        reset_value: '0'
+        width: 1
+    - USB0_SETEN:
+        access: w
+        description: Writing a 1 to this bit sets the event enable bit 9 in the ENABLE
+          register
+        lsb: 9
+        reset_value: '0'
+        width: 1
+    - USB1_SETEN:
+        access: w
+        description: Writing a 1 to this bit sets the event enable bit 10 in the ENABLE
+          register
+        lsb: 10
+        reset_value: '0'
+        width: 1
+    - SDMCC_SETEN:
+        access: w
+        description: Writing a 1 to this bit sets the event enable bit 11 in the ENABLE
+          register
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CAN_SETEN:
+        access: w
+        description: Writing a 1 to this bit sets the event enable bit 12 in the ENABLE
+          register
+        lsb: 12
+        reset_value: '0'
+        width: 1
+    - TIM2_SETEN:
+        access: w
+        description: Writing a 1 to this bit sets the event enable bit 13 in the ENABLE
+          register
+        lsb: 13
+        reset_value: '0'
+        width: 1
+    - TIM6_SETEN:
+        access: w
+        description: Writing a 1 to this bit sets the event enable bit 14 in the ENABLE
+          register
+        lsb: 14
+        reset_value: '0'
+        width: 1
+    - QEI_SETEN:
+        access: w
+        description: Writing a 1 to this bit sets the event enable bit 15 in the ENABLE
+          register
+        lsb: 15
+        reset_value: '0'
+        width: 1
+    - TIM14_SETEN:
+        access: w
+        description: Writing a 1 to this bit sets the event enable bit 16 in the ENABLE
+          register
+        lsb: 16
+        reset_value: '0'
+        width: 1
+    - RESET_SETEN:
+        access: w
+        description: Writing a 1 to this bit sets the event enable bit 19 in the ENABLE
+          register
+        lsb: 19
+        reset_value: '0'
+        width: 1
+- EVENTROUTER_STATUS:
+    fields: !!omap
+    - WAKEUP0_ST:
+        access: r
+        description: A 1 in this bit shows that the WAKEUP0 event has been raised
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - WAKEUP1_ST:
+        access: r
+        description: A 1 in this bit shows that the WAKEUP1 event has been raised
+        lsb: 1
+        reset_value: '1'
+        width: 1
+    - WAKEUP2_ST:
+        access: r
+        description: A 1 in this bit shows that the WAKEUP2 event has been raised
+        lsb: 2
+        reset_value: '1'
+        width: 1
+    - WAKEUP3_ST:
+        access: r
+        description: A 1 in this bit shows that the WAKEUP3 event has been raised
+        lsb: 3
+        reset_value: '1'
+        width: 1
+    - ATIMER_ST:
+        access: r
+        description: A 1 in this bit shows that the ATIMER event has been raised
+        lsb: 4
+        reset_value: '1'
+        width: 1
+    - RTC_ST:
+        access: r
+        description: A 1 in this bit shows that the RTC event has been raised
+        lsb: 5
+        reset_value: '1'
+        width: 1
+    - BOD_ST:
+        access: r
+        description: A 1 in this bit shows that the BOD event has been raised
+        lsb: 6
+        reset_value: '1'
+        width: 1
+    - WWDT_ST:
+        access: r
+        description: A 1 in this bit shows that the WWDT event has been raised
+        lsb: 7
+        reset_value: '1'
+        width: 1
+    - ETH_ST:
+        access: r
+        description: A 1 in this bit shows that the ETH event has been raised
+        lsb: 8
+        reset_value: '1'
+        width: 1
+    - USB0_ST:
+        access: r
+        description: A 1 in this bit shows that the USB0 event has been raised
+        lsb: 9
+        reset_value: '1'
+        width: 1
+    - USB1_ST:
+        access: r
+        description: A 1 in this bit shows that the USB1 event has been raised
+        lsb: 10
+        reset_value: '1'
+        width: 1
+    - SDMMC_ST:
+        access: r
+        description: A 1 in this bit shows that the SDMMC event has been raised
+        lsb: 11
+        reset_value: '1'
+        width: 1
+    - CAN_ST:
+        access: r
+        description: A 1 in this bit shows that the CAN event has been raised
+        lsb: 12
+        reset_value: '1'
+        width: 1
+    - TIM2_ST:
+        access: r
+        description: A 1 in this bit shows that the combined timer 2 output event
+          has been raised
+        lsb: 13
+        reset_value: '1'
+        width: 1
+    - TIM6_ST:
+        access: r
+        description: A 1 in this bit shows that the combined timer 6 output event
+          has been raised
+        lsb: 14
+        reset_value: '1'
+        width: 1
+    - QEI_ST:
+        access: r
+        description: A 1 in this bit shows that the QEI event has been raised
+        lsb: 15
+        reset_value: '1'
+        width: 1
+    - TIM14_ST:
+        access: r
+        description: A 1 in this bit shows that the combined timer 14 output event
+          has been raised
+        lsb: 16
+        reset_value: '1'
+        width: 1
+    - RESET_ST:
+        access: r
+        description: A 1 in this bit shows that the reset event has been raised
+        lsb: 19
+        reset_value: '1'
+        width: 1
+- EVENTROUTER_ENABLE:
+    fields: !!omap
+    - WAKEUP0_EN:
+        access: r
+        description: A 1 in this bit shows that the WAKEUP0 event has been enabled
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - WAKEUP1_EN:
+        access: r
+        description: A 1 in this bit shows that the WAKEUP1 event has been enabled
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP2_EN:
+        access: r
+        description: A 1 in this bit shows that the WAKEUP2 event has been enabled
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - WAKEUP3_EN:
+        access: r
+        description: A 1 in this bit shows that the WAKEUP3 event has been enabled
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - ATIMER_EN:
+        access: r
+        description: A 1 in this bit shows that the ATIMER event has been enabled
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - RTC_EN:
+        access: r
+        description: A 1 in this bit shows that the RTC event has been enabled
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - BOD_EN:
+        access: r
+        description: A 1 in this bit shows that the BOD event has been enabled
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - WWDT_EN:
+        access: r
+        description: A 1 in this bit shows that the WWDT event has been enabled
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - ETH_EN:
+        access: r
+        description: A 1 in this bit shows that the ETH event has been enabled
+        lsb: 8
+        reset_value: '0'
+        width: 1
+    - USB0_EN:
+        access: r
+        description: A 1 in this bit shows that the USB0 event has been enabled
+        lsb: 9
+        reset_value: '0'
+        width: 1
+    - USB1_EN:
+        access: r
+        description: A 1 in this bit shows that the USB1 event has been enabled
+        lsb: 10
+        reset_value: '0'
+        width: 1
+    - SDMMC_EN:
+        access: r
+        description: A 1 in this bit shows that the SDMMC event has been enabled
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CAN_EN:
+        access: r
+        description: A 1 in this bit shows that the CAN event has been enabled
+        lsb: 12
+        reset_value: '0'
+        width: 1
+    - TIM2_EN:
+        access: r
+        description: A 1 in this bit shows that the combined timer 2 output event
+          has been enabled
+        lsb: 13
+        reset_value: '0'
+        width: 1
+    - TIM6_EN:
+        access: r
+        description: A 1 in this bit shows that the combined timer 6 output event
+          has been enabled
+        lsb: 14
+        reset_value: '0'
+        width: 1
+    - QEI_EN:
+        access: r
+        description: A 1 in this bit shows that the QEI event has been enabled
+        lsb: 15
+        reset_value: '0'
+        width: 1
+    - TIM14_EN:
+        access: r
+        description: A 1 in this bit shows that the combined timer 14 output event
+          has been enabled
+        lsb: 16
+        reset_value: '0'
+        width: 1
+    - RESET_EN:
+        access: r
+        description: A 1 in this bit shows that the reset event has been enabled
+        lsb: 19
+        reset_value: '0'
+        width: 1
+- EVENTROUTER_CLR_STAT:
+    fields: !!omap
+    - WAKEUP0_CLRST:
+        access: w
+        description: Writing a 1 to this bit clears the STATUS event bit 0 in the
+          STATUS register
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - WAKEUP1_CLRST:
+        access: w
+        description: Writing a 1 to this bit clears the STATUS event bit 1 in the
+          STATUS register
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP2_CLRST:
+        access: w
+        description: Writing a 1 to this bit clears the STATUS event bit 2 in the
+          STATUS register
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - WAKEUP3_CLRST:
+        access: w
+        description: Writing a 1 to this bit clears the STATUS event bit 3 in the
+          STATUS register
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - ATIMER_CLRST:
+        access: w
+        description: Writing a 1 to this bit clears the STATUS event bit 4 in the
+          STATUS register
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - RTC_CLRST:
+        access: w
+        description: Writing a 1 to this bit clears the STATUS event bit 5 in the
+          STATUS register
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - BOD_CLRST:
+        access: w
+        description: Writing a 1 to this bit clears the STATUS event bit 6 in the
+          STATUS register
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - WWDT_CLRST:
+        access: w
+        description: Writing a 1 to this bit clears the STATUS event bit 7 in the
+          STATUS register
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - ETH_CLRST:
+        access: w
+        description: Writing a 1 to this bit clears the STATUS event bit 8 in the
+          STATUS register
+        lsb: 8
+        reset_value: '0'
+        width: 1
+    - USB0_CLRST:
+        access: w
+        description: Writing a 1 to this bit clears the STATUS event bit 9 in the
+          STATUS register
+        lsb: 9
+        reset_value: '0'
+        width: 1
+    - USB1_CLRST:
+        access: w
+        description: Writing a 1 to this bit clears the STATUS event bit 10 in the
+          STATUS register
+        lsb: 10
+        reset_value: '0'
+        width: 1
+    - SDMCC_CLRST:
+        access: w
+        description: Writing a 1 to this bit clears the STATUS event bit 11 in the
+          STATUS register
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CAN_CLRST:
+        access: w
+        description: Writing a 1 to this bit clears the STATUS event bit 12 in the
+          STATUS register
+        lsb: 12
+        reset_value: '0'
+        width: 1
+    - TIM2_CLRST:
+        access: w
+        description: Writing a 1 to this bit clears the STATUS event bit 13 in the
+          STATUS register
+        lsb: 13
+        reset_value: '0'
+        width: 1
+    - TIM6_CLRST:
+        access: w
+        description: Writing a 1 to this bit clears the STATUS event bit 14 in the
+          STATUS register
+        lsb: 14
+        reset_value: '0'
+        width: 1
+    - QEI_CLRST:
+        access: w
+        description: Writing a 1 to this bit clears the STATUS event bit 15 in the
+          STATUS register
+        lsb: 15
+        reset_value: '0'
+        width: 1
+    - TIM14_CLRST:
+        access: w
+        description: Writing a 1 to this bit clears the STATUS event bit 16 in the
+          STATUS register
+        lsb: 16
+        reset_value: '0'
+        width: 1
+    - RESET_CLRST:
+        access: w
+        description: Writing a 1 to this bit clears the STATUS event bit 19 in the
+          STATUS register
+        lsb: 19
+        reset_value: '0'
+        width: 1
+- EVENTROUTER_SET_STAT:
+    fields: !!omap
+    - WAKEUP0_SETST:
+        access: w
+        description: Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS
+          register
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - WAKEUP1_SETST:
+        access: w
+        description: Writing a 1 to this bit sets the STATUS event bit 1 in the STATUS
+          register
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - WAKEUP2_SETST:
+        access: w
+        description: Writing a 1 to this bit sets the STATUS event bit 2 in the STATUS
+          register
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - WAKEUP3_SETST:
+        access: w
+        description: Writing a 1 to this bit sets the STATUS event bit 3 in the STATUS
+          register
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - ATIMER_SETST:
+        access: w
+        description: Writing a 1 to this bit sets the STATUS event bit 4 in the STATUS
+          register
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - RTC_SETST:
+        access: w
+        description: Writing a 1 to this bit sets the STATUS event bit 5 in the STATUS
+          register
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - BOD_SETST:
+        access: w
+        description: Writing a 1 to this bit sets the STATUS event bit 6 in the STATUS
+          register
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - WWDT_SETST:
+        access: w
+        description: Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS
+          register
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - ETH_SETST:
+        access: w
+        description: Writing a 1 to this bit sets the STATUS event bit 8 in the STATUS
+          register
+        lsb: 8
+        reset_value: '0'
+        width: 1
+    - USB0_SETST:
+        access: w
+        description: Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS
+          register
+        lsb: 9
+        reset_value: '0'
+        width: 1
+    - USB1_SETST:
+        access: w
+        description: Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS
+          register
+        lsb: 10
+        reset_value: '0'
+        width: 1
+    - SDMCC_SETST:
+        access: w
+        description: Writing a 1 to this bit sets the STATUS event bit 11 in the STATUS
+          register
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CAN_SETST:
+        access: w
+        description: Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS
+          register
+        lsb: 12
+        reset_value: '0'
+        width: 1
+    - TIM2_SETST:
+        access: w
+        description: Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS
+          register
+        lsb: 13
+        reset_value: '0'
+        width: 1
+    - TIM6_SETST:
+        access: w
+        description: Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS
+          register
+        lsb: 14
+        reset_value: '0'
+        width: 1
+    - QEI_SETST:
+        access: w
+        description: Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS
+          register
+        lsb: 15
+        reset_value: '0'
+        width: 1
+    - TIM14_SETST:
+        access: w
+        description: Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS
+          register
+        lsb: 16
+        reset_value: '0'
+        width: 1
+    - RESET_SETST:
+        access: w
+        description: Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS
+          register
+        lsb: 19
+        reset_value: '0'
+        width: 1
diff --git a/libopencm3/scripts/data/lpc43xx/gen.py b/libopencm3/scripts/data/lpc43xx/gen.py
new file mode 100755
index 0000000..0a46e06
--- /dev/null
+++ b/libopencm3/scripts/data/lpc43xx/gen.py
@@ -0,0 +1,29 @@
+#!/usr/bin/env python
+
+import sys
+import yaml
+import yaml_odict
+from collections import OrderedDict
+
+from pprint import pprint
+
+registers = yaml.load(open(sys.argv[1], 'r'))
+
+for register_name, register in registers.iteritems():
+    print('/* --- %s values %s */' % (register_name, '-' * (50 - len(register_name))))
+    print
+    fields = register['fields']
+    #for field_name, field in sorted(fields.items(), lambda x, y: cmp(x[1]['lsb'], y[1]['lsb'])):
+    for field_name, field in fields.items():
+        mask_bits = (1 << field['width']) - 1
+        print('/* %s: %s */' % (field_name, field['description']))
+        print('#define %s_%s_SHIFT (%d)' % (
+            register_name, field_name, field['lsb'],
+        ))
+        print('#define %s_%s_MASK (0x%x << %s_%s_SHIFT)' % (
+            register_name, field_name, mask_bits, register_name, field_name,
+        ))
+        print('#define %s_%s(x) ((x) << %s_%s_SHIFT)' % (
+            register_name, field_name, register_name, field_name,
+        ))
+        print
diff --git a/libopencm3/scripts/data/lpc43xx/gima.yaml b/libopencm3/scripts/data/lpc43xx/gima.yaml
new file mode 100644
index 0000000..d34086d
--- /dev/null
+++ b/libopencm3/scripts/data/lpc43xx/gima.yaml
@@ -0,0 +1,961 @@
+!!omap
+- GIMA_CAP0_0_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CAP0_1_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CAP0_2_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CAP0_3_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CAP1_0_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CAP1_1_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CAP1_2_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CAP1_3_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CAP2_0_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CAP2_1_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CAP2_2_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CAP2_3_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CAP3_0_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CAP3_1_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CAP3_2_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CAP3_3_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CTIN_0_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CTIN_1_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CTIN_2_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CTIN_3_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CTIN_4_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CTIN_5_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CTIN_6_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_CTIN_7_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_VADC_TRIGGER_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_EVENTROUTER_13_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_EVENTROUTER_14_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_EVENTROUTER_16_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_ADCSTART0_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
+- GIMA_ADCSTART1_IN:
+    fields: !!omap
+    - INV:
+        access: rw
+        description: Invert input
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - EDGE:
+        access: rw
+        description: Enable rising edge detection
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SYNCH:
+        access: rw
+        description: Enable synchronization
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PULSE:
+        access: rw
+        description: Enable single pulse generation
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SELECT:
+        access: rw
+        description: Select input
+        lsb: 4
+        reset_value: '0'
+        width: 4
diff --git a/libopencm3/scripts/data/lpc43xx/gpdma.yaml b/libopencm3/scripts/data/lpc43xx/gpdma.yaml
new file mode 100644
index 0000000..b53ea85
--- /dev/null
+++ b/libopencm3/scripts/data/lpc43xx/gpdma.yaml
@@ -0,0 +1,1498 @@
+!!omap
+- GPDMA_INTSTAT:
+    fields: !!omap
+    - INTSTAT:
+        access: r
+        description: Status of DMA channel interrupts after masking
+        lsb: 0
+        reset_value: '0x00'
+        width: 8
+- GPDMA_INTTCSTAT:
+    fields: !!omap
+    - INTTCSTAT:
+        access: r
+        description: Terminal count interrupt request status for DMA channels
+        lsb: 0
+        reset_value: '0x00'
+        width: 8
+- GPDMA_INTTCCLEAR:
+    fields: !!omap
+    - INTTCCLEAR:
+        access: w
+        description: Allows clearing the Terminal count interrupt request (IntTCStat)
+          for DMA channels
+        lsb: 0
+        reset_value: '0x00'
+        width: 8
+- GPDMA_INTERRSTAT:
+    fields: !!omap
+    - INTERRSTAT:
+        access: r
+        description: Interrupt error status for DMA channels
+        lsb: 0
+        reset_value: '0x00'
+        width: 8
+- GPDMA_INTERRCLR:
+    fields: !!omap
+    - INTERRCLR:
+        access: w
+        description: Writing a 1 clears the error interrupt request (IntErrStat) for
+          DMA channels
+        lsb: 0
+        reset_value: '0x00'
+        width: 8
+- GPDMA_RAWINTTCSTAT:
+    fields: !!omap
+    - RAWINTTCSTAT:
+        access: r
+        description: Status of the terminal count interrupt for DMA channels prior
+          to masking
+        lsb: 0
+        reset_value: '0x00'
+        width: 8
+- GPDMA_RAWINTERRSTAT:
+    fields: !!omap
+    - RAWINTERRSTAT:
+        access: r
+        description: Status of the error interrupt for DMA channels prior to masking
+        lsb: 0
+        reset_value: '0x00'
+        width: 8
+- GPDMA_ENBLDCHNS:
+    fields: !!omap
+    - ENABLEDCHANNELS:
+        access: r
+        description: Enable status for DMA channels
+        lsb: 0
+        reset_value: '0x00'
+        width: 8
+- GPDMA_SOFTBREQ:
+    fields: !!omap
+    - SOFTBREQ:
+        access: rw
+        description: Software burst request flags for each of 16 possible sources
+        lsb: 0
+        reset_value: '0x00'
+        width: 16
+- GPDMA_SOFTSREQ:
+    fields: !!omap
+    - SOFTSREQ:
+        access: rw
+        description: Software single transfer request flags for each of 16 possible
+          sources
+        lsb: 0
+        reset_value: '0x00'
+        width: 16
+- GPDMA_SOFTLBREQ:
+    fields: !!omap
+    - SOFTLBREQ:
+        access: rw
+        description: Software last burst request flags for each of 16 possible sources
+        lsb: 0
+        reset_value: '0x00'
+        width: 16
+- GPDMA_SOFTLSREQ:
+    fields: !!omap
+    - SOFTLSREQ:
+        access: rw
+        description: Software last single transfer request flags for each of 16 possible
+          sources
+        lsb: 0
+        reset_value: '0x00'
+        width: 16
+- GPDMA_CONFIG:
+    fields: !!omap
+    - E:
+        access: rw
+        description: DMA Controller enable
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - M0:
+        access: rw
+        description: AHB Master 0 endianness configuration
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - M1:
+        access: rw
+        description: AHB Master 1 endianness configuration
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- GPDMA_SYNC:
+    fields: !!omap
+    - DMACSYNC:
+        access: rw
+        description: Controls the synchronization logic for DMA request signals
+        lsb: 0
+        reset_value: '0x00'
+        width: 16
+- GPDMA_C0SRCADDR:
+    fields: !!omap
+    - SRCADDR:
+        access: rw
+        description: DMA source address
+        lsb: 0
+        reset_value: '0x00000000'
+        width: 32
+- GPDMA_C1SRCADDR:
+    fields: !!omap
+    - SRCADDR:
+        access: rw
+        description: DMA source address
+        lsb: 0
+        reset_value: '0x00000000'
+        width: 32
+- GPDMA_C2SRCADDR:
+    fields: !!omap
+    - SRCADDR:
+        access: rw
+        description: DMA source address
+        lsb: 0
+        reset_value: '0x00000000'
+        width: 32
+- GPDMA_C3SRCADDR:
+    fields: !!omap
+    - SRCADDR:
+        access: rw
+        description: DMA source address
+        lsb: 0
+        reset_value: '0x00000000'
+        width: 32
+- GPDMA_C4SRCADDR:
+    fields: !!omap
+    - SRCADDR:
+        access: rw
+        description: DMA source address
+        lsb: 0
+        reset_value: '0x00000000'
+        width: 32
+- GPDMA_C5SRCADDR:
+    fields: !!omap
+    - SRCADDR:
+        access: rw
+        description: DMA source address
+        lsb: 0
+        reset_value: '0x00000000'
+        width: 32
+- GPDMA_C6SRCADDR:
+    fields: !!omap
+    - SRCADDR:
+        access: rw
+        description: DMA source address
+        lsb: 0
+        reset_value: '0x00000000'
+        width: 32
+- GPDMA_C7SRCADDR:
+    fields: !!omap
+    - SRCADDR:
+        access: rw
+        description: DMA source address
+        lsb: 0
+        reset_value: '0x00000000'
+        width: 32
+- GPDMA_C0DESTADDR:
+    fields: !!omap
+    - DESTADDR:
+        access: rw
+        description: DMA source address
+        lsb: 0
+        reset_value: '0x00000000'
+        width: 32
+- GPDMA_C1DESTADDR:
+    fields: !!omap
+    - DESTADDR:
+        access: rw
+        description: DMA source address
+        lsb: 0
+        reset_value: '0x00000000'
+        width: 32
+- GPDMA_C2DESTADDR:
+    fields: !!omap
+    - DESTADDR:
+        access: rw
+        description: DMA source address
+        lsb: 0
+        reset_value: '0x00000000'
+        width: 32
+- GPDMA_C3DESTADDR:
+    fields: !!omap
+    - DESTADDR:
+        access: rw
+        description: DMA source address
+        lsb: 0
+        reset_value: '0x00000000'
+        width: 32
+- GPDMA_C4DESTADDR:
+    fields: !!omap
+    - DESTADDR:
+        access: rw
+        description: DMA source address
+        lsb: 0
+        reset_value: '0x00000000'
+        width: 32
+- GPDMA_C5DESTADDR:
+    fields: !!omap
+    - DESTADDR:
+        access: rw
+        description: DMA source address
+        lsb: 0
+        reset_value: '0x00000000'
+        width: 32
+- GPDMA_C6DESTADDR:
+    fields: !!omap
+    - DESTADDR:
+        access: rw
+        description: DMA source address
+        lsb: 0
+        reset_value: '0x00000000'
+        width: 32
+- GPDMA_C7DESTADDR:
+    fields: !!omap
+    - DESTADDR:
+        access: rw
+        description: DMA source address
+        lsb: 0
+        reset_value: '0x00000000'
+        width: 32
+- GPDMA_C0LLI:
+    fields: !!omap
+    - LM:
+        access: rw
+        description: AHB master select for loading the next LLI
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - LLI:
+        access: rw
+        description: Linked list item
+        lsb: 2
+        reset_value: '0x00000000'
+        width: 30
+- GPDMA_C1LLI:
+    fields: !!omap
+    - LM:
+        access: rw
+        description: AHB master select for loading the next LLI
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - LLI:
+        access: rw
+        description: Linked list item
+        lsb: 2
+        reset_value: '0x00000000'
+        width: 30
+- GPDMA_C2LLI:
+    fields: !!omap
+    - LM:
+        access: rw
+        description: AHB master select for loading the next LLI
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - LLI:
+        access: rw
+        description: Linked list item
+        lsb: 2
+        reset_value: '0x00000000'
+        width: 30
+- GPDMA_C3LLI:
+    fields: !!omap
+    - LM:
+        access: rw
+        description: AHB master select for loading the next LLI
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - LLI:
+        access: rw
+        description: Linked list item
+        lsb: 2
+        reset_value: '0x00000000'
+        width: 30
+- GPDMA_C4LLI:
+    fields: !!omap
+    - LM:
+        access: rw
+        description: AHB master select for loading the next LLI
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - LLI:
+        access: rw
+        description: Linked list item
+        lsb: 2
+        reset_value: '0x00000000'
+        width: 30
+- GPDMA_C5LLI:
+    fields: !!omap
+    - LM:
+        access: rw
+        description: AHB master select for loading the next LLI
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - LLI:
+        access: rw
+        description: Linked list item
+        lsb: 2
+        reset_value: '0x00000000'
+        width: 30
+- GPDMA_C6LLI:
+    fields: !!omap
+    - LM:
+        access: rw
+        description: AHB master select for loading the next LLI
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - LLI:
+        access: rw
+        description: Linked list item
+        lsb: 2
+        reset_value: '0x00000000'
+        width: 30
+- GPDMA_C7LLI:
+    fields: !!omap
+    - LM:
+        access: rw
+        description: AHB master select for loading the next LLI
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - LLI:
+        access: rw
+        description: Linked list item
+        lsb: 2
+        reset_value: '0x00000000'
+        width: 30
+- GPDMA_C0CONTROL:
+    fields: !!omap
+    - TRANSFERSIZE:
+        access: rw
+        description: Transfer size in number of transfers
+        lsb: 0
+        reset_value: '0x00'
+        width: 12
+    - SBSIZE:
+        access: rw
+        description: Source burst size
+        lsb: 12
+        reset_value: '0x0'
+        width: 3
+    - DBSIZE:
+        access: rw
+        description: Destination burst size
+        lsb: 15
+        reset_value: '0x0'
+        width: 3
+    - SWIDTH:
+        access: rw
+        description: Source transfer width
+        lsb: 18
+        reset_value: '0x0'
+        width: 3
+    - DWIDTH:
+        access: rw
+        description: Destination transfer width
+        lsb: 21
+        reset_value: '0x0'
+        width: 3
+    - S:
+        access: rw
+        description: Source AHB master select
+        lsb: 24
+        reset_value: '0'
+        width: 1
+    - D:
+        access: rw
+        description: Destination AHB master select
+        lsb: 25
+        reset_value: '0'
+        width: 1
+    - SI:
+        access: rw
+        description: Source increment
+        lsb: 26
+        reset_value: '0'
+        width: 1
+    - DI:
+        access: rw
+        description: Destination increment
+        lsb: 27
+        reset_value: '0'
+        width: 1
+    - PROT1:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates that the access is in user mode or privileged mode
+        lsb: 28
+        reset_value: '0'
+        width: 1
+    - PROT2:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates to the peripheral that the access is bufferable or
+          not bufferable
+        lsb: 29
+        reset_value: '0'
+        width: 1
+    - PROT3:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates to the peripheral that the access is cacheable or not
+          cacheable
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - I:
+        access: rw
+        description: Terminal count interrupt enable bit
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- GPDMA_C1CONTROL:
+    fields: !!omap
+    - TRANSFERSIZE:
+        access: rw
+        description: Transfer size in number of transfers
+        lsb: 0
+        reset_value: '0x00'
+        width: 12
+    - SBSIZE:
+        access: rw
+        description: Source burst size
+        lsb: 12
+        reset_value: '0x0'
+        width: 3
+    - DBSIZE:
+        access: rw
+        description: Destination burst size
+        lsb: 15
+        reset_value: '0x0'
+        width: 3
+    - SWIDTH:
+        access: rw
+        description: Source transfer width
+        lsb: 18
+        reset_value: '0x0'
+        width: 3
+    - DWIDTH:
+        access: rw
+        description: Destination transfer width
+        lsb: 21
+        reset_value: '0x0'
+        width: 3
+    - S:
+        access: rw
+        description: Source AHB master select
+        lsb: 24
+        reset_value: '0'
+        width: 1
+    - D:
+        access: rw
+        description: Destination AHB master select
+        lsb: 25
+        reset_value: '0'
+        width: 1
+    - SI:
+        access: rw
+        description: Source increment
+        lsb: 26
+        reset_value: '0'
+        width: 1
+    - DI:
+        access: rw
+        description: Destination increment
+        lsb: 27
+        reset_value: '0'
+        width: 1
+    - PROT1:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates that the access is in user mode or privileged mode
+        lsb: 28
+        reset_value: '0'
+        width: 1
+    - PROT2:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates to the peripheral that the access is bufferable or
+          not bufferable
+        lsb: 29
+        reset_value: '0'
+        width: 1
+    - PROT3:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates to the peripheral that the access is cacheable or not
+          cacheable
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - I:
+        access: rw
+        description: Terminal count interrupt enable bit
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- GPDMA_C2CONTROL:
+    fields: !!omap
+    - TRANSFERSIZE:
+        access: rw
+        description: Transfer size in number of transfers
+        lsb: 0
+        reset_value: '0x00'
+        width: 12
+    - SBSIZE:
+        access: rw
+        description: Source burst size
+        lsb: 12
+        reset_value: '0x0'
+        width: 3
+    - DBSIZE:
+        access: rw
+        description: Destination burst size
+        lsb: 15
+        reset_value: '0x0'
+        width: 3
+    - SWIDTH:
+        access: rw
+        description: Source transfer width
+        lsb: 18
+        reset_value: '0x0'
+        width: 3
+    - DWIDTH:
+        access: rw
+        description: Destination transfer width
+        lsb: 21
+        reset_value: '0x0'
+        width: 3
+    - S:
+        access: rw
+        description: Source AHB master select
+        lsb: 24
+        reset_value: '0'
+        width: 1
+    - D:
+        access: rw
+        description: Destination AHB master select
+        lsb: 25
+        reset_value: '0'
+        width: 1
+    - SI:
+        access: rw
+        description: Source increment
+        lsb: 26
+        reset_value: '0'
+        width: 1
+    - DI:
+        access: rw
+        description: Destination increment
+        lsb: 27
+        reset_value: '0'
+        width: 1
+    - PROT1:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates that the access is in user mode or privileged mode
+        lsb: 28
+        reset_value: '0'
+        width: 1
+    - PROT2:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates to the peripheral that the access is bufferable or
+          not bufferable
+        lsb: 29
+        reset_value: '0'
+        width: 1
+    - PROT3:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates to the peripheral that the access is cacheable or not
+          cacheable
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - I:
+        access: rw
+        description: Terminal count interrupt enable bit
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- GPDMA_C3CONTROL:
+    fields: !!omap
+    - TRANSFERSIZE:
+        access: rw
+        description: Transfer size in number of transfers
+        lsb: 0
+        reset_value: '0x00'
+        width: 12
+    - SBSIZE:
+        access: rw
+        description: Source burst size
+        lsb: 12
+        reset_value: '0x0'
+        width: 3
+    - DBSIZE:
+        access: rw
+        description: Destination burst size
+        lsb: 15
+        reset_value: '0x0'
+        width: 3
+    - SWIDTH:
+        access: rw
+        description: Source transfer width
+        lsb: 18
+        reset_value: '0x0'
+        width: 3
+    - DWIDTH:
+        access: rw
+        description: Destination transfer width
+        lsb: 21
+        reset_value: '0x0'
+        width: 3
+    - S:
+        access: rw
+        description: Source AHB master select
+        lsb: 24
+        reset_value: '0'
+        width: 1
+    - D:
+        access: rw
+        description: Destination AHB master select
+        lsb: 25
+        reset_value: '0'
+        width: 1
+    - SI:
+        access: rw
+        description: Source increment
+        lsb: 26
+        reset_value: '0'
+        width: 1
+    - DI:
+        access: rw
+        description: Destination increment
+        lsb: 27
+        reset_value: '0'
+        width: 1
+    - PROT1:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates that the access is in user mode or privileged mode
+        lsb: 28
+        reset_value: '0'
+        width: 1
+    - PROT2:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates to the peripheral that the access is bufferable or
+          not bufferable
+        lsb: 29
+        reset_value: '0'
+        width: 1
+    - PROT3:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates to the peripheral that the access is cacheable or not
+          cacheable
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - I:
+        access: rw
+        description: Terminal count interrupt enable bit
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- GPDMA_C4CONTROL:
+    fields: !!omap
+    - TRANSFERSIZE:
+        access: rw
+        description: Transfer size in number of transfers
+        lsb: 0
+        reset_value: '0x00'
+        width: 12
+    - SBSIZE:
+        access: rw
+        description: Source burst size
+        lsb: 12
+        reset_value: '0x0'
+        width: 3
+    - DBSIZE:
+        access: rw
+        description: Destination burst size
+        lsb: 15
+        reset_value: '0x0'
+        width: 3
+    - SWIDTH:
+        access: rw
+        description: Source transfer width
+        lsb: 18
+        reset_value: '0x0'
+        width: 3
+    - DWIDTH:
+        access: rw
+        description: Destination transfer width
+        lsb: 21
+        reset_value: '0x0'
+        width: 3
+    - S:
+        access: rw
+        description: Source AHB master select
+        lsb: 24
+        reset_value: '0'
+        width: 1
+    - D:
+        access: rw
+        description: Destination AHB master select
+        lsb: 25
+        reset_value: '0'
+        width: 1
+    - SI:
+        access: rw
+        description: Source increment
+        lsb: 26
+        reset_value: '0'
+        width: 1
+    - DI:
+        access: rw
+        description: Destination increment
+        lsb: 27
+        reset_value: '0'
+        width: 1
+    - PROT1:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates that the access is in user mode or privileged mode
+        lsb: 28
+        reset_value: '0'
+        width: 1
+    - PROT2:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates to the peripheral that the access is bufferable or
+          not bufferable
+        lsb: 29
+        reset_value: '0'
+        width: 1
+    - PROT3:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates to the peripheral that the access is cacheable or not
+          cacheable
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - I:
+        access: rw
+        description: Terminal count interrupt enable bit
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- GPDMA_C5CONTROL:
+    fields: !!omap
+    - TRANSFERSIZE:
+        access: rw
+        description: Transfer size in number of transfers
+        lsb: 0
+        reset_value: '0x00'
+        width: 12
+    - SBSIZE:
+        access: rw
+        description: Source burst size
+        lsb: 12
+        reset_value: '0x0'
+        width: 3
+    - DBSIZE:
+        access: rw
+        description: Destination burst size
+        lsb: 15
+        reset_value: '0x0'
+        width: 3
+    - SWIDTH:
+        access: rw
+        description: Source transfer width
+        lsb: 18
+        reset_value: '0x0'
+        width: 3
+    - DWIDTH:
+        access: rw
+        description: Destination transfer width
+        lsb: 21
+        reset_value: '0x0'
+        width: 3
+    - S:
+        access: rw
+        description: Source AHB master select
+        lsb: 24
+        reset_value: '0'
+        width: 1
+    - D:
+        access: rw
+        description: Destination AHB master select
+        lsb: 25
+        reset_value: '0'
+        width: 1
+    - SI:
+        access: rw
+        description: Source increment
+        lsb: 26
+        reset_value: '0'
+        width: 1
+    - DI:
+        access: rw
+        description: Destination increment
+        lsb: 27
+        reset_value: '0'
+        width: 1
+    - PROT1:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates that the access is in user mode or privileged mode
+        lsb: 28
+        reset_value: '0'
+        width: 1
+    - PROT2:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates to the peripheral that the access is bufferable or
+          not bufferable
+        lsb: 29
+        reset_value: '0'
+        width: 1
+    - PROT3:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates to the peripheral that the access is cacheable or not
+          cacheable
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - I:
+        access: rw
+        description: Terminal count interrupt enable bit
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- GPDMA_C6CONTROL:
+    fields: !!omap
+    - TRANSFERSIZE:
+        access: rw
+        description: Transfer size in number of transfers
+        lsb: 0
+        reset_value: '0x00'
+        width: 12
+    - SBSIZE:
+        access: rw
+        description: Source burst size
+        lsb: 12
+        reset_value: '0x0'
+        width: 3
+    - DBSIZE:
+        access: rw
+        description: Destination burst size
+        lsb: 15
+        reset_value: '0x0'
+        width: 3
+    - SWIDTH:
+        access: rw
+        description: Source transfer width
+        lsb: 18
+        reset_value: '0x0'
+        width: 3
+    - DWIDTH:
+        access: rw
+        description: Destination transfer width
+        lsb: 21
+        reset_value: '0x0'
+        width: 3
+    - S:
+        access: rw
+        description: Source AHB master select
+        lsb: 24
+        reset_value: '0'
+        width: 1
+    - D:
+        access: rw
+        description: Destination AHB master select
+        lsb: 25
+        reset_value: '0'
+        width: 1
+    - SI:
+        access: rw
+        description: Source increment
+        lsb: 26
+        reset_value: '0'
+        width: 1
+    - DI:
+        access: rw
+        description: Destination increment
+        lsb: 27
+        reset_value: '0'
+        width: 1
+    - PROT1:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates that the access is in user mode or privileged mode
+        lsb: 28
+        reset_value: '0'
+        width: 1
+    - PROT2:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates to the peripheral that the access is bufferable or
+          not bufferable
+        lsb: 29
+        reset_value: '0'
+        width: 1
+    - PROT3:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates to the peripheral that the access is cacheable or not
+          cacheable
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - I:
+        access: rw
+        description: Terminal count interrupt enable bit
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- GPDMA_C7CONTROL:
+    fields: !!omap
+    - TRANSFERSIZE:
+        access: rw
+        description: Transfer size in number of transfers
+        lsb: 0
+        reset_value: '0x00'
+        width: 12
+    - SBSIZE:
+        access: rw
+        description: Source burst size
+        lsb: 12
+        reset_value: '0x0'
+        width: 3
+    - DBSIZE:
+        access: rw
+        description: Destination burst size
+        lsb: 15
+        reset_value: '0x0'
+        width: 3
+    - SWIDTH:
+        access: rw
+        description: Source transfer width
+        lsb: 18
+        reset_value: '0x0'
+        width: 3
+    - DWIDTH:
+        access: rw
+        description: Destination transfer width
+        lsb: 21
+        reset_value: '0x0'
+        width: 3
+    - S:
+        access: rw
+        description: Source AHB master select
+        lsb: 24
+        reset_value: '0'
+        width: 1
+    - D:
+        access: rw
+        description: Destination AHB master select
+        lsb: 25
+        reset_value: '0'
+        width: 1
+    - SI:
+        access: rw
+        description: Source increment
+        lsb: 26
+        reset_value: '0'
+        width: 1
+    - DI:
+        access: rw
+        description: Destination increment
+        lsb: 27
+        reset_value: '0'
+        width: 1
+    - PROT1:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates that the access is in user mode or privileged mode
+        lsb: 28
+        reset_value: '0'
+        width: 1
+    - PROT2:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates to the peripheral that the access is bufferable or
+          not bufferable
+        lsb: 29
+        reset_value: '0'
+        width: 1
+    - PROT3:
+        access: rw
+        description: This information is provided to the peripheral during a DMA bus
+          access and indicates to the peripheral that the access is cacheable or not
+          cacheable
+        lsb: 30
+        reset_value: '0'
+        width: 1
+    - I:
+        access: rw
+        description: Terminal count interrupt enable bit
+        lsb: 31
+        reset_value: '0'
+        width: 1
+- GPDMA_C0CONFIG:
+    fields: !!omap
+    - E:
+        access: rw
+        description: Channel enable
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - SRCPERIPHERAL:
+        access: rw
+        description: Source peripheral
+        lsb: 1
+        reset_value: ''
+        width: 5
+    - DESTPERIPHERAL:
+        access: rw
+        description: Destination peripheral
+        lsb: 6
+        reset_value: ''
+        width: 5
+    - FLOWCNTRL:
+        access: rw
+        description: Flow control and transfer type
+        lsb: 11
+        reset_value: ''
+        width: 3
+    - IE:
+        access: rw
+        description: Interrupt error mask
+        lsb: 14
+        reset_value: ''
+        width: 1
+    - ITC:
+        access: rw
+        description: Terminal count interrupt mask
+        lsb: 15
+        reset_value: ''
+        width: 1
+    - L:
+        access: rw
+        description: Lock
+        lsb: 16
+        reset_value: ''
+        width: 1
+    - A:
+        access: r
+        description: Active
+        lsb: 17
+        reset_value: ''
+        width: 1
+    - H:
+        access: rw
+        description: Halt
+        lsb: 18
+        reset_value: ''
+        width: 1
+- GPDMA_C1CONFIG:
+    fields: !!omap
+    - E:
+        access: rw
+        description: Channel enable
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - SRCPERIPHERAL:
+        access: rw
+        description: Source peripheral
+        lsb: 1
+        reset_value: ''
+        width: 5
+    - DESTPERIPHERAL:
+        access: rw
+        description: Destination peripheral
+        lsb: 6
+        reset_value: ''
+        width: 5
+    - FLOWCNTRL:
+        access: rw
+        description: Flow control and transfer type
+        lsb: 11
+        reset_value: ''
+        width: 3
+    - IE:
+        access: rw
+        description: Interrupt error mask
+        lsb: 14
+        reset_value: ''
+        width: 1
+    - ITC:
+        access: rw
+        description: Terminal count interrupt mask
+        lsb: 15
+        reset_value: ''
+        width: 1
+    - L:
+        access: rw
+        description: Lock
+        lsb: 16
+        reset_value: ''
+        width: 1
+    - A:
+        access: r
+        description: Active
+        lsb: 17
+        reset_value: ''
+        width: 1
+    - H:
+        access: rw
+        description: Halt
+        lsb: 18
+        reset_value: ''
+        width: 1
+- GPDMA_C2CONFIG:
+    fields: !!omap
+    - E:
+        access: rw
+        description: Channel enable
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - SRCPERIPHERAL:
+        access: rw
+        description: Source peripheral
+        lsb: 1
+        reset_value: ''
+        width: 5
+    - DESTPERIPHERAL:
+        access: rw
+        description: Destination peripheral
+        lsb: 6
+        reset_value: ''
+        width: 5
+    - FLOWCNTRL:
+        access: rw
+        description: Flow control and transfer type
+        lsb: 11
+        reset_value: ''
+        width: 3
+    - IE:
+        access: rw
+        description: Interrupt error mask
+        lsb: 14
+        reset_value: ''
+        width: 1
+    - ITC:
+        access: rw
+        description: Terminal count interrupt mask
+        lsb: 15
+        reset_value: ''
+        width: 1
+    - L:
+        access: rw
+        description: Lock
+        lsb: 16
+        reset_value: ''
+        width: 1
+    - A:
+        access: r
+        description: Active
+        lsb: 17
+        reset_value: ''
+        width: 1
+    - H:
+        access: rw
+        description: Halt
+        lsb: 18
+        reset_value: ''
+        width: 1
+- GPDMA_C3CONFIG:
+    fields: !!omap
+    - E:
+        access: rw
+        description: Channel enable
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - SRCPERIPHERAL:
+        access: rw
+        description: Source peripheral
+        lsb: 1
+        reset_value: ''
+        width: 5
+    - DESTPERIPHERAL:
+        access: rw
+        description: Destination peripheral
+        lsb: 6
+        reset_value: ''
+        width: 5
+    - FLOWCNTRL:
+        access: rw
+        description: Flow control and transfer type
+        lsb: 11
+        reset_value: ''
+        width: 3
+    - IE:
+        access: rw
+        description: Interrupt error mask
+        lsb: 14
+        reset_value: ''
+        width: 1
+    - ITC:
+        access: rw
+        description: Terminal count interrupt mask
+        lsb: 15
+        reset_value: ''
+        width: 1
+    - L:
+        access: rw
+        description: Lock
+        lsb: 16
+        reset_value: ''
+        width: 1
+    - A:
+        access: r
+        description: Active
+        lsb: 17
+        reset_value: ''
+        width: 1
+    - H:
+        access: rw
+        description: Halt
+        lsb: 18
+        reset_value: ''
+        width: 1
+- GPDMA_C4CONFIG:
+    fields: !!omap
+    - E:
+        access: rw
+        description: Channel enable
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - SRCPERIPHERAL:
+        access: rw
+        description: Source peripheral
+        lsb: 1
+        reset_value: ''
+        width: 5
+    - DESTPERIPHERAL:
+        access: rw
+        description: Destination peripheral
+        lsb: 6
+        reset_value: ''
+        width: 5
+    - FLOWCNTRL:
+        access: rw
+        description: Flow control and transfer type
+        lsb: 11
+        reset_value: ''
+        width: 3
+    - IE:
+        access: rw
+        description: Interrupt error mask
+        lsb: 14
+        reset_value: ''
+        width: 1
+    - ITC:
+        access: rw
+        description: Terminal count interrupt mask
+        lsb: 15
+        reset_value: ''
+        width: 1
+    - L:
+        access: rw
+        description: Lock
+        lsb: 16
+        reset_value: ''
+        width: 1
+    - A:
+        access: r
+        description: Active
+        lsb: 17
+        reset_value: ''
+        width: 1
+    - H:
+        access: rw
+        description: Halt
+        lsb: 18
+        reset_value: ''
+        width: 1
+- GPDMA_C5CONFIG:
+    fields: !!omap
+    - E:
+        access: rw
+        description: Channel enable
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - SRCPERIPHERAL:
+        access: rw
+        description: Source peripheral
+        lsb: 1
+        reset_value: ''
+        width: 5
+    - DESTPERIPHERAL:
+        access: rw
+        description: Destination peripheral
+        lsb: 6
+        reset_value: ''
+        width: 5
+    - FLOWCNTRL:
+        access: rw
+        description: Flow control and transfer type
+        lsb: 11
+        reset_value: ''
+        width: 3
+    - IE:
+        access: rw
+        description: Interrupt error mask
+        lsb: 14
+        reset_value: ''
+        width: 1
+    - ITC:
+        access: rw
+        description: Terminal count interrupt mask
+        lsb: 15
+        reset_value: ''
+        width: 1
+    - L:
+        access: rw
+        description: Lock
+        lsb: 16
+        reset_value: ''
+        width: 1
+    - A:
+        access: r
+        description: Active
+        lsb: 17
+        reset_value: ''
+        width: 1
+    - H:
+        access: rw
+        description: Halt
+        lsb: 18
+        reset_value: ''
+        width: 1
+- GPDMA_C6CONFIG:
+    fields: !!omap
+    - E:
+        access: rw
+        description: Channel enable
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - SRCPERIPHERAL:
+        access: rw
+        description: Source peripheral
+        lsb: 1
+        reset_value: ''
+        width: 5
+    - DESTPERIPHERAL:
+        access: rw
+        description: Destination peripheral
+        lsb: 6
+        reset_value: ''
+        width: 5
+    - FLOWCNTRL:
+        access: rw
+        description: Flow control and transfer type
+        lsb: 11
+        reset_value: ''
+        width: 3
+    - IE:
+        access: rw
+        description: Interrupt error mask
+        lsb: 14
+        reset_value: ''
+        width: 1
+    - ITC:
+        access: rw
+        description: Terminal count interrupt mask
+        lsb: 15
+        reset_value: ''
+        width: 1
+    - L:
+        access: rw
+        description: Lock
+        lsb: 16
+        reset_value: ''
+        width: 1
+    - A:
+        access: r
+        description: Active
+        lsb: 17
+        reset_value: ''
+        width: 1
+    - H:
+        access: rw
+        description: Halt
+        lsb: 18
+        reset_value: ''
+        width: 1
+- GPDMA_C7CONFIG:
+    fields: !!omap
+    - E:
+        access: rw
+        description: Channel enable
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - SRCPERIPHERAL:
+        access: rw
+        description: Source peripheral
+        lsb: 1
+        reset_value: ''
+        width: 5
+    - DESTPERIPHERAL:
+        access: rw
+        description: Destination peripheral
+        lsb: 6
+        reset_value: ''
+        width: 5
+    - FLOWCNTRL:
+        access: rw
+        description: Flow control and transfer type
+        lsb: 11
+        reset_value: ''
+        width: 3
+    - IE:
+        access: rw
+        description: Interrupt error mask
+        lsb: 14
+        reset_value: ''
+        width: 1
+    - ITC:
+        access: rw
+        description: Terminal count interrupt mask
+        lsb: 15
+        reset_value: ''
+        width: 1
+    - L:
+        access: rw
+        description: Lock
+        lsb: 16
+        reset_value: ''
+        width: 1
+    - A:
+        access: r
+        description: Active
+        lsb: 17
+        reset_value: ''
+        width: 1
+    - H:
+        access: rw
+        description: Halt
+        lsb: 18
+        reset_value: ''
+        width: 1
diff --git a/libopencm3/scripts/data/lpc43xx/gpio.yaml b/libopencm3/scripts/data/lpc43xx/gpio.yaml
new file mode 100644
index 0000000..b76e37f
--- /dev/null
+++ b/libopencm3/scripts/data/lpc43xx/gpio.yaml
@@ -0,0 +1,4926 @@
+!!omap
+- GPIO_PIN_INTERRUPT_ISEL:
+    fields: !!omap
+    - PMODE:
+        access: rw
+        description: Selects the interrupt mode for each pin interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 8
+- GPIO_PIN_INTERRUPT_IENR:
+    fields: !!omap
+    - ENRL:
+        access: rw
+        description: Enables the rising edge or level interrupt for each pin interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 8
+- GPIO_PIN_INTERRUPT_SIENR:
+    fields: !!omap
+    - SETENRL:
+        access: w
+        description: Ones written to this address set bits in the IENR, thus enabling
+          interrupts
+        lsb: 0
+        reset_value: ''
+        width: 8
+- GPIO_PIN_INTERRUPT_CIENR:
+    fields: !!omap
+    - CENRL:
+        access: w
+        description: Ones written to this address clear bits in the IENR, thus disabling
+          the interrupts
+        lsb: 0
+        reset_value: ''
+        width: 8
+- GPIO_PIN_INTERRUPT_IENF:
+    fields: !!omap
+    - ENAF:
+        access: rw
+        description: Enables the falling edge or configures the active level interrupt
+          for each pin interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 8
+- GPIO_PIN_INTERRUPT_SIENF:
+    fields: !!omap
+    - SETENAF:
+        access: w
+        description: Ones written to this address set bits in the IENF, thus enabling
+          interrupts
+        lsb: 0
+        reset_value: ''
+        width: 8
+- GPIO_PIN_INTERRUPT_CIENF:
+    fields: !!omap
+    - CENAF:
+        access: w
+        description: Ones written to this address clears bits in the IENF, thus disabling
+          interrupts
+        lsb: 0
+        reset_value: ''
+        width: 8
+- GPIO_PIN_INTERRUPT_RISE:
+    fields: !!omap
+    - RDET:
+        access: rw
+        description: Rising edge detect
+        lsb: 0
+        reset_value: '0'
+        width: 8
+- GPIO_PIN_INTERRUPT_FALL:
+    fields: !!omap
+    - FDET:
+        access: rw
+        description: Falling edge detect
+        lsb: 0
+        reset_value: '0'
+        width: 8
+- GPIO_PIN_INTERRUPT_IST:
+    fields: !!omap
+    - PSTAT:
+        access: rw
+        description: Pin interrupt status
+        lsb: 0
+        reset_value: '0'
+        width: 8
+- GPIO_GROUP0_INTERRUPT_CTRL:
+    fields: !!omap
+    - INT:
+        access: rw
+        description: Group interrupt status
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - COMB:
+        access: rw
+        description: Combine enabled inputs for group interrupt
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - TRIG:
+        access: rw
+        description: Group interrupt trigger
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- GPIO_GROUP0_INTERRUPT_PORT_POL0:
+    fields: !!omap
+    - POL:
+        access: rw
+        description: Configure pin polarity of port 0 pins for group interrupt
+        lsb: 0
+        reset_value: '1'
+        width: 32
+- GPIO_GROUP0_INTERRUPT_PORT_POL1:
+    fields: !!omap
+    - POL:
+        access: rw
+        description: Configure pin polarity of port 1 pins for group interrupt
+        lsb: 0
+        reset_value: '1'
+        width: 32
+- GPIO_GROUP0_INTERRUPT_PORT_POL2:
+    fields: !!omap
+    - POL:
+        access: rw
+        description: Configure pin polarity of port 2 pins for group interrupt
+        lsb: 0
+        reset_value: '1'
+        width: 32
+- GPIO_GROUP0_INTERRUPT_PORT_POL3:
+    fields: !!omap
+    - POL:
+        access: rw
+        description: Configure pin polarity of port 3 pins for group interrupt
+        lsb: 0
+        reset_value: '1'
+        width: 32
+- GPIO_GROUP0_INTERRUPT_PORT_POL4:
+    fields: !!omap
+    - POL:
+        access: rw
+        description: Configure pin polarity of port 4 pins for group interrupt
+        lsb: 0
+        reset_value: '1'
+        width: 32
+- GPIO_GROUP0_INTERRUPT_PORT_POL5:
+    fields: !!omap
+    - POL:
+        access: rw
+        description: Configure pin polarity of port 5 pins for group interrupt
+        lsb: 0
+        reset_value: '1'
+        width: 32
+- GPIO_GROUP0_INTERRUPT_PORT_POL6:
+    fields: !!omap
+    - POL:
+        access: rw
+        description: Configure pin polarity of port 6 pins for group interrupt
+        lsb: 0
+        reset_value: '1'
+        width: 32
+- GPIO_GROUP0_INTERRUPT_PORT_POL7:
+    fields: !!omap
+    - POL:
+        access: rw
+        description: Configure pin polarity of port 7 pins for group interrupt
+        lsb: 0
+        reset_value: '1'
+        width: 32
+- GPIO_GROUP0_INTERRUPT_PORT_ENA0:
+    fields: !!omap
+    - ENA:
+        access: rw
+        description: Enable port 0 pin for group interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO_GROUP0_INTERRUPT_PORT_ENA1:
+    fields: !!omap
+    - ENA:
+        access: rw
+        description: Enable port 1 pin for group interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO_GROUP0_INTERRUPT_PORT_ENA2:
+    fields: !!omap
+    - ENA:
+        access: rw
+        description: Enable port 2 pin for group interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO_GROUP0_INTERRUPT_PORT_ENA3:
+    fields: !!omap
+    - ENA:
+        access: rw
+        description: Enable port 3 pin for group interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO_GROUP0_INTERRUPT_PORT_ENA4:
+    fields: !!omap
+    - ENA:
+        access: rw
+        description: Enable port 4 pin for group interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO_GROUP0_INTERRUPT_PORT_ENA5:
+    fields: !!omap
+    - ENA:
+        access: rw
+        description: Enable port 5 pin for group interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO_GROUP0_INTERRUPT_PORT_ENA6:
+    fields: !!omap
+    - ENA:
+        access: rw
+        description: Enable port 6 pin for group interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO_GROUP0_INTERRUPT_PORT_ENA7:
+    fields: !!omap
+    - ENA:
+        access: rw
+        description: Enable port 7 pin for group interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO_GROUP1_INTERRUPT_CTRL:
+    fields: !!omap
+    - INT:
+        access: rw
+        description: Group interrupt status
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - COMB:
+        access: rw
+        description: Combine enabled inputs for group interrupt
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - TRIG:
+        access: rw
+        description: Group interrupt trigger
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- GPIO_GROUP1_INTERRUPT_PORT_POL0:
+    fields: !!omap
+    - POL:
+        access: rw
+        description: Configure pin polarity of port 0 pins for group interrupt
+        lsb: 0
+        reset_value: '1'
+        width: 32
+- GPIO_GROUP1_INTERRUPT_PORT_POL1:
+    fields: !!omap
+    - POL:
+        access: rw
+        description: Configure pin polarity of port 1 pins for group interrupt
+        lsb: 0
+        reset_value: '1'
+        width: 32
+- GPIO_GROUP1_INTERRUPT_PORT_POL2:
+    fields: !!omap
+    - POL:
+        access: rw
+        description: Configure pin polarity of port 2 pins for group interrupt
+        lsb: 0
+        reset_value: '1'
+        width: 32
+- GPIO_GROUP1_INTERRUPT_PORT_POL3:
+    fields: !!omap
+    - POL:
+        access: rw
+        description: Configure pin polarity of port 3 pins for group interrupt
+        lsb: 0
+        reset_value: '1'
+        width: 32
+- GPIO_GROUP1_INTERRUPT_PORT_POL4:
+    fields: !!omap
+    - POL:
+        access: rw
+        description: Configure pin polarity of port 4 pins for group interrupt
+        lsb: 0
+        reset_value: '1'
+        width: 32
+- GPIO_GROUP1_INTERRUPT_PORT_POL5:
+    fields: !!omap
+    - POL:
+        access: rw
+        description: Configure pin polarity of port 5 pins for group interrupt
+        lsb: 0
+        reset_value: '1'
+        width: 32
+- GPIO_GROUP1_INTERRUPT_PORT_POL6:
+    fields: !!omap
+    - POL:
+        access: rw
+        description: Configure pin polarity of port 6 pins for group interrupt
+        lsb: 0
+        reset_value: '1'
+        width: 32
+- GPIO_GROUP1_INTERRUPT_PORT_POL7:
+    fields: !!omap
+    - POL:
+        access: rw
+        description: Configure pin polarity of port 7 pins for group interrupt
+        lsb: 0
+        reset_value: '1'
+        width: 32
+- GPIO_GROUP1_INTERRUPT_PORT_ENA0:
+    fields: !!omap
+    - ENA:
+        access: rw
+        description: Enable port 0 pin for group interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO_GROUP1_INTERRUPT_PORT_ENA1:
+    fields: !!omap
+    - ENA:
+        access: rw
+        description: Enable port 1 pin for group interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO_GROUP1_INTERRUPT_PORT_ENA2:
+    fields: !!omap
+    - ENA:
+        access: rw
+        description: Enable port 2 pin for group interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO_GROUP1_INTERRUPT_PORT_ENA3:
+    fields: !!omap
+    - ENA:
+        access: rw
+        description: Enable port 3 pin for group interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO_GROUP1_INTERRUPT_PORT_ENA4:
+    fields: !!omap
+    - ENA:
+        access: rw
+        description: Enable port 4 pin for group interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO_GROUP1_INTERRUPT_PORT_ENA5:
+    fields: !!omap
+    - ENA:
+        access: rw
+        description: Enable port 5 pin for group interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO_GROUP1_INTERRUPT_PORT_ENA6:
+    fields: !!omap
+    - ENA:
+        access: rw
+        description: Enable port 6 pin for group interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO_GROUP1_INTERRUPT_PORT_ENA7:
+    fields: !!omap
+    - ENA:
+        access: rw
+        description: Enable port 7 pin for group interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO_B0:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B1:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B2:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B3:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B4:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B5:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B6:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B7:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B8:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B9:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B10:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B11:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B12:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B13:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B14:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B15:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B16:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B17:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B18:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B19:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B20:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B21:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B22:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B23:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B24:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B25:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B26:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B27:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B28:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B29:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B30:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B31:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B32:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B33:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B34:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B35:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B36:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B37:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B38:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B39:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B40:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B41:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B42:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B43:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B44:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B45:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B46:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B47:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B48:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B49:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B50:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B51:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B52:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B53:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B54:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B55:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B56:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B57:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B58:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B59:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B60:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B61:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B62:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B63:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B64:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B65:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B66:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B67:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B68:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B69:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B70:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B71:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B72:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B73:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B74:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B75:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B76:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B77:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B78:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B79:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B80:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B81:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B82:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B83:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B84:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B85:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B86:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B87:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B88:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B89:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B90:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B91:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B92:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B93:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B94:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B95:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B96:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B97:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B98:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B99:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B100:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B101:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B102:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B103:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B104:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B105:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B106:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B107:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B108:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B109:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B110:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B111:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B112:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B113:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B114:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B115:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B116:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B117:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B118:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B119:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B120:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B121:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B122:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B123:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B124:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B125:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B126:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B127:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B128:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B129:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B130:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B131:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B132:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B133:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B134:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B135:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B136:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B137:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B138:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B139:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B140:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B141:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B142:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B143:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B144:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B145:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B146:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B147:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B148:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B149:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B150:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B151:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B152:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B153:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B154:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B155:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B156:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B157:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B158:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B159:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B160:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B161:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B162:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B163:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B164:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B165:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B166:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B167:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B168:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B169:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B170:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B171:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B172:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B173:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B174:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B175:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B176:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B177:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B178:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B179:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B180:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B181:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B182:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B183:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B184:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B185:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B186:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B187:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B188:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B189:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B190:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B191:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B192:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B193:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B194:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B195:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B196:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B197:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B198:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B199:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B200:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B201:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B202:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B203:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B204:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B205:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B206:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B207:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B208:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B209:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B210:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B211:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B212:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B213:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B214:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B215:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B216:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B217:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B218:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B219:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B220:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B221:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B222:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B223:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B224:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B225:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B226:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B227:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B228:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B229:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B230:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B231:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B232:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B233:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B234:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B235:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B236:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B237:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B238:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B239:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B240:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B241:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B242:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B243:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B244:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B245:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B246:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B247:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B248:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B249:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B250:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B251:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B252:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B253:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B254:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_B255:
+    fields: !!omap
+    - PBYTE:
+        access: rw
+        description: GPIO port byte pin register
+        lsb: 0
+        reset_value: ''
+        width: 1
+- GPIO_W0:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W1:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W2:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W3:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W4:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W5:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W6:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W7:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W8:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W9:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W10:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W11:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W12:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W13:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W14:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W15:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W16:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W17:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W18:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W19:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W20:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W21:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W22:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W23:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W24:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W25:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W26:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W27:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W28:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W29:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W30:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W31:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W32:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W33:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W34:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W35:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W36:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W37:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W38:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W39:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W40:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W41:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W42:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W43:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W44:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W45:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W46:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W47:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W48:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W49:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W50:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W51:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W52:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W53:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W54:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W55:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W56:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W57:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W58:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W59:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W60:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W61:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W62:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W63:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W64:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W65:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W66:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W67:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W68:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W69:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W70:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W71:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W72:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W73:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W74:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W75:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W76:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W77:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W78:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W79:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W80:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W81:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W82:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W83:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W84:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W85:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W86:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W87:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W88:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W89:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W90:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W91:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W92:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W93:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W94:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W95:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W96:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W97:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W98:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W99:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W100:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W101:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W102:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W103:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W104:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W105:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W106:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W107:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W108:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W109:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W110:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W111:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W112:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W113:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W114:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W115:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W116:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W117:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W118:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W119:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W120:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W121:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W122:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W123:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W124:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W125:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W126:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W127:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W128:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W129:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W130:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W131:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W132:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W133:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W134:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W135:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W136:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W137:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W138:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W139:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W140:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W141:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W142:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W143:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W144:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W145:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W146:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W147:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W148:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W149:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W150:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W151:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W152:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W153:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W154:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W155:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W156:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W157:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W158:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W159:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W160:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W161:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W162:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W163:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W164:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W165:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W166:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W167:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W168:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W169:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W170:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W171:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W172:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W173:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W174:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W175:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W176:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W177:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W178:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W179:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W180:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W181:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W182:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W183:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W184:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W185:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W186:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W187:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W188:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W189:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W190:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W191:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W192:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W193:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W194:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W195:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W196:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W197:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W198:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W199:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W200:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W201:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W202:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W203:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W204:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W205:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W206:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W207:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W208:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W209:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W210:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W211:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W212:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W213:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W214:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W215:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W216:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W217:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W218:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W219:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W220:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W221:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W222:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W223:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W224:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W225:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W226:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W227:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W228:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W229:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W230:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W231:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W232:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W233:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W234:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W235:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W236:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W237:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W238:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W239:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W240:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W241:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W242:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W243:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W244:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W245:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W246:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W247:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W248:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W249:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W250:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W251:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W252:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W253:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W254:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO_W255:
+    fields: !!omap
+    - PWORD:
+        access: rw
+        description: GPIO port word pin register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO0_DIR:
+    fields: !!omap
+    - DIR:
+        access: rw
+        description: Selects pin direction for GPIO0
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO1_DIR:
+    fields: !!omap
+    - DIR:
+        access: rw
+        description: Selects pin direction for GPIO1
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO2_DIR:
+    fields: !!omap
+    - DIR:
+        access: rw
+        description: Selects pin direction for GPIO2
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO3_DIR:
+    fields: !!omap
+    - DIR:
+        access: rw
+        description: Selects pin direction for GPIO3
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO4_DIR:
+    fields: !!omap
+    - DIR:
+        access: rw
+        description: Selects pin direction for GPIO4
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO5_DIR:
+    fields: !!omap
+    - DIR:
+        access: rw
+        description: Selects pin direction for GPIO5
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO6_DIR:
+    fields: !!omap
+    - DIR:
+        access: rw
+        description: Selects pin direction for GPIO6
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO7_DIR:
+    fields: !!omap
+    - DIR:
+        access: rw
+        description: Selects pin direction for GPIO7
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO0_MASK:
+    fields: !!omap
+    - MASK:
+        access: rw
+        description: Controls which pins are active in the MPORT register
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO1_MASK:
+    fields: !!omap
+    - MASK:
+        access: rw
+        description: Controls which pins are active in the MPORT register
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO2_MASK:
+    fields: !!omap
+    - MASK:
+        access: rw
+        description: Controls which pins are active in the MPORT register
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO3_MASK:
+    fields: !!omap
+    - MASK:
+        access: rw
+        description: Controls which pins are active in the MPORT register
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO4_MASK:
+    fields: !!omap
+    - MASK:
+        access: rw
+        description: Controls which pins are active in the MPORT register
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO5_MASK:
+    fields: !!omap
+    - MASK:
+        access: rw
+        description: Controls which pins are active in the MPORT register
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO6_MASK:
+    fields: !!omap
+    - MASK:
+        access: rw
+        description: Controls which pins are active in the MPORT register
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO7_MASK:
+    fields: !!omap
+    - MASK:
+        access: rw
+        description: Controls which pins are active in the MPORT register
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO0_PIN:
+    fields: !!omap
+    - PORT:
+        access: rw
+        description: Reads pin states or loads output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO1_PIN:
+    fields: !!omap
+    - PORT:
+        access: rw
+        description: Reads pin states or loads output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO2_PIN:
+    fields: !!omap
+    - PORT:
+        access: rw
+        description: Reads pin states or loads output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO3_PIN:
+    fields: !!omap
+    - PORT:
+        access: rw
+        description: Reads pin states or loads output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO4_PIN:
+    fields: !!omap
+    - PORT:
+        access: rw
+        description: Reads pin states or loads output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO5_PIN:
+    fields: !!omap
+    - PORT:
+        access: rw
+        description: Reads pin states or loads output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO6_PIN:
+    fields: !!omap
+    - PORT:
+        access: rw
+        description: Reads pin states or loads output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO7_PIN:
+    fields: !!omap
+    - PORT:
+        access: rw
+        description: Reads pin states or loads output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO0_MPIN:
+    fields: !!omap
+    - MPORT:
+        access: rw
+        description: Masked port register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO1_MPIN:
+    fields: !!omap
+    - MPORT:
+        access: rw
+        description: Masked port register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO2_MPIN:
+    fields: !!omap
+    - MPORT:
+        access: rw
+        description: Masked port register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO3_MPIN:
+    fields: !!omap
+    - MPORT:
+        access: rw
+        description: Masked port register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO4_MPIN:
+    fields: !!omap
+    - MPORT:
+        access: rw
+        description: Masked port register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO5_MPIN:
+    fields: !!omap
+    - MPORT:
+        access: rw
+        description: Masked port register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO6_MPIN:
+    fields: !!omap
+    - MPORT:
+        access: rw
+        description: Masked port register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO7_MPIN:
+    fields: !!omap
+    - MPORT:
+        access: rw
+        description: Masked port register
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO0_SET:
+    fields: !!omap
+    - SET:
+        access: rw
+        description: Read or set output bits
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO1_SET:
+    fields: !!omap
+    - SET:
+        access: rw
+        description: Read or set output bits
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO2_SET:
+    fields: !!omap
+    - SET:
+        access: rw
+        description: Read or set output bits
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO3_SET:
+    fields: !!omap
+    - SET:
+        access: rw
+        description: Read or set output bits
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO4_SET:
+    fields: !!omap
+    - SET:
+        access: rw
+        description: Read or set output bits
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO5_SET:
+    fields: !!omap
+    - SET:
+        access: rw
+        description: Read or set output bits
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO6_SET:
+    fields: !!omap
+    - SET:
+        access: rw
+        description: Read or set output bits
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO7_SET:
+    fields: !!omap
+    - SET:
+        access: rw
+        description: Read or set output bits
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- GPIO0_CLR:
+    fields: !!omap
+    - CLR:
+        access: w
+        description: Clear output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO1_CLR:
+    fields: !!omap
+    - CLR:
+        access: w
+        description: Clear output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO2_CLR:
+    fields: !!omap
+    - CLR:
+        access: w
+        description: Clear output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO3_CLR:
+    fields: !!omap
+    - CLR:
+        access: w
+        description: Clear output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO4_CLR:
+    fields: !!omap
+    - CLR:
+        access: w
+        description: Clear output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO5_CLR:
+    fields: !!omap
+    - CLR:
+        access: w
+        description: Clear output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO6_CLR:
+    fields: !!omap
+    - CLR:
+        access: w
+        description: Clear output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO7_CLR:
+    fields: !!omap
+    - CLR:
+        access: w
+        description: Clear output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO0_NOT:
+    fields: !!omap
+    - NOT:
+        access: w
+        description: Toggle output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO1_NOT:
+    fields: !!omap
+    - NOT:
+        access: w
+        description: Toggle output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO2_NOT:
+    fields: !!omap
+    - NOT:
+        access: w
+        description: Toggle output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO3_NOT:
+    fields: !!omap
+    - NOT:
+        access: w
+        description: Toggle output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO4_NOT:
+    fields: !!omap
+    - NOT:
+        access: w
+        description: Toggle output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO5_NOT:
+    fields: !!omap
+    - NOT:
+        access: w
+        description: Toggle output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO6_NOT:
+    fields: !!omap
+    - NOT:
+        access: w
+        description: Toggle output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
+- GPIO7_NOT:
+    fields: !!omap
+    - NOT:
+        access: w
+        description: Toggle output bits
+        lsb: 0
+        reset_value: ''
+        width: 32
diff --git a/libopencm3/scripts/data/lpc43xx/i2c.yaml b/libopencm3/scripts/data/lpc43xx/i2c.yaml
new file mode 100644
index 0000000..0e59a6a
--- /dev/null
+++ b/libopencm3/scripts/data/lpc43xx/i2c.yaml
@@ -0,0 +1,415 @@
+!!omap
+- I2C0_CONSET:
+    fields: !!omap
+    - AA:
+        access: rw
+        description: Assert acknowledge flag
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - SI:
+        access: rw
+        description: I2C interrupt flag
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - STO:
+        access: rw
+        description: STOP flag
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - STA:
+        access: rw
+        description: START flag
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - I2EN:
+        access: rw
+        description: I2C interface enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+- I2C1_CONSET:
+    fields: !!omap
+    - AA:
+        access: rw
+        description: Assert acknowledge flag
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - SI:
+        access: rw
+        description: I2C interrupt flag
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - STO:
+        access: rw
+        description: STOP flag
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - STA:
+        access: rw
+        description: START flag
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - I2EN:
+        access: rw
+        description: I2C interface enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+- I2C0_STAT:
+    fields: !!omap
+    - STATUS:
+        access: r
+        description: These bits give the actual status information about the I2C interface
+        lsb: 3
+        reset_value: '0x1f'
+        width: 5
+- I2C1_STAT:
+    fields: !!omap
+    - STATUS:
+        access: r
+        description: These bits give the actual status information about the I2C interface
+        lsb: 3
+        reset_value: '0x1f'
+        width: 5
+- I2C0_DAT:
+    fields: !!omap
+    - DATA:
+        access: rw
+        description: This register holds data values that have been received or are
+          to be transmitted
+        lsb: 0
+        reset_value: '0'
+        width: 8
+- I2C1_DAT:
+    fields: !!omap
+    - DATA:
+        access: rw
+        description: This register holds data values that have been received or are
+          to be transmitted
+        lsb: 0
+        reset_value: '0'
+        width: 8
+- I2C0_ADR0:
+    fields: !!omap
+    - GC:
+        access: rw
+        description: General Call enable bit
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - ADDRESS:
+        access: rw
+        description: The I2C device address for slave mode
+        lsb: 1
+        reset_value: '0'
+        width: 7
+- I2C1_ADR0:
+    fields: !!omap
+    - GC:
+        access: rw
+        description: General Call enable bit
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - ADDRESS:
+        access: rw
+        description: The I2C device address for slave mode
+        lsb: 1
+        reset_value: '0'
+        width: 7
+- I2C0_SCLH:
+    fields: !!omap
+    - SCLH:
+        access: rw
+        description: Count for SCL HIGH time period selection
+        lsb: 0
+        reset_value: '0x0004'
+        width: 16
+- I2C1_SCLH:
+    fields: !!omap
+    - SCLH:
+        access: rw
+        description: Count for SCL HIGH time period selection
+        lsb: 0
+        reset_value: '0x0004'
+        width: 16
+- I2C0_SCLL:
+    fields: !!omap
+    - SCLL:
+        access: rw
+        description: Count for SCL LOW time period selection
+        lsb: 0
+        reset_value: '0x0004'
+        width: 16
+- I2C1_SCLL:
+    fields: !!omap
+    - SCLL:
+        access: rw
+        description: Count for SCL LOW time period selection
+        lsb: 0
+        reset_value: '0x0004'
+        width: 16
+- I2C0_CONCLR:
+    fields: !!omap
+    - AAC:
+        access: w
+        description: Assert acknowledge Clear bit
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - SIC:
+        access: w
+        description: I2C interrupt Clear bit
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - STAC:
+        access: w
+        description: START flag Clear bit
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - I2ENC:
+        access: w
+        description: I2C interface Disable bit
+        lsb: 6
+        reset_value: '0'
+        width: 1
+- I2C1_CONCLR:
+    fields: !!omap
+    - AAC:
+        access: w
+        description: Assert acknowledge Clear bit
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - SIC:
+        access: w
+        description: I2C interrupt Clear bit
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - STAC:
+        access: w
+        description: START flag Clear bit
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - I2ENC:
+        access: w
+        description: I2C interface Disable bit
+        lsb: 6
+        reset_value: '0'
+        width: 1
+- I2C0_MMCTRL:
+    fields: !!omap
+    - MM_ENA:
+        access: rw
+        description: Monitor mode enable
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - ENA_SCL:
+        access: rw
+        description: SCL output enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - MATCH_ALL:
+        access: rw
+        description: Select interrupt register match
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- I2C1_MMCTRL:
+    fields: !!omap
+    - MM_ENA:
+        access: rw
+        description: Monitor mode enable
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - ENA_SCL:
+        access: rw
+        description: SCL output enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - MATCH_ALL:
+        access: rw
+        description: Select interrupt register match
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- I2C0_ADR1:
+    fields: !!omap
+    - GC:
+        access: rw
+        description: General Call enable bit
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - ADDRESS:
+        access: rw
+        description: The I2C device address for slave mode
+        lsb: 1
+        reset_value: '0'
+        width: 7
+- I2C1_ADR1:
+    fields: !!omap
+    - GC:
+        access: rw
+        description: General Call enable bit
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - ADDRESS:
+        access: rw
+        description: The I2C device address for slave mode
+        lsb: 1
+        reset_value: '0'
+        width: 7
+- I2C0_ADR2:
+    fields: !!omap
+    - GC:
+        access: rw
+        description: General Call enable bit
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - ADDRESS:
+        access: rw
+        description: The I2C device address for slave mode
+        lsb: 1
+        reset_value: '0'
+        width: 7
+- I2C1_ADR2:
+    fields: !!omap
+    - GC:
+        access: rw
+        description: General Call enable bit
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - ADDRESS:
+        access: rw
+        description: The I2C device address for slave mode
+        lsb: 1
+        reset_value: '0'
+        width: 7
+- I2C0_ADR3:
+    fields: !!omap
+    - GC:
+        access: rw
+        description: General Call enable bit
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - ADDRESS:
+        access: rw
+        description: The I2C device address for slave mode
+        lsb: 1
+        reset_value: '0'
+        width: 7
+- I2C1_ADR3:
+    fields: !!omap
+    - GC:
+        access: rw
+        description: General Call enable bit
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - ADDRESS:
+        access: rw
+        description: The I2C device address for slave mode
+        lsb: 1
+        reset_value: '0'
+        width: 7
+- I2C0_DATA_BUFFER:
+    fields: !!omap
+    - DATA:
+        access: r
+        description: This register holds contents of the 8 MSBs of the DAT shift register
+        lsb: 0
+        reset_value: '0'
+        width: 8
+- I2C1_DATA_BUFFER:
+    fields: !!omap
+    - DATA:
+        access: r
+        description: This register holds contents of the 8 MSBs of the DAT shift register
+        lsb: 0
+        reset_value: '0'
+        width: 8
+- I2C0_MASK0:
+    fields: !!omap
+    - MASK:
+        access: rw
+        description: Mask bits
+        lsb: 1
+        reset_value: '0'
+        width: 7
+- I2C1_MASK0:
+    fields: !!omap
+    - MASK:
+        access: rw
+        description: Mask bits
+        lsb: 1
+        reset_value: '0'
+        width: 7
+- I2C0_MASK1:
+    fields: !!omap
+    - MASK:
+        access: rw
+        description: Mask bits
+        lsb: 1
+        reset_value: '0'
+        width: 7
+- I2C1_MASK1:
+    fields: !!omap
+    - MASK:
+        access: rw
+        description: Mask bits
+        lsb: 1
+        reset_value: '0'
+        width: 7
+- I2C0_MASK2:
+    fields: !!omap
+    - MASK:
+        access: rw
+        description: Mask bits
+        lsb: 1
+        reset_value: '0'
+        width: 7
+- I2C1_MASK2:
+    fields: !!omap
+    - MASK:
+        access: rw
+        description: Mask bits
+        lsb: 1
+        reset_value: '0'
+        width: 7
+- I2C0_MASK3:
+    fields: !!omap
+    - MASK:
+        access: rw
+        description: Mask bits
+        lsb: 1
+        reset_value: '0'
+        width: 7
+- I2C1_MASK3:
+    fields: !!omap
+    - MASK:
+        access: rw
+        description: Mask bits
+        lsb: 1
+        reset_value: '0'
+        width: 7
diff --git a/libopencm3/scripts/data/lpc43xx/i2s.yaml b/libopencm3/scripts/data/lpc43xx/i2s.yaml
new file mode 100644
index 0000000..833e5b5
--- /dev/null
+++ b/libopencm3/scripts/data/lpc43xx/i2s.yaml
@@ -0,0 +1,619 @@
+!!omap
+- I2S0_DAO:
+    fields: !!omap
+    - WORDWIDTH:
+        access: rw
+        description: Selects the number of bytes in data
+        lsb: 0
+        reset_value: '1'
+        width: 2
+    - MONO:
+        access: rw
+        description: When 1, data is of monaural format. When 0, the data is in stereo
+          format
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - STOP:
+        access: rw
+        description: When 1, disables accesses on FIFOs, places the transmit channel
+          in mute mode
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - RESET:
+        access: rw
+        description: When 1, asynchronously resets the transmit channel and FIFO
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - WS_SEL:
+        access: rw
+        description: When 0, the interface is in master mode. When 1, the interface
+          is in slave mode
+        lsb: 5
+        reset_value: '1'
+        width: 1
+    - WS_HALFPERIOD:
+        access: rw
+        description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod
+          = 31.
+        lsb: 6
+        reset_value: '0x1f'
+        width: 9
+    - MUTE:
+        access: rw
+        description: When 1, the transmit channel sends only zeroes
+        lsb: 15
+        reset_value: '1'
+        width: 1
+- I2S1_DAO:
+    fields: !!omap
+    - WORDWIDTH:
+        access: rw
+        description: Selects the number of bytes in data
+        lsb: 0
+        reset_value: '1'
+        width: 2
+    - MONO:
+        access: rw
+        description: When 1, data is of monaural format. When 0, the data is in stereo
+          format
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - STOP:
+        access: rw
+        description: When 1, disables accesses on FIFOs, places the transmit channel
+          in mute mode
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - RESET:
+        access: rw
+        description: When 1, asynchronously resets the transmit channel and FIFO
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - WS_SEL:
+        access: rw
+        description: When 0, the interface is in master mode. When 1, the interface
+          is in slave mode
+        lsb: 5
+        reset_value: '1'
+        width: 1
+    - WS_HALFPERIOD:
+        access: rw
+        description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod
+          = 31.
+        lsb: 6
+        reset_value: '0x1f'
+        width: 9
+    - MUTE:
+        access: rw
+        description: When 1, the transmit channel sends only zeroes
+        lsb: 15
+        reset_value: '1'
+        width: 1
+- I2S0_DAI:
+    fields: !!omap
+    - WORDWIDTH:
+        access: rw
+        description: Selects the number of bytes in data
+        lsb: 0
+        reset_value: '1'
+        width: 2
+    - MONO:
+        access: rw
+        description: When 1, data is of monaural format. When 0, the data is in stereo
+          format
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - STOP:
+        access: rw
+        description: When 1, disables accesses on FIFOs, places the transmit channel
+          in mute mode
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - RESET:
+        access: rw
+        description: When 1, asynchronously resets the transmit channel and FIFO
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - WS_SEL:
+        access: rw
+        description: When 0, the interface is in master mode. When 1, the interface
+          is in slave mode
+        lsb: 5
+        reset_value: '1'
+        width: 1
+    - WS_HALFPERIOD:
+        access: rw
+        description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod
+          = 31.
+        lsb: 6
+        reset_value: '0x1f'
+        width: 9
+    - MUTE:
+        access: rw
+        description: When 1, the transmit channel sends only zeroes
+        lsb: 15
+        reset_value: '1'
+        width: 1
+- I2S1_DAI:
+    fields: !!omap
+    - WORDWIDTH:
+        access: rw
+        description: Selects the number of bytes in data
+        lsb: 0
+        reset_value: '1'
+        width: 2
+    - MONO:
+        access: rw
+        description: When 1, data is of monaural format. When 0, the data is in stereo
+          format
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - STOP:
+        access: rw
+        description: When 1, disables accesses on FIFOs, places the transmit channel
+          in mute mode
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - RESET:
+        access: rw
+        description: When 1, asynchronously resets the transmit channel and FIFO
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - WS_SEL:
+        access: rw
+        description: When 0, the interface is in master mode. When 1, the interface
+          is in slave mode
+        lsb: 5
+        reset_value: '1'
+        width: 1
+    - WS_HALFPERIOD:
+        access: rw
+        description: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod
+          = 31.
+        lsb: 6
+        reset_value: '0x1f'
+        width: 9
+    - MUTE:
+        access: rw
+        description: When 1, the transmit channel sends only zeroes
+        lsb: 15
+        reset_value: '1'
+        width: 1
+- I2S0_TXFIFO:
+    fields: !!omap
+    - I2STXFIFO:
+        access: w
+        description: 8 x 32-bit transmit FIFO
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- I2S1_TXFIFO:
+    fields: !!omap
+    - I2STXFIFO:
+        access: w
+        description: 8 x 32-bit transmit FIFO
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- I2S0_RXFIFO:
+    fields: !!omap
+    - I2SRXFIFO:
+        access: r
+        description: 8 x 32-bit receive FIFO
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- I2S1_RXFIFO:
+    fields: !!omap
+    - I2SRXFIFO:
+        access: r
+        description: 8 x 32-bit receive FIFO
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- I2S0_STATE:
+    fields: !!omap
+    - IRQ:
+        access: r
+        description: This bit reflects the presence of Receive Interrupt or Transmit
+          Interrupt
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - DMAREQ1:
+        access: r
+        description: This bit reflects the presence of Receive or Transmit DMA Request
+          1
+        lsb: 1
+        reset_value: '1'
+        width: 1
+    - DMAREQ2:
+        access: r
+        description: This bit reflects the presence of Receive or Transmit DMA Request
+          2
+        lsb: 2
+        reset_value: '1'
+        width: 1
+    - RX_LEVEL:
+        access: r
+        description: Reflects the current level of the Receive FIFO
+        lsb: 8
+        reset_value: '0'
+        width: 4
+    - TX_LEVEL:
+        access: r
+        description: Reflects the current level of the Transmit FIFO
+        lsb: 16
+        reset_value: '0'
+        width: 4
+- I2S1_STATE:
+    fields: !!omap
+    - IRQ:
+        access: r
+        description: This bit reflects the presence of Receive Interrupt or Transmit
+          Interrupt
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - DMAREQ1:
+        access: r
+        description: This bit reflects the presence of Receive or Transmit DMA Request
+          1
+        lsb: 1
+        reset_value: '1'
+        width: 1
+    - DMAREQ2:
+        access: r
+        description: This bit reflects the presence of Receive or Transmit DMA Request
+          2
+        lsb: 2
+        reset_value: '1'
+        width: 1
+    - RX_LEVEL:
+        access: r
+        description: Reflects the current level of the Receive FIFO
+        lsb: 8
+        reset_value: '0'
+        width: 4
+    - TX_LEVEL:
+        access: r
+        description: Reflects the current level of the Transmit FIFO
+        lsb: 16
+        reset_value: '0'
+        width: 4
+- I2S0_DMA1:
+    fields: !!omap
+    - RX_DMA1_ENABLE:
+        access: rw
+        description: When 1, enables DMA1 for I2S receive
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - TX_DMA1_ENABLE:
+        access: rw
+        description: When 1, enables DMA1 for I2S transmit
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - RX_DEPTH_DMA1:
+        access: rw
+        description: Set the FIFO level that triggers a receive DMA request on DMA1
+        lsb: 8
+        reset_value: '0'
+        width: 4
+    - TX_DEPTH_DMA1:
+        access: rw
+        description: Set the FIFO level that triggers a transmit DMA request on DMA1
+        lsb: 16
+        reset_value: '0'
+        width: 4
+- I2S1_DMA1:
+    fields: !!omap
+    - RX_DMA1_ENABLE:
+        access: rw
+        description: When 1, enables DMA1 for I2S receive
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - TX_DMA1_ENABLE:
+        access: rw
+        description: When 1, enables DMA1 for I2S transmit
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - RX_DEPTH_DMA1:
+        access: rw
+        description: Set the FIFO level that triggers a receive DMA request on DMA1
+        lsb: 8
+        reset_value: '0'
+        width: 4
+    - TX_DEPTH_DMA1:
+        access: rw
+        description: Set the FIFO level that triggers a transmit DMA request on DMA1
+        lsb: 16
+        reset_value: '0'
+        width: 4
+- I2S0_DMA2:
+    fields: !!omap
+    - RX_DMA2_ENABLE:
+        access: rw
+        description: When 1, enables DMA2 for I2S receive
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - TX_DMA2_ENABLE:
+        access: rw
+        description: When 1, enables DMA2 for I2S transmit
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - RX_DEPTH_DMA2:
+        access: rw
+        description: Set the FIFO level that triggers a receive DMA request on DMA2
+        lsb: 8
+        reset_value: '0'
+        width: 4
+    - TX_DEPTH_DMA2:
+        access: rw
+        description: Set the FIFO level that triggers a transmit DMA request on DMA2
+        lsb: 16
+        reset_value: '0'
+        width: 4
+- I2S1_DMA2:
+    fields: !!omap
+    - RX_DMA2_ENABLE:
+        access: rw
+        description: When 1, enables DMA2 for I2S receive
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - TX_DMA2_ENABLE:
+        access: rw
+        description: When 1, enables DMA2 for I2S transmit
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - RX_DEPTH_DMA2:
+        access: rw
+        description: Set the FIFO level that triggers a receive DMA request on DMA2
+        lsb: 8
+        reset_value: '0'
+        width: 4
+    - TX_DEPTH_DMA2:
+        access: rw
+        description: Set the FIFO level that triggers a transmit DMA request on DMA2
+        lsb: 16
+        reset_value: '0'
+        width: 4
+- I2S0_IRQ:
+    fields: !!omap
+    - RX_IRQ_ENABLE:
+        access: rw
+        description: When 1, enables I2S receive interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - TX_IRQ_ENABLE:
+        access: rw
+        description: When 1, enables I2S transmit interrupt
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - RX_DEPTH_IRQ:
+        access: rw
+        description: Set the FIFO level on which to create an irq request.
+        lsb: 8
+        reset_value: '0'
+        width: 4
+    - TX_DEPTH_IRQ:
+        access: rw
+        description: Set the FIFO level on which to create an irq request.
+        lsb: 16
+        reset_value: '0'
+        width: 4
+- I2S1_IRQ:
+    fields: !!omap
+    - RX_IRQ_ENABLE:
+        access: rw
+        description: When 1, enables I2S receive interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - TX_IRQ_ENABLE:
+        access: rw
+        description: When 1, enables I2S transmit interrupt
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - RX_DEPTH_IRQ:
+        access: rw
+        description: Set the FIFO level on which to create an irq request.
+        lsb: 8
+        reset_value: '0'
+        width: 4
+    - TX_DEPTH_IRQ:
+        access: rw
+        description: Set the FIFO level on which to create an irq request.
+        lsb: 16
+        reset_value: '0'
+        width: 4
+- I2S0_TXRATE:
+    fields: !!omap
+    - Y_DIVIDER:
+        access: rw
+        description: I2S transmit MCLK rate denominator
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - X_DIVIDER:
+        access: rw
+        description: I2S transmit MCLK rate numerator
+        lsb: 8
+        reset_value: '0'
+        width: 8
+- I2S1_TXRATE:
+    fields: !!omap
+    - Y_DIVIDER:
+        access: rw
+        description: I2S transmit MCLK rate denominator
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - X_DIVIDER:
+        access: rw
+        description: I2S transmit MCLK rate numerator
+        lsb: 8
+        reset_value: '0'
+        width: 8
+- I2S0_RXRATE:
+    fields: !!omap
+    - Y_DIVIDER:
+        access: rw
+        description: I2S receive MCLK rate denominator
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - X_DIVIDER:
+        access: rw
+        description: I2S receive MCLK rate numerator
+        lsb: 8
+        reset_value: '0'
+        width: 8
+- I2S1_RXRATE:
+    fields: !!omap
+    - Y_DIVIDER:
+        access: rw
+        description: I2S receive MCLK rate denominator
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - X_DIVIDER:
+        access: rw
+        description: I2S receive MCLK rate numerator
+        lsb: 8
+        reset_value: '0'
+        width: 8
+- I2S0_TXBITRATE:
+    fields: !!omap
+    - TX_BITRATE:
+        access: rw
+        description: I2S transmit bit rate
+        lsb: 0
+        reset_value: '0'
+        width: 6
+- I2S1_TXBITRATE:
+    fields: !!omap
+    - TX_BITRATE:
+        access: rw
+        description: I2S transmit bit rate
+        lsb: 0
+        reset_value: '0'
+        width: 6
+- I2S0_RXBITRATE:
+    fields: !!omap
+    - RX_BITRATE:
+        access: rw
+        description: I2S receive bit rate
+        lsb: 0
+        reset_value: '0'
+        width: 6
+- I2S1_RXBITRATE:
+    fields: !!omap
+    - RX_BITRATE:
+        access: rw
+        description: I2S receive bit rate
+        lsb: 0
+        reset_value: '0'
+        width: 6
+- I2S0_TXMODE:
+    fields: !!omap
+    - TXCLKSEL:
+        access: rw
+        description: Clock source selection for the transmit bit clock divider
+        lsb: 0
+        reset_value: '0'
+        width: 2
+    - TX4PIN:
+        access: rw
+        description: Transmit 4-pin mode selection
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - TXMCENA:
+        access: rw
+        description: Enable for the TX_MCLK output
+        lsb: 3
+        reset_value: '0'
+        width: 1
+- I2S1_TXMODE:
+    fields: !!omap
+    - TXCLKSEL:
+        access: rw
+        description: Clock source selection for the transmit bit clock divider
+        lsb: 0
+        reset_value: '0'
+        width: 2
+    - TX4PIN:
+        access: rw
+        description: Transmit 4-pin mode selection
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - TXMCENA:
+        access: rw
+        description: Enable for the TX_MCLK output
+        lsb: 3
+        reset_value: '0'
+        width: 1
+- I2S0_RXMODE:
+    fields: !!omap
+    - RXCLKSEL:
+        access: rw
+        description: Clock source selection for the receive bit clock divider
+        lsb: 0
+        reset_value: '0'
+        width: 2
+    - RX4PIN:
+        access: rw
+        description: Receive 4-pin mode selection
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - RXMCENA:
+        access: rw
+        description: Enable for the RX_MCLK output
+        lsb: 3
+        reset_value: '0'
+        width: 1
+- I2S1_RXMODE:
+    fields: !!omap
+    - RXCLKSEL:
+        access: rw
+        description: Clock source selection for the receive bit clock divider
+        lsb: 0
+        reset_value: '0'
+        width: 2
+    - RX4PIN:
+        access: rw
+        description: Receive 4-pin mode selection
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - RXMCENA:
+        access: rw
+        description: Enable for the RX_MCLK output
+        lsb: 3
+        reset_value: '0'
+        width: 1
diff --git a/libopencm3/scripts/data/lpc43xx/rgu.yaml b/libopencm3/scripts/data/lpc43xx/rgu.yaml
new file mode 100644
index 0000000..6561d32
--- /dev/null
+++ b/libopencm3/scripts/data/lpc43xx/rgu.yaml
@@ -0,0 +1,1199 @@
+!!omap
+- RESET_CTRL0:
+    fields: !!omap
+    - CORE_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - PERIPH_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - MASTER_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - WWDT_RST:
+        access: ''
+        description: Writing a one to this bit has no effect
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - CREG_RST:
+        access: ''
+        description: Writing a one to this bit has no effect
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - BUS_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 8
+        reset_value: '0'
+        width: 1
+    - SCU_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 9
+        reset_value: '0'
+        width: 1
+    - M4_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 13
+        reset_value: '0'
+        width: 1
+    - LCD_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 16
+        reset_value: '0'
+        width: 1
+    - USB0_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 17
+        reset_value: '0'
+        width: 1
+    - USB1_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 18
+        reset_value: '0'
+        width: 1
+    - DMA_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 19
+        reset_value: '0'
+        width: 1
+    - SDIO_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 20
+        reset_value: '0'
+        width: 1
+    - EMC_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 21
+        reset_value: '0'
+        width: 1
+    - ETHERNET_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 22
+        reset_value: '0'
+        width: 1
+    - FLASHA_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 25
+        reset_value: '0'
+        width: 1
+    - EEPROM_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 27
+        reset_value: '0'
+        width: 1
+    - GPIO_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 28
+        reset_value: '0'
+        width: 1
+    - FLASHB_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 29
+        reset_value: '0'
+        width: 1
+- RESET_CTRL1:
+    fields: !!omap
+    - TIMER0_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - TIMER1_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - TIMER2_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - TIMER3_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - RTIMER_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - SCT_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - MOTOCONPWM_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - QEI_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - ADC0_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 8
+        reset_value: '0'
+        width: 1
+    - ADC1_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 9
+        reset_value: '0'
+        width: 1
+    - DAC_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 10
+        reset_value: '0'
+        width: 1
+    - UART0_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 12
+        reset_value: '0'
+        width: 1
+    - UART1_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 13
+        reset_value: '0'
+        width: 1
+    - UART2_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 14
+        reset_value: '0'
+        width: 1
+    - UART3_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 15
+        reset_value: '0'
+        width: 1
+    - I2C0_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 16
+        reset_value: '0'
+        width: 1
+    - I2C1_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 17
+        reset_value: '0'
+        width: 1
+    - SSP0_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 18
+        reset_value: '0'
+        width: 1
+    - SSP1_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 19
+        reset_value: '0'
+        width: 1
+    - I2S_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 20
+        reset_value: '0'
+        width: 1
+    - SPIFI_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 21
+        reset_value: '0'
+        width: 1
+    - CAN1_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 22
+        reset_value: '0'
+        width: 1
+    - CAN0_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 23
+        reset_value: '0'
+        width: 1
+    - M0APP_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 24
+        reset_value: '1'
+        width: 1
+    - SGPIO_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 25
+        reset_value: '0'
+        width: 1
+    - SPI_RST:
+        access: w
+        description: Writing a one activates the reset
+        lsb: 26
+        reset_value: '0'
+        width: 1
+- RESET_STATUS0:
+    fields: !!omap
+    - CORE_RST:
+        access: rw
+        description: Status of the CORE_RST reset generator output
+        lsb: 0
+        reset_value: '0x0'
+        width: 2
+    - PERIPH_RST:
+        access: rw
+        description: Status of the PERIPH_RST reset generator output
+        lsb: 2
+        reset_value: '0x0'
+        width: 2
+    - MASTER_RST:
+        access: rw
+        description: Status of the MASTER_RST reset generator output
+        lsb: 4
+        reset_value: '0x1'
+        width: 2
+    - WWDT_RST:
+        access: rw
+        description: Status of the WWDT_RST reset generator output
+        lsb: 8
+        reset_value: '0x0'
+        width: 2
+    - CREG_RST:
+        access: rw
+        description: Status of the CREG_RST reset generator output
+        lsb: 10
+        reset_value: '0x0'
+        width: 2
+    - BUS_RST:
+        access: rw
+        description: Status of the BUS_RST reset generator output
+        lsb: 16
+        reset_value: '0x1'
+        width: 2
+    - SCU_RST:
+        access: rw
+        description: Status of the SCU_RST reset generator output
+        lsb: 18
+        reset_value: '0x1'
+        width: 2
+    - M4_RST:
+        access: rw
+        description: Status of the M4_RST reset generator output
+        lsb: 26
+        reset_value: '0x1'
+        width: 2
+- RESET_STATUS1:
+    fields: !!omap
+    - LCD_RST:
+        access: rw
+        description: Status of the LCD_RST reset generator output
+        lsb: 0
+        reset_value: '0x1'
+        width: 2
+    - USB0_RST:
+        access: rw
+        description: Status of the USB0_RST reset generator output
+        lsb: 2
+        reset_value: '0x1'
+        width: 2
+    - USB1_RST:
+        access: rw
+        description: Status of the USB1_RST reset generator output
+        lsb: 4
+        reset_value: '0x1'
+        width: 2
+    - DMA_RST:
+        access: rw
+        description: Status of the DMA_RST reset generator output
+        lsb: 6
+        reset_value: '0x1'
+        width: 2
+    - SDIO_RST:
+        access: rw
+        description: Status of the SDIO_RST reset generator output
+        lsb: 8
+        reset_value: '0x1'
+        width: 2
+    - EMC_RST:
+        access: rw
+        description: Status of the EMC_RST reset generator output
+        lsb: 10
+        reset_value: '0x1'
+        width: 2
+    - ETHERNET_RST:
+        access: rw
+        description: Status of the ETHERNET_RST reset generator output
+        lsb: 12
+        reset_value: '0x1'
+        width: 2
+    - FLASHA_RST:
+        access: ''
+        description: Status of the FLASHA_RST reset generator output
+        lsb: 18
+        reset_value: '0x1'
+        width: 2
+    - EEPROM_RST:
+        access: ''
+        description: Status of the EEPROM_RST reset generator output
+        lsb: 22
+        reset_value: '0x1'
+        width: 2
+    - GPIO_RST:
+        access: rw
+        description: Status of the GPIO_RST reset generator output
+        lsb: 24
+        reset_value: '0x1'
+        width: 2
+    - FLASHB_RST:
+        access: rw
+        description: Status of the FLASHB_RST reset generator output
+        lsb: 26
+        reset_value: '0x1'
+        width: 2
+- RESET_STATUS2:
+    fields: !!omap
+    - TIMER0_RST:
+        access: rw
+        description: Status of the TIMER0_RST reset generator output
+        lsb: 0
+        reset_value: '0x1'
+        width: 2
+    - TIMER1_RST:
+        access: rw
+        description: Status of the TIMER1_RST reset generator output
+        lsb: 2
+        reset_value: '0x1'
+        width: 2
+    - TIMER2_RST:
+        access: rw
+        description: Status of the TIMER2_RST reset generator output
+        lsb: 4
+        reset_value: '0x1'
+        width: 2
+    - TIMER3_RST:
+        access: rw
+        description: Status of the TIMER3_RST reset generator output
+        lsb: 6
+        reset_value: '0x1'
+        width: 2
+    - RITIMER_RST:
+        access: rw
+        description: Status of the RITIMER_RST reset generator output
+        lsb: 8
+        reset_value: '0x1'
+        width: 2
+    - SCT_RST:
+        access: rw
+        description: Status of the SCT_RST reset generator output
+        lsb: 10
+        reset_value: '0x1'
+        width: 2
+    - MOTOCONPWM_RST:
+        access: rw
+        description: Status of the MOTOCONPWM_RST reset generator output
+        lsb: 12
+        reset_value: '0x1'
+        width: 2
+    - QEI_RST:
+        access: rw
+        description: Status of the QEI_RST reset generator output
+        lsb: 14
+        reset_value: '0x1'
+        width: 2
+    - ADC0_RST:
+        access: rw
+        description: Status of the ADC0_RST reset generator output
+        lsb: 16
+        reset_value: '0x1'
+        width: 2
+    - ADC1_RST:
+        access: rw
+        description: Status of the ADC1_RST reset generator output
+        lsb: 18
+        reset_value: '0x1'
+        width: 2
+    - DAC_RST:
+        access: rw
+        description: Status of the DAC_RST reset generator output
+        lsb: 20
+        reset_value: '0x1'
+        width: 2
+    - UART0_RST:
+        access: rw
+        description: Status of the UART0_RST reset generator output
+        lsb: 24
+        reset_value: '0x1'
+        width: 2
+    - UART1_RST:
+        access: rw
+        description: Status of the UART1_RST reset generator output
+        lsb: 26
+        reset_value: '0x1'
+        width: 2
+    - UART2_RST:
+        access: rw
+        description: Status of the UART2_RST reset generator output
+        lsb: 28
+        reset_value: '0x1'
+        width: 2
+    - UART3_RST:
+        access: rw
+        description: Status of the UART3_RST reset generator output
+        lsb: 30
+        reset_value: '0x1'
+        width: 2
+- RESET_STATUS3:
+    fields: !!omap
+    - I2C0_RST:
+        access: rw
+        description: Status of the I2C0_RST reset generator output
+        lsb: 0
+        reset_value: '0x1'
+        width: 2
+    - I2C1_RST:
+        access: rw
+        description: Status of the I2C1_RST reset generator output
+        lsb: 2
+        reset_value: '0x1'
+        width: 2
+    - SSP0_RST:
+        access: rw
+        description: Status of the SSP0_RST reset generator output
+        lsb: 4
+        reset_value: '0x1'
+        width: 2
+    - SSP1_RST:
+        access: rw
+        description: Status of the SSP1_RST reset generator output
+        lsb: 6
+        reset_value: '0x1'
+        width: 2
+    - I2S_RST:
+        access: rw
+        description: Status of the I2S_RST reset generator output
+        lsb: 8
+        reset_value: '0x1'
+        width: 2
+    - SPIFI_RST:
+        access: rw
+        description: Status of the SPIFI_RST reset generator output
+        lsb: 10
+        reset_value: '0x1'
+        width: 2
+    - CAN1_RST:
+        access: rw
+        description: Status of the CAN1_RST reset generator output
+        lsb: 12
+        reset_value: '0x1'
+        width: 2
+    - CAN0_RST:
+        access: rw
+        description: Status of the CAN0_RST reset generator output
+        lsb: 14
+        reset_value: '0x1'
+        width: 2
+    - M0APP_RST:
+        access: rw
+        description: Status of the M0APP_RST reset generator output
+        lsb: 16
+        reset_value: '0x3'
+        width: 2
+    - SGPIO_RST:
+        access: rw
+        description: Status of the SGPIO_RST reset generator output
+        lsb: 18
+        reset_value: '0x1'
+        width: 2
+    - SPI_RST:
+        access: rw
+        description: Status of the SPI_RST reset generator output
+        lsb: 20
+        reset_value: '0x1'
+        width: 2
+- RESET_ACTIVE_STATUS0:
+    fields: !!omap
+    - CORE_RST:
+        access: r
+        description: Current status of the CORE_RST
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - PERIPH_RST:
+        access: r
+        description: Current status of the PERIPH_RST
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - MASTER_RST:
+        access: r
+        description: Current status of the MASTER_RST
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - WWDT_RST:
+        access: r
+        description: Current status of the WWDT_RST
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - CREG_RST:
+        access: r
+        description: Current status of the CREG_RST
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - BUS_RST:
+        access: r
+        description: Current status of the BUS_RST
+        lsb: 8
+        reset_value: '0'
+        width: 1
+    - SCU_RST:
+        access: r
+        description: Current status of the SCU_RST
+        lsb: 9
+        reset_value: '0'
+        width: 1
+    - M4_RST:
+        access: r
+        description: Current status of the M4_RST
+        lsb: 13
+        reset_value: '0'
+        width: 1
+    - LCD_RST:
+        access: r
+        description: Current status of the LCD_RST
+        lsb: 16
+        reset_value: '0'
+        width: 1
+    - USB0_RST:
+        access: r
+        description: Current status of the USB0_RST
+        lsb: 17
+        reset_value: '0'
+        width: 1
+    - USB1_RST:
+        access: r
+        description: Current status of the USB1_RST
+        lsb: 18
+        reset_value: '0'
+        width: 1
+    - DMA_RST:
+        access: r
+        description: Current status of the DMA_RST
+        lsb: 19
+        reset_value: '0'
+        width: 1
+    - SDIO_RST:
+        access: r
+        description: Current status of the SDIO_RST
+        lsb: 20
+        reset_value: '0'
+        width: 1
+    - EMC_RST:
+        access: r
+        description: Current status of the EMC_RST
+        lsb: 21
+        reset_value: '0'
+        width: 1
+    - ETHERNET_RST:
+        access: r
+        description: Current status of the ETHERNET_RST
+        lsb: 22
+        reset_value: '0'
+        width: 1
+    - FLASHA_RST:
+        access: r
+        description: Current status of the FLASHA_RST
+        lsb: 25
+        reset_value: '0'
+        width: 1
+    - EEPROM_RST:
+        access: r
+        description: Current status of the EEPROM_RST
+        lsb: 27
+        reset_value: '0'
+        width: 1
+    - GPIO_RST:
+        access: r
+        description: Current status of the GPIO_RST
+        lsb: 28
+        reset_value: '0'
+        width: 1
+    - FLASHB_RST:
+        access: r
+        description: Current status of the FLASHB_RST
+        lsb: 29
+        reset_value: '0'
+        width: 1
+- RESET_ACTIVE_STATUS1:
+    fields: !!omap
+    - TIMER0_RST:
+        access: r
+        description: Current status of the TIMER0_RST
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - TIMER1_RST:
+        access: r
+        description: Current status of the TIMER1_RST
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - TIMER2_RST:
+        access: r
+        description: Current status of the TIMER2_RST
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - TIMER3_RST:
+        access: r
+        description: Current status of the TIMER3_RST
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - RITIMER_RST:
+        access: r
+        description: Current status of the RITIMER_RST
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - SCT_RST:
+        access: r
+        description: Current status of the SCT_RST
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - MOTOCONPWM_RST:
+        access: r
+        description: Current status of the MOTOCONPWM_RST
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - QEI_RST:
+        access: r
+        description: Current status of the QEI_RST
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - ADC0_RST:
+        access: r
+        description: Current status of the ADC0_RST
+        lsb: 8
+        reset_value: '0'
+        width: 1
+    - ADC1_RST:
+        access: r
+        description: Current status of the ADC1_RST
+        lsb: 9
+        reset_value: '0'
+        width: 1
+    - DAC_RST:
+        access: r
+        description: Current status of the DAC_RST
+        lsb: 10
+        reset_value: '0'
+        width: 1
+    - UART0_RST:
+        access: r
+        description: Current status of the UART0_RST
+        lsb: 12
+        reset_value: '0'
+        width: 1
+    - UART1_RST:
+        access: r
+        description: Current status of the UART1_RST
+        lsb: 13
+        reset_value: '0'
+        width: 1
+    - UART2_RST:
+        access: r
+        description: Current status of the UART2_RST
+        lsb: 14
+        reset_value: '0'
+        width: 1
+    - UART3_RST:
+        access: r
+        description: Current status of the UART3_RST
+        lsb: 15
+        reset_value: '0'
+        width: 1
+    - I2C0_RST:
+        access: r
+        description: Current status of the I2C0_RST
+        lsb: 16
+        reset_value: '0'
+        width: 1
+    - I2C1_RST:
+        access: r
+        description: Current status of the I2C1_RST
+        lsb: 17
+        reset_value: '0'
+        width: 1
+    - SSP0_RST:
+        access: r
+        description: Current status of the SSP0_RST
+        lsb: 18
+        reset_value: '0'
+        width: 1
+    - SSP1_RST:
+        access: r
+        description: Current status of the SSP1_RST
+        lsb: 19
+        reset_value: '0'
+        width: 1
+    - I2S_RST:
+        access: r
+        description: Current status of the I2S_RST
+        lsb: 20
+        reset_value: '0'
+        width: 1
+    - SPIFI_RST:
+        access: r
+        description: Current status of the SPIFI_RST
+        lsb: 21
+        reset_value: '0'
+        width: 1
+    - CAN1_RST:
+        access: r
+        description: Current status of the CAN1_RST
+        lsb: 22
+        reset_value: '0'
+        width: 1
+    - CAN0_RST:
+        access: r
+        description: Current status of the CAN0_RST
+        lsb: 23
+        reset_value: '0'
+        width: 1
+    - M0APP_RST:
+        access: r
+        description: Current status of the M0APP_RST
+        lsb: 24
+        reset_value: '0'
+        width: 1
+    - SGPIO_RST:
+        access: r
+        description: Current status of the SGPIO_RST
+        lsb: 25
+        reset_value: '0'
+        width: 1
+    - SPI_RST:
+        access: r
+        description: Current status of the SPI_RST
+        lsb: 26
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT0:
+    fields: !!omap
+    - EXT_RESET:
+        access: rw
+        description: Reset activated by external reset from reset pin
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - BOD_RESET:
+        access: rw
+        description: Reset activated by BOD reset
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - WWDT_RESET:
+        access: rw
+        description: Reset activated by WWDT time-out
+        lsb: 5
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT1:
+    fields: !!omap
+    - CORE_RESET:
+        access: rw
+        description: Reset activated by CORE_RST output
+        lsb: 1
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT2:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT4:
+    fields: !!omap
+    - CORE_RESET:
+        access: rw
+        description: Reset activated by CORE_RST output
+        lsb: 1
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT5:
+    fields: !!omap
+    - CORE_RESET:
+        access: rw
+        description: Reset activated by CORE_RST output
+        lsb: 1
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT8:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT9:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT13:
+    fields: !!omap
+    - MASTER_RESET:
+        access: rw
+        description: Reset activated by MASTER_RST output
+        lsb: 3
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT16:
+    fields: !!omap
+    - MASTER_RESET:
+        access: rw
+        description: Reset activated by MASTER_RST output
+        lsb: 3
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT17:
+    fields: !!omap
+    - MASTER_RESET:
+        access: rw
+        description: Reset activated by MASTER_RST output
+        lsb: 3
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT18:
+    fields: !!omap
+    - MASTER_RESET:
+        access: rw
+        description: Reset activated by MASTER_RST output
+        lsb: 3
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT19:
+    fields: !!omap
+    - MASTER_RESET:
+        access: rw
+        description: Reset activated by MASTER_RST output
+        lsb: 3
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT20:
+    fields: !!omap
+    - MASTER_RESET:
+        access: rw
+        description: Reset activated by MASTER_RST output
+        lsb: 3
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT21:
+    fields: !!omap
+    - MASTER_RESET:
+        access: rw
+        description: Reset activated by MASTER_RST output
+        lsb: 3
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT22:
+    fields: !!omap
+    - MASTER_RESET:
+        access: rw
+        description: Reset activated by MASTER_RST output
+        lsb: 3
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT25:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT27:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT28:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT29:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT32:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT33:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT34:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT35:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT36:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT37:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT38:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT39:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT40:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT41:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT42:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT44:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT45:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT46:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT47:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT48:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT49:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT50:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT51:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT52:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT53:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT54:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT55:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT56:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: ''
+        width: 1
+- RESET_EXT_STAT57:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
+- RESET_EXT_STAT58:
+    fields: !!omap
+    - PERIPHERAL_RESET:
+        access: rw
+        description: Reset activated by PERIPHERAL_RST output
+        lsb: 2
+        reset_value: '0'
+        width: 1
diff --git a/libopencm3/scripts/data/lpc43xx/ritimer.yaml b/libopencm3/scripts/data/lpc43xx/ritimer.yaml
new file mode 100644
index 0000000..9c4da5c
--- /dev/null
+++ b/libopencm3/scripts/data/lpc43xx/ritimer.yaml
@@ -0,0 +1,51 @@
+!!omap
+- RITIMER_COMPVAL:
+    fields: !!omap
+    - RICOMP:
+        access: rw
+        description: Compare register
+        lsb: 0
+        reset_value: '0xFFFFFFFF'
+        width: 32
+- RITIMER_MASK:
+    fields: !!omap
+    - RIMASK:
+        access: rw
+        description: Mask register
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- RITIMER_CTRL:
+    fields: !!omap
+    - RITINT:
+        access: rw
+        description: Interrupt flag
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - RITENCLR:
+        access: rw
+        description: Timer enable clear
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - RITENBR:
+        access: rw
+        description: Timer enable for debug
+        lsb: 2
+        reset_value: '1'
+        width: 1
+    - RITEN:
+        access: rw
+        description: Timer enable
+        lsb: 3
+        reset_value: '1'
+        width: 1
+- RITIMER_COUNTER:
+    fields: !!omap
+    - RICOUNTER:
+        access: rw
+        description: 32-bit up counter
+        lsb: 0
+        reset_value: '0'
+        width: 32
diff --git a/libopencm3/scripts/data/lpc43xx/scu.yaml b/libopencm3/scripts/data/lpc43xx/scu.yaml
new file mode 100644
index 0000000..447ce24
--- /dev/null
+++ b/libopencm3/scripts/data/lpc43xx/scu.yaml
@@ -0,0 +1,7063 @@
+!!omap
+- SCU_SFSP0_0:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP0_1:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP1_0:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP1_1:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP1_2:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP1_3:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP1_4:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP1_5:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP1_6:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP1_7:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP1_8:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP1_9:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP1_10:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP1_11:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP1_12:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP1_13:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP1_14:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP1_15:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP1_16:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP1_18:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP1_19:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP1_20:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP2_0:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP2_1:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP2_2:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP2_6:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP2_7:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP2_8:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP2_9:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP2_10:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP2_11:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP2_12:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP2_13:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP3_0:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP3_1:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP3_2:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP3_4:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP3_5:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP3_6:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP3_7:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP3_8:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP4_0:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP4_1:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP4_2:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP4_3:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP4_4:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP4_5:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP4_6:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP4_7:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP4_8:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP4_9:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP4_10:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP5_0:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP5_1:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP5_2:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP5_3:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP5_4:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP5_5:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP5_6:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP5_7:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP6_0:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP6_1:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP6_2:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP6_3:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP6_4:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP6_5:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP6_6:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP6_7:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP6_8:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP6_9:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP6_10:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP6_11:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP6_12:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP7_0:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP7_1:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP7_2:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP7_3:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP7_4:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP7_5:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP7_6:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP7_7:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP8_3:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP8_4:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP8_5:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP8_6:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP8_7:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP8_8:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP9_0:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP9_1:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP9_2:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP9_3:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP9_4:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP9_5:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP9_6:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPA_0:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPA_4:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPB_0:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPB_1:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPB_2:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPB_3:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPB_4:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPB_5:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPB_6:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPC_0:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPC_1:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPC_2:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPC_3:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPC_4:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPC_5:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPC_6:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPC_7:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPC_8:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPC_9:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPC_10:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPC_11:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPC_12:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPC_13:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPC_14:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPD_0:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPD_1:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPD_2:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPD_3:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPD_4:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPD_5:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPD_6:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPD_7:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPD_8:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPD_9:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPD_10:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPD_11:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPD_12:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPD_13:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPD_14:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPD_15:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPD_16:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPE_0:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPE_1:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPE_2:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPE_3:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPE_4:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPE_5:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPE_6:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPE_7:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPE_8:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPE_9:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPE_10:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPE_11:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPE_12:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPE_13:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPE_14:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPE_15:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPF_0:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPF_1:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPF_2:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPF_3:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPF_4:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPF_5:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPF_6:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPF_7:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPF_8:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPF_9:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPF_10:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSPF_11:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSP1_17:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - EHD:
+        access: rw
+        description: Select drive strength
+        lsb: 8
+        reset_value: '0'
+        width: 2
+- SCU_SFSP2_3:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - EHD:
+        access: rw
+        description: Select drive strength
+        lsb: 8
+        reset_value: '0'
+        width: 2
+- SCU_SFSP2_4:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - EHD:
+        access: rw
+        description: Select drive strength
+        lsb: 8
+        reset_value: '0'
+        width: 2
+- SCU_SFSP2_5:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - EHD:
+        access: rw
+        description: Select drive strength
+        lsb: 8
+        reset_value: '0'
+        width: 2
+- SCU_SFSP8_0:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - EHD:
+        access: rw
+        description: Select drive strength
+        lsb: 8
+        reset_value: '0'
+        width: 2
+- SCU_SFSP8_1:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - EHD:
+        access: rw
+        description: Select drive strength
+        lsb: 8
+        reset_value: '0'
+        width: 2
+- SCU_SFSP8_2:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - EHD:
+        access: rw
+        description: Select drive strength
+        lsb: 8
+        reset_value: '0'
+        width: 2
+- SCU_SFSPA_1:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - EHD:
+        access: rw
+        description: Select drive strength
+        lsb: 8
+        reset_value: '0'
+        width: 2
+- SCU_SFSPA_2:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - EHD:
+        access: rw
+        description: Select drive strength
+        lsb: 8
+        reset_value: '0'
+        width: 2
+- SCU_SFSPA_3:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - EHD:
+        access: rw
+        description: Select drive strength
+        lsb: 8
+        reset_value: '0'
+        width: 2
+- SCU_SFSP3_3:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSCLK0:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSCLK1:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSCLK2:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSCLK3:
+    fields: !!omap
+    - MODE:
+        access: rw
+        description: Select pin function
+        lsb: 0
+        reset_value: '0'
+        width: 3
+    - EPD:
+        access: rw
+        description: Enable pull-down resistor at pad
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - EPUN:
+        access: rw
+        description: Disable pull-up resistor at pad
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - EHS:
+        access: rw
+        description: Select Slew rate
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - EZI:
+        access: rw
+        description: Input buffer enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ZIF:
+        access: rw
+        description: Input glitch filter
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_SFSUSB:
+    fields: !!omap
+    - USB_AIM:
+        access: rw
+        description: Differential data input AIP/AIM
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - USB_ESEA:
+        access: rw
+        description: Control signal for differential input or single input
+        lsb: 1
+        reset_value: '1'
+        width: 1
+    - USB_EPD:
+        access: rw
+        description: Enable pull-down connect
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - USB_EPWR:
+        access: rw
+        description: Power mode
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - USB_VBUS:
+        access: rw
+        description: Enable the vbus_valid signal
+        lsb: 5
+        reset_value: '0'
+        width: 1
+- SCU_SFSI2C0:
+    fields: !!omap
+    - SCL_EFP:
+        access: rw
+        description: Select input glitch filter time constant for the SCL pin
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - SCL_EHD:
+        access: rw
+        description: Select I2C mode for the SCL pin
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - SCL_EZI:
+        access: rw
+        description: Enable the input receiver for the SCL pin
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SCL_ZIF:
+        access: rw
+        description: Enable or disable input glitch filter for the SCL pin
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - SDA_EFP:
+        access: rw
+        description: Select input glitch filter time constant for the SDA pin
+        lsb: 8
+        reset_value: '0'
+        width: 1
+    - SDA_EHD:
+        access: rw
+        description: Select I2C mode for the SDA pin
+        lsb: 10
+        reset_value: '0'
+        width: 1
+    - SDA_EZI:
+        access: rw
+        description: Enable the input receiver for the SDA pin
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - SDA_ZIF:
+        access: rw
+        description: Enable or disable input glitch filter for the SDA pin
+        lsb: 15
+        reset_value: '0'
+        width: 1
+- SCU_ENAIO0:
+    fields: !!omap
+    - ADC0_0:
+        access: rw
+        description: Select ADC0_0
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - ADC0_1:
+        access: rw
+        description: Select ADC0_1
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - ADC0_2:
+        access: rw
+        description: Select ADC0_2
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - ADC0_3:
+        access: rw
+        description: Select ADC0_3
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - ADC0_4:
+        access: rw
+        description: Select ADC0_4
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - ADC0_5:
+        access: rw
+        description: Select ADC0_5
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - ADC0_6:
+        access: rw
+        description: Select ADC0_6
+        lsb: 6
+        reset_value: '0'
+        width: 1
+- SCU_ENAIO1:
+    fields: !!omap
+    - ADC1_0:
+        access: rw
+        description: Select ADC1_0
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - ADC1_1:
+        access: rw
+        description: Select ADC1_1
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - ADC1_2:
+        access: rw
+        description: Select ADC1_2
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - ADC1_3:
+        access: rw
+        description: Select ADC1_3
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - ADC1_4:
+        access: rw
+        description: Select ADC1_4
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - ADC1_5:
+        access: rw
+        description: Select ADC1_5
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - ADC1_6:
+        access: rw
+        description: Select ADC1_6
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ADC1_7:
+        access: rw
+        description: Select ADC1_7
+        lsb: 7
+        reset_value: '0'
+        width: 1
+- SCU_ENAIO2:
+    fields: !!omap
+    - DAC:
+        access: rw
+        description: Select DAC
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - BG:
+        access: rw
+        description: Select band gap output
+        lsb: 4
+        reset_value: '0'
+        width: 1
+- SCU_EMCDELAYCLK:
+    fields: !!omap
+    - CLK_DELAY:
+        access: rw
+        description: EMC_CLKn SDRAM clock output delay
+        lsb: 0
+        reset_value: '0'
+        width: 16
+- SCU_PINTSEL0:
+    fields: !!omap
+    - INTPIN0:
+        access: ''
+        description: pin number for interrupt 0 source
+        lsb: 0
+        reset_value: '0'
+        width: 5
+    - PORTSEL0:
+        access: ''
+        description: port for interrupt 0 source
+        lsb: 5
+        reset_value: '0'
+        width: 3
+    - INTPIN1:
+        access: ''
+        description: pin number for interrupt 1 source
+        lsb: 8
+        reset_value: '0'
+        width: 5
+    - PORTSEL1:
+        access: ''
+        description: port for interrupt 1 source
+        lsb: 13
+        reset_value: '0'
+        width: 3
+    - INTPIN2:
+        access: ''
+        description: pin number for interrupt 2 source
+        lsb: 16
+        reset_value: '0'
+        width: 5
+    - PORTSEL2:
+        access: ''
+        description: port for interrupt 2 source
+        lsb: 21
+        reset_value: '0'
+        width: 3
+    - INTPIN3:
+        access: ''
+        description: pin number for interrupt 3 source
+        lsb: 24
+        reset_value: '0'
+        width: 5
+    - PORTSEL3:
+        access: ''
+        description: port for interrupt 3 source
+        lsb: 29
+        reset_value: '0'
+        width: 3
+- SCU_PINTSEL1:
+    fields: !!omap
+    - INTPIN4:
+        access: ''
+        description: pin number for interrupt 4 source
+        lsb: 0
+        reset_value: '0'
+        width: 5
+    - PORTSEL4:
+        access: ''
+        description: port for interrupt 4 source
+        lsb: 5
+        reset_value: '0'
+        width: 3
+    - INTPIN5:
+        access: ''
+        description: pin number for interrupt 5 source
+        lsb: 8
+        reset_value: '0'
+        width: 5
+    - PORTSEL5:
+        access: ''
+        description: port for interrupt 5 source
+        lsb: 13
+        reset_value: '0'
+        width: 3
+    - INTPIN6:
+        access: ''
+        description: pin number for interrupt 6 source
+        lsb: 16
+        reset_value: '0'
+        width: 5
+    - PORTSEL6:
+        access: ''
+        description: port for interrupt 6 source
+        lsb: 21
+        reset_value: '0'
+        width: 3
+    - INTPIN7:
+        access: ''
+        description: pin number for interrupt 7 source
+        lsb: 24
+        reset_value: '0'
+        width: 5
+    - PORTSEL7:
+        access: ''
+        description: port for interrupt 7 source
+        lsb: 29
+        reset_value: '0'
+        width: 3
diff --git a/libopencm3/scripts/data/lpc43xx/sgpio.yaml b/libopencm3/scripts/data/lpc43xx/sgpio.yaml
new file mode 100644
index 0000000..fab91b6
--- /dev/null
+++ b/libopencm3/scripts/data/lpc43xx/sgpio.yaml
@@ -0,0 +1,1953 @@
+!!omap
+- SGPIO_OUT_MUX_CFG0:
+    fields: !!omap
+    - P_OUT_CFG:
+        access: rw
+        description: Output control of output SGPIOn
+        lsb: 0
+        reset_value: '0'
+        width: 4
+    - P_OE_CFG:
+        access: rw
+        description: Output enable source
+        lsb: 4
+        reset_value: '0'
+        width: 3
+- SGPIO_OUT_MUX_CFG1:
+    fields: !!omap
+    - P_OUT_CFG:
+        access: rw
+        description: Output control of output SGPIOn
+        lsb: 0
+        reset_value: '0'
+        width: 4
+    - P_OE_CFG:
+        access: rw
+        description: Output enable source
+        lsb: 4
+        reset_value: '0'
+        width: 3
+- SGPIO_OUT_MUX_CFG2:
+    fields: !!omap
+    - P_OUT_CFG:
+        access: rw
+        description: Output control of output SGPIOn
+        lsb: 0
+        reset_value: '0'
+        width: 4
+    - P_OE_CFG:
+        access: rw
+        description: Output enable source
+        lsb: 4
+        reset_value: '0'
+        width: 3
+- SGPIO_OUT_MUX_CFG3:
+    fields: !!omap
+    - P_OUT_CFG:
+        access: rw
+        description: Output control of output SGPIOn
+        lsb: 0
+        reset_value: '0'
+        width: 4
+    - P_OE_CFG:
+        access: rw
+        description: Output enable source
+        lsb: 4
+        reset_value: '0'
+        width: 3
+- SGPIO_OUT_MUX_CFG4:
+    fields: !!omap
+    - P_OUT_CFG:
+        access: rw
+        description: Output control of output SGPIOn
+        lsb: 0
+        reset_value: '0'
+        width: 4
+    - P_OE_CFG:
+        access: rw
+        description: Output enable source
+        lsb: 4
+        reset_value: '0'
+        width: 3
+- SGPIO_OUT_MUX_CFG5:
+    fields: !!omap
+    - P_OUT_CFG:
+        access: rw
+        description: Output control of output SGPIOn
+        lsb: 0
+        reset_value: '0'
+        width: 4
+    - P_OE_CFG:
+        access: rw
+        description: Output enable source
+        lsb: 4
+        reset_value: '0'
+        width: 3
+- SGPIO_OUT_MUX_CFG6:
+    fields: !!omap
+    - P_OUT_CFG:
+        access: rw
+        description: Output control of output SGPIOn
+        lsb: 0
+        reset_value: '0'
+        width: 4
+    - P_OE_CFG:
+        access: rw
+        description: Output enable source
+        lsb: 4
+        reset_value: '0'
+        width: 3
+- SGPIO_OUT_MUX_CFG7:
+    fields: !!omap
+    - P_OUT_CFG:
+        access: rw
+        description: Output control of output SGPIOn
+        lsb: 0
+        reset_value: '0'
+        width: 4
+    - P_OE_CFG:
+        access: rw
+        description: Output enable source
+        lsb: 4
+        reset_value: '0'
+        width: 3
+- SGPIO_OUT_MUX_CFG8:
+    fields: !!omap
+    - P_OUT_CFG:
+        access: rw
+        description: Output control of output SGPIOn
+        lsb: 0
+        reset_value: '0'
+        width: 4
+    - P_OE_CFG:
+        access: rw
+        description: Output enable source
+        lsb: 4
+        reset_value: '0'
+        width: 3
+- SGPIO_OUT_MUX_CFG9:
+    fields: !!omap
+    - P_OUT_CFG:
+        access: rw
+        description: Output control of output SGPIOn
+        lsb: 0
+        reset_value: '0'
+        width: 4
+    - P_OE_CFG:
+        access: rw
+        description: Output enable source
+        lsb: 4
+        reset_value: '0'
+        width: 3
+- SGPIO_OUT_MUX_CFG10:
+    fields: !!omap
+    - P_OUT_CFG:
+        access: rw
+        description: Output control of output SGPIOn
+        lsb: 0
+        reset_value: '0'
+        width: 4
+    - P_OE_CFG:
+        access: rw
+        description: Output enable source
+        lsb: 4
+        reset_value: '0'
+        width: 3
+- SGPIO_OUT_MUX_CFG11:
+    fields: !!omap
+    - P_OUT_CFG:
+        access: rw
+        description: Output control of output SGPIOn
+        lsb: 0
+        reset_value: '0'
+        width: 4
+    - P_OE_CFG:
+        access: rw
+        description: Output enable source
+        lsb: 4
+        reset_value: '0'
+        width: 3
+- SGPIO_OUT_MUX_CFG12:
+    fields: !!omap
+    - P_OUT_CFG:
+        access: rw
+        description: Output control of output SGPIOn
+        lsb: 0
+        reset_value: '0'
+        width: 4
+    - P_OE_CFG:
+        access: rw
+        description: Output enable source
+        lsb: 4
+        reset_value: '0'
+        width: 3
+- SGPIO_OUT_MUX_CFG13:
+    fields: !!omap
+    - P_OUT_CFG:
+        access: rw
+        description: Output control of output SGPIOn
+        lsb: 0
+        reset_value: '0'
+        width: 4
+    - P_OE_CFG:
+        access: rw
+        description: Output enable source
+        lsb: 4
+        reset_value: '0'
+        width: 3
+- SGPIO_OUT_MUX_CFG14:
+    fields: !!omap
+    - P_OUT_CFG:
+        access: rw
+        description: Output control of output SGPIOn
+        lsb: 0
+        reset_value: '0'
+        width: 4
+    - P_OE_CFG:
+        access: rw
+        description: Output enable source
+        lsb: 4
+        reset_value: '0'
+        width: 3
+- SGPIO_OUT_MUX_CFG15:
+    fields: !!omap
+    - P_OUT_CFG:
+        access: rw
+        description: Output control of output SGPIOn
+        lsb: 0
+        reset_value: '0'
+        width: 4
+    - P_OE_CFG:
+        access: rw
+        description: Output enable source
+        lsb: 4
+        reset_value: '0'
+        width: 3
+- SGPIO_MUX_CFG0:
+    fields: !!omap
+    - EXT_CLK_ENABLE:
+        access: rw
+        description: Select clock signal
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_SOURCE_PIN_MODE:
+        access: rw
+        description: Select source clock pin
+        lsb: 1
+        reset_value: '0'
+        width: 2
+    - CLK_SOURCE_SLICE_MODE:
+        access: rw
+        description: Select clock source slice
+        lsb: 3
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_MODE:
+        access: rw
+        description: Select qualifier mode
+        lsb: 5
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_PIN_MODE:
+        access: rw
+        description: Select qualifier pin
+        lsb: 7
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_SLICE_MODE:
+        access: rw
+        description: Select qualifier slice
+        lsb: 9
+        reset_value: '0'
+        width: 2
+    - CONCAT_ENABLE:
+        access: rw
+        description: Enable concatenation
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CONCAT_ORDER:
+        access: rw
+        description: Select concatenation order
+        lsb: 12
+        reset_value: '0'
+        width: 2
+- SGPIO_MUX_CFG1:
+    fields: !!omap
+    - EXT_CLK_ENABLE:
+        access: rw
+        description: Select clock signal
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_SOURCE_PIN_MODE:
+        access: rw
+        description: Select source clock pin
+        lsb: 1
+        reset_value: '0'
+        width: 2
+    - CLK_SOURCE_SLICE_MODE:
+        access: rw
+        description: Select clock source slice
+        lsb: 3
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_MODE:
+        access: rw
+        description: Select qualifier mode
+        lsb: 5
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_PIN_MODE:
+        access: rw
+        description: Select qualifier pin
+        lsb: 7
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_SLICE_MODE:
+        access: rw
+        description: Select qualifier slice
+        lsb: 9
+        reset_value: '0'
+        width: 2
+    - CONCAT_ENABLE:
+        access: rw
+        description: Enable concatenation
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CONCAT_ORDER:
+        access: rw
+        description: Select concatenation order
+        lsb: 12
+        reset_value: '0'
+        width: 2
+- SGPIO_MUX_CFG2:
+    fields: !!omap
+    - EXT_CLK_ENABLE:
+        access: rw
+        description: Select clock signal
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_SOURCE_PIN_MODE:
+        access: rw
+        description: Select source clock pin
+        lsb: 1
+        reset_value: '0'
+        width: 2
+    - CLK_SOURCE_SLICE_MODE:
+        access: rw
+        description: Select clock source slice
+        lsb: 3
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_MODE:
+        access: rw
+        description: Select qualifier mode
+        lsb: 5
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_PIN_MODE:
+        access: rw
+        description: Select qualifier pin
+        lsb: 7
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_SLICE_MODE:
+        access: rw
+        description: Select qualifier slice
+        lsb: 9
+        reset_value: '0'
+        width: 2
+    - CONCAT_ENABLE:
+        access: rw
+        description: Enable concatenation
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CONCAT_ORDER:
+        access: rw
+        description: Select concatenation order
+        lsb: 12
+        reset_value: '0'
+        width: 2
+- SGPIO_MUX_CFG3:
+    fields: !!omap
+    - EXT_CLK_ENABLE:
+        access: rw
+        description: Select clock signal
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_SOURCE_PIN_MODE:
+        access: rw
+        description: Select source clock pin
+        lsb: 1
+        reset_value: '0'
+        width: 2
+    - CLK_SOURCE_SLICE_MODE:
+        access: rw
+        description: Select clock source slice
+        lsb: 3
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_MODE:
+        access: rw
+        description: Select qualifier mode
+        lsb: 5
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_PIN_MODE:
+        access: rw
+        description: Select qualifier pin
+        lsb: 7
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_SLICE_MODE:
+        access: rw
+        description: Select qualifier slice
+        lsb: 9
+        reset_value: '0'
+        width: 2
+    - CONCAT_ENABLE:
+        access: rw
+        description: Enable concatenation
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CONCAT_ORDER:
+        access: rw
+        description: Select concatenation order
+        lsb: 12
+        reset_value: '0'
+        width: 2
+- SGPIO_MUX_CFG4:
+    fields: !!omap
+    - EXT_CLK_ENABLE:
+        access: rw
+        description: Select clock signal
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_SOURCE_PIN_MODE:
+        access: rw
+        description: Select source clock pin
+        lsb: 1
+        reset_value: '0'
+        width: 2
+    - CLK_SOURCE_SLICE_MODE:
+        access: rw
+        description: Select clock source slice
+        lsb: 3
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_MODE:
+        access: rw
+        description: Select qualifier mode
+        lsb: 5
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_PIN_MODE:
+        access: rw
+        description: Select qualifier pin
+        lsb: 7
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_SLICE_MODE:
+        access: rw
+        description: Select qualifier slice
+        lsb: 9
+        reset_value: '0'
+        width: 2
+    - CONCAT_ENABLE:
+        access: rw
+        description: Enable concatenation
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CONCAT_ORDER:
+        access: rw
+        description: Select concatenation order
+        lsb: 12
+        reset_value: '0'
+        width: 2
+- SGPIO_MUX_CFG5:
+    fields: !!omap
+    - EXT_CLK_ENABLE:
+        access: rw
+        description: Select clock signal
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_SOURCE_PIN_MODE:
+        access: rw
+        description: Select source clock pin
+        lsb: 1
+        reset_value: '0'
+        width: 2
+    - CLK_SOURCE_SLICE_MODE:
+        access: rw
+        description: Select clock source slice
+        lsb: 3
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_MODE:
+        access: rw
+        description: Select qualifier mode
+        lsb: 5
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_PIN_MODE:
+        access: rw
+        description: Select qualifier pin
+        lsb: 7
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_SLICE_MODE:
+        access: rw
+        description: Select qualifier slice
+        lsb: 9
+        reset_value: '0'
+        width: 2
+    - CONCAT_ENABLE:
+        access: rw
+        description: Enable concatenation
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CONCAT_ORDER:
+        access: rw
+        description: Select concatenation order
+        lsb: 12
+        reset_value: '0'
+        width: 2
+- SGPIO_MUX_CFG6:
+    fields: !!omap
+    - EXT_CLK_ENABLE:
+        access: rw
+        description: Select clock signal
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_SOURCE_PIN_MODE:
+        access: rw
+        description: Select source clock pin
+        lsb: 1
+        reset_value: '0'
+        width: 2
+    - CLK_SOURCE_SLICE_MODE:
+        access: rw
+        description: Select clock source slice
+        lsb: 3
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_MODE:
+        access: rw
+        description: Select qualifier mode
+        lsb: 5
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_PIN_MODE:
+        access: rw
+        description: Select qualifier pin
+        lsb: 7
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_SLICE_MODE:
+        access: rw
+        description: Select qualifier slice
+        lsb: 9
+        reset_value: '0'
+        width: 2
+    - CONCAT_ENABLE:
+        access: rw
+        description: Enable concatenation
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CONCAT_ORDER:
+        access: rw
+        description: Select concatenation order
+        lsb: 12
+        reset_value: '0'
+        width: 2
+- SGPIO_MUX_CFG7:
+    fields: !!omap
+    - EXT_CLK_ENABLE:
+        access: rw
+        description: Select clock signal
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_SOURCE_PIN_MODE:
+        access: rw
+        description: Select source clock pin
+        lsb: 1
+        reset_value: '0'
+        width: 2
+    - CLK_SOURCE_SLICE_MODE:
+        access: rw
+        description: Select clock source slice
+        lsb: 3
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_MODE:
+        access: rw
+        description: Select qualifier mode
+        lsb: 5
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_PIN_MODE:
+        access: rw
+        description: Select qualifier pin
+        lsb: 7
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_SLICE_MODE:
+        access: rw
+        description: Select qualifier slice
+        lsb: 9
+        reset_value: '0'
+        width: 2
+    - CONCAT_ENABLE:
+        access: rw
+        description: Enable concatenation
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CONCAT_ORDER:
+        access: rw
+        description: Select concatenation order
+        lsb: 12
+        reset_value: '0'
+        width: 2
+- SGPIO_MUX_CFG8:
+    fields: !!omap
+    - EXT_CLK_ENABLE:
+        access: rw
+        description: Select clock signal
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_SOURCE_PIN_MODE:
+        access: rw
+        description: Select source clock pin
+        lsb: 1
+        reset_value: '0'
+        width: 2
+    - CLK_SOURCE_SLICE_MODE:
+        access: rw
+        description: Select clock source slice
+        lsb: 3
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_MODE:
+        access: rw
+        description: Select qualifier mode
+        lsb: 5
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_PIN_MODE:
+        access: rw
+        description: Select qualifier pin
+        lsb: 7
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_SLICE_MODE:
+        access: rw
+        description: Select qualifier slice
+        lsb: 9
+        reset_value: '0'
+        width: 2
+    - CONCAT_ENABLE:
+        access: rw
+        description: Enable concatenation
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CONCAT_ORDER:
+        access: rw
+        description: Select concatenation order
+        lsb: 12
+        reset_value: '0'
+        width: 2
+- SGPIO_MUX_CFG9:
+    fields: !!omap
+    - EXT_CLK_ENABLE:
+        access: rw
+        description: Select clock signal
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_SOURCE_PIN_MODE:
+        access: rw
+        description: Select source clock pin
+        lsb: 1
+        reset_value: '0'
+        width: 2
+    - CLK_SOURCE_SLICE_MODE:
+        access: rw
+        description: Select clock source slice
+        lsb: 3
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_MODE:
+        access: rw
+        description: Select qualifier mode
+        lsb: 5
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_PIN_MODE:
+        access: rw
+        description: Select qualifier pin
+        lsb: 7
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_SLICE_MODE:
+        access: rw
+        description: Select qualifier slice
+        lsb: 9
+        reset_value: '0'
+        width: 2
+    - CONCAT_ENABLE:
+        access: rw
+        description: Enable concatenation
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CONCAT_ORDER:
+        access: rw
+        description: Select concatenation order
+        lsb: 12
+        reset_value: '0'
+        width: 2
+- SGPIO_MUX_CFG10:
+    fields: !!omap
+    - EXT_CLK_ENABLE:
+        access: rw
+        description: Select clock signal
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_SOURCE_PIN_MODE:
+        access: rw
+        description: Select source clock pin
+        lsb: 1
+        reset_value: '0'
+        width: 2
+    - CLK_SOURCE_SLICE_MODE:
+        access: rw
+        description: Select clock source slice
+        lsb: 3
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_MODE:
+        access: rw
+        description: Select qualifier mode
+        lsb: 5
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_PIN_MODE:
+        access: rw
+        description: Select qualifier pin
+        lsb: 7
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_SLICE_MODE:
+        access: rw
+        description: Select qualifier slice
+        lsb: 9
+        reset_value: '0'
+        width: 2
+    - CONCAT_ENABLE:
+        access: rw
+        description: Enable concatenation
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CONCAT_ORDER:
+        access: rw
+        description: Select concatenation order
+        lsb: 12
+        reset_value: '0'
+        width: 2
+- SGPIO_MUX_CFG11:
+    fields: !!omap
+    - EXT_CLK_ENABLE:
+        access: rw
+        description: Select clock signal
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_SOURCE_PIN_MODE:
+        access: rw
+        description: Select source clock pin
+        lsb: 1
+        reset_value: '0'
+        width: 2
+    - CLK_SOURCE_SLICE_MODE:
+        access: rw
+        description: Select clock source slice
+        lsb: 3
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_MODE:
+        access: rw
+        description: Select qualifier mode
+        lsb: 5
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_PIN_MODE:
+        access: rw
+        description: Select qualifier pin
+        lsb: 7
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_SLICE_MODE:
+        access: rw
+        description: Select qualifier slice
+        lsb: 9
+        reset_value: '0'
+        width: 2
+    - CONCAT_ENABLE:
+        access: rw
+        description: Enable concatenation
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CONCAT_ORDER:
+        access: rw
+        description: Select concatenation order
+        lsb: 12
+        reset_value: '0'
+        width: 2
+- SGPIO_MUX_CFG12:
+    fields: !!omap
+    - EXT_CLK_ENABLE:
+        access: rw
+        description: Select clock signal
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_SOURCE_PIN_MODE:
+        access: rw
+        description: Select source clock pin
+        lsb: 1
+        reset_value: '0'
+        width: 2
+    - CLK_SOURCE_SLICE_MODE:
+        access: rw
+        description: Select clock source slice
+        lsb: 3
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_MODE:
+        access: rw
+        description: Select qualifier mode
+        lsb: 5
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_PIN_MODE:
+        access: rw
+        description: Select qualifier pin
+        lsb: 7
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_SLICE_MODE:
+        access: rw
+        description: Select qualifier slice
+        lsb: 9
+        reset_value: '0'
+        width: 2
+    - CONCAT_ENABLE:
+        access: rw
+        description: Enable concatenation
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CONCAT_ORDER:
+        access: rw
+        description: Select concatenation order
+        lsb: 12
+        reset_value: '0'
+        width: 2
+- SGPIO_MUX_CFG13:
+    fields: !!omap
+    - EXT_CLK_ENABLE:
+        access: rw
+        description: Select clock signal
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_SOURCE_PIN_MODE:
+        access: rw
+        description: Select source clock pin
+        lsb: 1
+        reset_value: '0'
+        width: 2
+    - CLK_SOURCE_SLICE_MODE:
+        access: rw
+        description: Select clock source slice
+        lsb: 3
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_MODE:
+        access: rw
+        description: Select qualifier mode
+        lsb: 5
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_PIN_MODE:
+        access: rw
+        description: Select qualifier pin
+        lsb: 7
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_SLICE_MODE:
+        access: rw
+        description: Select qualifier slice
+        lsb: 9
+        reset_value: '0'
+        width: 2
+    - CONCAT_ENABLE:
+        access: rw
+        description: Enable concatenation
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CONCAT_ORDER:
+        access: rw
+        description: Select concatenation order
+        lsb: 12
+        reset_value: '0'
+        width: 2
+- SGPIO_MUX_CFG14:
+    fields: !!omap
+    - EXT_CLK_ENABLE:
+        access: rw
+        description: Select clock signal
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_SOURCE_PIN_MODE:
+        access: rw
+        description: Select source clock pin
+        lsb: 1
+        reset_value: '0'
+        width: 2
+    - CLK_SOURCE_SLICE_MODE:
+        access: rw
+        description: Select clock source slice
+        lsb: 3
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_MODE:
+        access: rw
+        description: Select qualifier mode
+        lsb: 5
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_PIN_MODE:
+        access: rw
+        description: Select qualifier pin
+        lsb: 7
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_SLICE_MODE:
+        access: rw
+        description: Select qualifier slice
+        lsb: 9
+        reset_value: '0'
+        width: 2
+    - CONCAT_ENABLE:
+        access: rw
+        description: Enable concatenation
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CONCAT_ORDER:
+        access: rw
+        description: Select concatenation order
+        lsb: 12
+        reset_value: '0'
+        width: 2
+- SGPIO_MUX_CFG15:
+    fields: !!omap
+    - EXT_CLK_ENABLE:
+        access: rw
+        description: Select clock signal
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_SOURCE_PIN_MODE:
+        access: rw
+        description: Select source clock pin
+        lsb: 1
+        reset_value: '0'
+        width: 2
+    - CLK_SOURCE_SLICE_MODE:
+        access: rw
+        description: Select clock source slice
+        lsb: 3
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_MODE:
+        access: rw
+        description: Select qualifier mode
+        lsb: 5
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_PIN_MODE:
+        access: rw
+        description: Select qualifier pin
+        lsb: 7
+        reset_value: '0'
+        width: 2
+    - QUALIFIER_SLICE_MODE:
+        access: rw
+        description: Select qualifier slice
+        lsb: 9
+        reset_value: '0'
+        width: 2
+    - CONCAT_ENABLE:
+        access: rw
+        description: Enable concatenation
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - CONCAT_ORDER:
+        access: rw
+        description: Select concatenation order
+        lsb: 12
+        reset_value: '0'
+        width: 2
+- SGPIO_SLICE_MUX_CFG0:
+    fields: !!omap
+    - MATCH_MODE:
+        access: rw
+        description: Match mode
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_CAPTURE_MODE:
+        access: rw
+        description: Capture clock mode
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - CLKGEN_MODE:
+        access: rw
+        description: Clock generation mode
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - INV_OUT_CLK:
+        access: rw
+        description: Invert output clock
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - DATA_CAPTURE_MODE:
+        access: rw
+        description: Condition for input bit match interrupt
+        lsb: 4
+        reset_value: '0'
+        width: 2
+    - PARALLEL_MODE:
+        access: rw
+        description: Parallel mode
+        lsb: 6
+        reset_value: '0'
+        width: 2
+    - INV_QUALIFIER:
+        access: rw
+        description: Inversion qualifier
+        lsb: 8
+        reset_value: '0'
+        width: 1
+- SGPIO_SLICE_MUX_CFG1:
+    fields: !!omap
+    - MATCH_MODE:
+        access: rw
+        description: Match mode
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_CAPTURE_MODE:
+        access: rw
+        description: Capture clock mode
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - CLKGEN_MODE:
+        access: rw
+        description: Clock generation mode
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - INV_OUT_CLK:
+        access: rw
+        description: Invert output clock
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - DATA_CAPTURE_MODE:
+        access: rw
+        description: Condition for input bit match interrupt
+        lsb: 4
+        reset_value: '0'
+        width: 2
+    - PARALLEL_MODE:
+        access: rw
+        description: Parallel mode
+        lsb: 6
+        reset_value: '0'
+        width: 2
+    - INV_QUALIFIER:
+        access: rw
+        description: Inversion qualifier
+        lsb: 8
+        reset_value: '0'
+        width: 1
+- SGPIO_SLICE_MUX_CFG2:
+    fields: !!omap
+    - MATCH_MODE:
+        access: rw
+        description: Match mode
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_CAPTURE_MODE:
+        access: rw
+        description: Capture clock mode
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - CLKGEN_MODE:
+        access: rw
+        description: Clock generation mode
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - INV_OUT_CLK:
+        access: rw
+        description: Invert output clock
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - DATA_CAPTURE_MODE:
+        access: rw
+        description: Condition for input bit match interrupt
+        lsb: 4
+        reset_value: '0'
+        width: 2
+    - PARALLEL_MODE:
+        access: rw
+        description: Parallel mode
+        lsb: 6
+        reset_value: '0'
+        width: 2
+    - INV_QUALIFIER:
+        access: rw
+        description: Inversion qualifier
+        lsb: 8
+        reset_value: '0'
+        width: 1
+- SGPIO_SLICE_MUX_CFG3:
+    fields: !!omap
+    - MATCH_MODE:
+        access: rw
+        description: Match mode
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_CAPTURE_MODE:
+        access: rw
+        description: Capture clock mode
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - CLKGEN_MODE:
+        access: rw
+        description: Clock generation mode
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - INV_OUT_CLK:
+        access: rw
+        description: Invert output clock
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - DATA_CAPTURE_MODE:
+        access: rw
+        description: Condition for input bit match interrupt
+        lsb: 4
+        reset_value: '0'
+        width: 2
+    - PARALLEL_MODE:
+        access: rw
+        description: Parallel mode
+        lsb: 6
+        reset_value: '0'
+        width: 2
+    - INV_QUALIFIER:
+        access: rw
+        description: Inversion qualifier
+        lsb: 8
+        reset_value: '0'
+        width: 1
+- SGPIO_SLICE_MUX_CFG4:
+    fields: !!omap
+    - MATCH_MODE:
+        access: rw
+        description: Match mode
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_CAPTURE_MODE:
+        access: rw
+        description: Capture clock mode
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - CLKGEN_MODE:
+        access: rw
+        description: Clock generation mode
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - INV_OUT_CLK:
+        access: rw
+        description: Invert output clock
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - DATA_CAPTURE_MODE:
+        access: rw
+        description: Condition for input bit match interrupt
+        lsb: 4
+        reset_value: '0'
+        width: 2
+    - PARALLEL_MODE:
+        access: rw
+        description: Parallel mode
+        lsb: 6
+        reset_value: '0'
+        width: 2
+    - INV_QUALIFIER:
+        access: rw
+        description: Inversion qualifier
+        lsb: 8
+        reset_value: '0'
+        width: 1
+- SGPIO_SLICE_MUX_CFG5:
+    fields: !!omap
+    - MATCH_MODE:
+        access: rw
+        description: Match mode
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_CAPTURE_MODE:
+        access: rw
+        description: Capture clock mode
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - CLKGEN_MODE:
+        access: rw
+        description: Clock generation mode
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - INV_OUT_CLK:
+        access: rw
+        description: Invert output clock
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - DATA_CAPTURE_MODE:
+        access: rw
+        description: Condition for input bit match interrupt
+        lsb: 4
+        reset_value: '0'
+        width: 2
+    - PARALLEL_MODE:
+        access: rw
+        description: Parallel mode
+        lsb: 6
+        reset_value: '0'
+        width: 2
+    - INV_QUALIFIER:
+        access: rw
+        description: Inversion qualifier
+        lsb: 8
+        reset_value: '0'
+        width: 1
+- SGPIO_SLICE_MUX_CFG6:
+    fields: !!omap
+    - MATCH_MODE:
+        access: rw
+        description: Match mode
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_CAPTURE_MODE:
+        access: rw
+        description: Capture clock mode
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - CLKGEN_MODE:
+        access: rw
+        description: Clock generation mode
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - INV_OUT_CLK:
+        access: rw
+        description: Invert output clock
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - DATA_CAPTURE_MODE:
+        access: rw
+        description: Condition for input bit match interrupt
+        lsb: 4
+        reset_value: '0'
+        width: 2
+    - PARALLEL_MODE:
+        access: rw
+        description: Parallel mode
+        lsb: 6
+        reset_value: '0'
+        width: 2
+    - INV_QUALIFIER:
+        access: rw
+        description: Inversion qualifier
+        lsb: 8
+        reset_value: '0'
+        width: 1
+- SGPIO_SLICE_MUX_CFG7:
+    fields: !!omap
+    - MATCH_MODE:
+        access: rw
+        description: Match mode
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_CAPTURE_MODE:
+        access: rw
+        description: Capture clock mode
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - CLKGEN_MODE:
+        access: rw
+        description: Clock generation mode
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - INV_OUT_CLK:
+        access: rw
+        description: Invert output clock
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - DATA_CAPTURE_MODE:
+        access: rw
+        description: Condition for input bit match interrupt
+        lsb: 4
+        reset_value: '0'
+        width: 2
+    - PARALLEL_MODE:
+        access: rw
+        description: Parallel mode
+        lsb: 6
+        reset_value: '0'
+        width: 2
+    - INV_QUALIFIER:
+        access: rw
+        description: Inversion qualifier
+        lsb: 8
+        reset_value: '0'
+        width: 1
+- SGPIO_SLICE_MUX_CFG8:
+    fields: !!omap
+    - MATCH_MODE:
+        access: rw
+        description: Match mode
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_CAPTURE_MODE:
+        access: rw
+        description: Capture clock mode
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - CLKGEN_MODE:
+        access: rw
+        description: Clock generation mode
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - INV_OUT_CLK:
+        access: rw
+        description: Invert output clock
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - DATA_CAPTURE_MODE:
+        access: rw
+        description: Condition for input bit match interrupt
+        lsb: 4
+        reset_value: '0'
+        width: 2
+    - PARALLEL_MODE:
+        access: rw
+        description: Parallel mode
+        lsb: 6
+        reset_value: '0'
+        width: 2
+    - INV_QUALIFIER:
+        access: rw
+        description: Inversion qualifier
+        lsb: 8
+        reset_value: '0'
+        width: 1
+- SGPIO_SLICE_MUX_CFG9:
+    fields: !!omap
+    - MATCH_MODE:
+        access: rw
+        description: Match mode
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_CAPTURE_MODE:
+        access: rw
+        description: Capture clock mode
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - CLKGEN_MODE:
+        access: rw
+        description: Clock generation mode
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - INV_OUT_CLK:
+        access: rw
+        description: Invert output clock
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - DATA_CAPTURE_MODE:
+        access: rw
+        description: Condition for input bit match interrupt
+        lsb: 4
+        reset_value: '0'
+        width: 2
+    - PARALLEL_MODE:
+        access: rw
+        description: Parallel mode
+        lsb: 6
+        reset_value: '0'
+        width: 2
+    - INV_QUALIFIER:
+        access: rw
+        description: Inversion qualifier
+        lsb: 8
+        reset_value: '0'
+        width: 1
+- SGPIO_SLICE_MUX_CFG10:
+    fields: !!omap
+    - MATCH_MODE:
+        access: rw
+        description: Match mode
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_CAPTURE_MODE:
+        access: rw
+        description: Capture clock mode
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - CLKGEN_MODE:
+        access: rw
+        description: Clock generation mode
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - INV_OUT_CLK:
+        access: rw
+        description: Invert output clock
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - DATA_CAPTURE_MODE:
+        access: rw
+        description: Condition for input bit match interrupt
+        lsb: 4
+        reset_value: '0'
+        width: 2
+    - PARALLEL_MODE:
+        access: rw
+        description: Parallel mode
+        lsb: 6
+        reset_value: '0'
+        width: 2
+    - INV_QUALIFIER:
+        access: rw
+        description: Inversion qualifier
+        lsb: 8
+        reset_value: '0'
+        width: 1
+- SGPIO_SLICE_MUX_CFG11:
+    fields: !!omap
+    - MATCH_MODE:
+        access: rw
+        description: Match mode
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_CAPTURE_MODE:
+        access: rw
+        description: Capture clock mode
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - CLKGEN_MODE:
+        access: rw
+        description: Clock generation mode
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - INV_OUT_CLK:
+        access: rw
+        description: Invert output clock
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - DATA_CAPTURE_MODE:
+        access: rw
+        description: Condition for input bit match interrupt
+        lsb: 4
+        reset_value: '0'
+        width: 2
+    - PARALLEL_MODE:
+        access: rw
+        description: Parallel mode
+        lsb: 6
+        reset_value: '0'
+        width: 2
+    - INV_QUALIFIER:
+        access: rw
+        description: Inversion qualifier
+        lsb: 8
+        reset_value: '0'
+        width: 1
+- SGPIO_SLICE_MUX_CFG12:
+    fields: !!omap
+    - MATCH_MODE:
+        access: rw
+        description: Match mode
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_CAPTURE_MODE:
+        access: rw
+        description: Capture clock mode
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - CLKGEN_MODE:
+        access: rw
+        description: Clock generation mode
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - INV_OUT_CLK:
+        access: rw
+        description: Invert output clock
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - DATA_CAPTURE_MODE:
+        access: rw
+        description: Condition for input bit match interrupt
+        lsb: 4
+        reset_value: '0'
+        width: 2
+    - PARALLEL_MODE:
+        access: rw
+        description: Parallel mode
+        lsb: 6
+        reset_value: '0'
+        width: 2
+    - INV_QUALIFIER:
+        access: rw
+        description: Inversion qualifier
+        lsb: 8
+        reset_value: '0'
+        width: 1
+- SGPIO_SLICE_MUX_CFG13:
+    fields: !!omap
+    - MATCH_MODE:
+        access: rw
+        description: Match mode
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_CAPTURE_MODE:
+        access: rw
+        description: Capture clock mode
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - CLKGEN_MODE:
+        access: rw
+        description: Clock generation mode
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - INV_OUT_CLK:
+        access: rw
+        description: Invert output clock
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - DATA_CAPTURE_MODE:
+        access: rw
+        description: Condition for input bit match interrupt
+        lsb: 4
+        reset_value: '0'
+        width: 2
+    - PARALLEL_MODE:
+        access: rw
+        description: Parallel mode
+        lsb: 6
+        reset_value: '0'
+        width: 2
+    - INV_QUALIFIER:
+        access: rw
+        description: Inversion qualifier
+        lsb: 8
+        reset_value: '0'
+        width: 1
+- SGPIO_SLICE_MUX_CFG14:
+    fields: !!omap
+    - MATCH_MODE:
+        access: rw
+        description: Match mode
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_CAPTURE_MODE:
+        access: rw
+        description: Capture clock mode
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - CLKGEN_MODE:
+        access: rw
+        description: Clock generation mode
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - INV_OUT_CLK:
+        access: rw
+        description: Invert output clock
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - DATA_CAPTURE_MODE:
+        access: rw
+        description: Condition for input bit match interrupt
+        lsb: 4
+        reset_value: '0'
+        width: 2
+    - PARALLEL_MODE:
+        access: rw
+        description: Parallel mode
+        lsb: 6
+        reset_value: '0'
+        width: 2
+    - INV_QUALIFIER:
+        access: rw
+        description: Inversion qualifier
+        lsb: 8
+        reset_value: '0'
+        width: 1
+- SGPIO_SLICE_MUX_CFG15:
+    fields: !!omap
+    - MATCH_MODE:
+        access: rw
+        description: Match mode
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CLK_CAPTURE_MODE:
+        access: rw
+        description: Capture clock mode
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - CLKGEN_MODE:
+        access: rw
+        description: Clock generation mode
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - INV_OUT_CLK:
+        access: rw
+        description: Invert output clock
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - DATA_CAPTURE_MODE:
+        access: rw
+        description: Condition for input bit match interrupt
+        lsb: 4
+        reset_value: '0'
+        width: 2
+    - PARALLEL_MODE:
+        access: rw
+        description: Parallel mode
+        lsb: 6
+        reset_value: '0'
+        width: 2
+    - INV_QUALIFIER:
+        access: rw
+        description: Inversion qualifier
+        lsb: 8
+        reset_value: '0'
+        width: 1
+- SGPIO_POS0:
+    fields: !!omap
+    - POS:
+        access: rw
+        description: Each time COUNT reaches 0x0 POS counts down
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - POS_RESET:
+        access: rw
+        description: Reload value for POS after POS reaches 0x0
+        lsb: 8
+        reset_value: '0'
+        width: 8
+- SGPIO_POS1:
+    fields: !!omap
+    - POS:
+        access: rw
+        description: Each time COUNT reaches 0x0 POS counts down
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - POS_RESET:
+        access: rw
+        description: Reload value for POS after POS reaches 0x0
+        lsb: 8
+        reset_value: '0'
+        width: 8
+- SGPIO_POS2:
+    fields: !!omap
+    - POS:
+        access: rw
+        description: Each time COUNT reaches 0x0 POS counts down
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - POS_RESET:
+        access: rw
+        description: Reload value for POS after POS reaches 0x0
+        lsb: 8
+        reset_value: '0'
+        width: 8
+- SGPIO_POS3:
+    fields: !!omap
+    - POS:
+        access: rw
+        description: Each time COUNT reaches 0x0 POS counts down
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - POS_RESET:
+        access: rw
+        description: Reload value for POS after POS reaches 0x0
+        lsb: 8
+        reset_value: '0'
+        width: 8
+- SGPIO_POS4:
+    fields: !!omap
+    - POS:
+        access: rw
+        description: Each time COUNT reaches 0x0 POS counts down
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - POS_RESET:
+        access: rw
+        description: Reload value for POS after POS reaches 0x0
+        lsb: 8
+        reset_value: '0'
+        width: 8
+- SGPIO_POS5:
+    fields: !!omap
+    - POS:
+        access: rw
+        description: Each time COUNT reaches 0x0 POS counts down
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - POS_RESET:
+        access: rw
+        description: Reload value for POS after POS reaches 0x0
+        lsb: 8
+        reset_value: '0'
+        width: 8
+- SGPIO_POS6:
+    fields: !!omap
+    - POS:
+        access: rw
+        description: Each time COUNT reaches 0x0 POS counts down
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - POS_RESET:
+        access: rw
+        description: Reload value for POS after POS reaches 0x0
+        lsb: 8
+        reset_value: '0'
+        width: 8
+- SGPIO_POS7:
+    fields: !!omap
+    - POS:
+        access: rw
+        description: Each time COUNT reaches 0x0 POS counts down
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - POS_RESET:
+        access: rw
+        description: Reload value for POS after POS reaches 0x0
+        lsb: 8
+        reset_value: '0'
+        width: 8
+- SGPIO_POS8:
+    fields: !!omap
+    - POS:
+        access: rw
+        description: Each time COUNT reaches 0x0 POS counts down
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - POS_RESET:
+        access: rw
+        description: Reload value for POS after POS reaches 0x0
+        lsb: 8
+        reset_value: '0'
+        width: 8
+- SGPIO_POS9:
+    fields: !!omap
+    - POS:
+        access: rw
+        description: Each time COUNT reaches 0x0 POS counts down
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - POS_RESET:
+        access: rw
+        description: Reload value for POS after POS reaches 0x0
+        lsb: 8
+        reset_value: '0'
+        width: 8
+- SGPIO_POS10:
+    fields: !!omap
+    - POS:
+        access: rw
+        description: Each time COUNT reaches 0x0 POS counts down
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - POS_RESET:
+        access: rw
+        description: Reload value for POS after POS reaches 0x0
+        lsb: 8
+        reset_value: '0'
+        width: 8
+- SGPIO_POS11:
+    fields: !!omap
+    - POS:
+        access: rw
+        description: Each time COUNT reaches 0x0 POS counts down
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - POS_RESET:
+        access: rw
+        description: Reload value for POS after POS reaches 0x0
+        lsb: 8
+        reset_value: '0'
+        width: 8
+- SGPIO_POS12:
+    fields: !!omap
+    - POS:
+        access: rw
+        description: Each time COUNT reaches 0x0 POS counts down
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - POS_RESET:
+        access: rw
+        description: Reload value for POS after POS reaches 0x0
+        lsb: 8
+        reset_value: '0'
+        width: 8
+- SGPIO_POS13:
+    fields: !!omap
+    - POS:
+        access: rw
+        description: Each time COUNT reaches 0x0 POS counts down
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - POS_RESET:
+        access: rw
+        description: Reload value for POS after POS reaches 0x0
+        lsb: 8
+        reset_value: '0'
+        width: 8
+- SGPIO_POS14:
+    fields: !!omap
+    - POS:
+        access: rw
+        description: Each time COUNT reaches 0x0 POS counts down
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - POS_RESET:
+        access: rw
+        description: Reload value for POS after POS reaches 0x0
+        lsb: 8
+        reset_value: '0'
+        width: 8
+- SGPIO_POS15:
+    fields: !!omap
+    - POS:
+        access: rw
+        description: Each time COUNT reaches 0x0 POS counts down
+        lsb: 0
+        reset_value: '0'
+        width: 8
+    - POS_RESET:
+        access: rw
+        description: Reload value for POS after POS reaches 0x0
+        lsb: 8
+        reset_value: '0'
+        width: 8
diff --git a/libopencm3/scripts/data/lpc43xx/ssp.yaml b/libopencm3/scripts/data/lpc43xx/ssp.yaml
new file mode 100644
index 0000000..54b440b
--- /dev/null
+++ b/libopencm3/scripts/data/lpc43xx/ssp.yaml
@@ -0,0 +1,445 @@
+!!omap
+- SSP0_CR0:
+    fields: !!omap
+    - DSS:
+        access: rw
+        description: Data Size Select
+        lsb: 0
+        reset_value: '0'
+        width: 4
+    - FRF:
+        access: rw
+        description: Frame Format
+        lsb: 4
+        reset_value: '0'
+        width: 2
+    - CPOL:
+        access: rw
+        description: Clock Out Polarity
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - CPHA:
+        access: rw
+        description: Clock Out Phase
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - SCR:
+        access: rw
+        description: Serial Clock Rate
+        lsb: 8
+        reset_value: '0'
+        width: 8
+- SSP1_CR0:
+    fields: !!omap
+    - DSS:
+        access: rw
+        description: Data Size Select
+        lsb: 0
+        reset_value: '0'
+        width: 4
+    - FRF:
+        access: rw
+        description: Frame Format
+        lsb: 4
+        reset_value: '0'
+        width: 2
+    - CPOL:
+        access: rw
+        description: Clock Out Polarity
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - CPHA:
+        access: rw
+        description: Clock Out Phase
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - SCR:
+        access: rw
+        description: Serial Clock Rate
+        lsb: 8
+        reset_value: '0'
+        width: 8
+- SSP0_CR1:
+    fields: !!omap
+    - LBM:
+        access: rw
+        description: Loop Back Mode
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - SSE:
+        access: rw
+        description: SSP Enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - MS:
+        access: rw
+        description: Master/Slave Mode
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - SOD:
+        access: rw
+        description: Slave Output Disable
+        lsb: 3
+        reset_value: '0'
+        width: 1
+- SSP1_CR1:
+    fields: !!omap
+    - SSE:
+        access: rw
+        description: SSP Enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - MS:
+        access: rw
+        description: Master/Slave Mode
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - SOD:
+        access: rw
+        description: Slave Output Disable
+        lsb: 3
+        reset_value: '0'
+        width: 1
+- SSP0_DR:
+    fields: !!omap
+    - DATA:
+        access: rw
+        description: Software can write data to be transmitted to this register, and
+          read data that has been
+        lsb: 0
+        reset_value: '0'
+        width: 16
+- SSP1_DR:
+    fields: !!omap
+    - DATA:
+        access: rw
+        description: Software can write data to be transmitted to this register, and
+          read data that has been
+        lsb: 0
+        reset_value: '0'
+        width: 16
+- SSP0_SR:
+    fields: !!omap
+    - TFE:
+        access: r
+        description: Transmit FIFO Empty
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - TNF:
+        access: r
+        description: Transmit FIFO Not Full
+        lsb: 1
+        reset_value: '1'
+        width: 1
+    - RNE:
+        access: r
+        description: Receive FIFO Not Empty
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - RFF:
+        access: r
+        description: Receive FIFO Full
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - BSY:
+        access: r
+        description: Busy.
+        lsb: 4
+        reset_value: '0'
+        width: 1
+- SSP1_SR:
+    fields: !!omap
+    - TFE:
+        access: r
+        description: Transmit FIFO Empty
+        lsb: 0
+        reset_value: '1'
+        width: 1
+    - TNF:
+        access: r
+        description: Transmit FIFO Not Full
+        lsb: 1
+        reset_value: '1'
+        width: 1
+    - RNE:
+        access: r
+        description: Receive FIFO Not Empty
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - RFF:
+        access: r
+        description: Receive FIFO Full
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - BSY:
+        access: r
+        description: Busy.
+        lsb: 4
+        reset_value: '0'
+        width: 1
+- SSP0_CPSR:
+    fields: !!omap
+    - CPSDVSR:
+        access: rw
+        description: SSP Clock Prescale Register
+        lsb: 0
+        reset_value: '0'
+        width: 8
+- SSP1_CPSR:
+    fields: !!omap
+    - CPSDVSR:
+        access: rw
+        description: SSP Clock Prescale Register
+        lsb: 0
+        reset_value: '0'
+        width: 8
+- SSP0_IMSC:
+    fields: !!omap
+    - RORIM:
+        access: rw
+        description: Software should set this bit to enable interrupt when a Receive
+          Overrun occurs
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - RTIM:
+        access: rw
+        description: Software should set this bit to enable interrupt when a Receive
+          Time-out condition occurs
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - RXIM:
+        access: rw
+        description: Software should set this bit to enable interrupt when the Rx
+          FIFO is at least half full
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - TXIM:
+        access: rw
+        description: Software should set this bit to enable interrupt when the Tx
+          FIFO is at least half empty
+        lsb: 3
+        reset_value: '0'
+        width: 1
+- SSP1_IMSC:
+    fields: !!omap
+    - RORIM:
+        access: rw
+        description: Software should set this bit to enable interrupt when a Receive
+          Overrun occurs
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - RTIM:
+        access: rw
+        description: Software should set this bit to enable interrupt when a Receive
+          Time-out condition occurs
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - RXIM:
+        access: rw
+        description: Software should set this bit to enable interrupt when the Rx
+          FIFO is at least half full
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - TXIM:
+        access: rw
+        description: Software should set this bit to enable interrupt when the Tx
+          FIFO is at least half empty
+        lsb: 3
+        reset_value: '0'
+        width: 1
+- SSP0_RIS:
+    fields: !!omap
+    - RORRIS:
+        access: r
+        description: This bit is 1 if another frame was completely received while
+          the RxFIFO was full
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - RTRIS:
+        access: r
+        description: This bit is 1 if the Rx FIFO is not empty, and has not been read
+          for a time-out period
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - RXRIS:
+        access: r
+        description: This bit is 1 if the Rx FIFO is at least half full
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - TXRIS:
+        access: r
+        description: This bit is 1 if the Tx FIFO is at least half empty
+        lsb: 3
+        reset_value: '1'
+        width: 1
+- SSP1_RIS:
+    fields: !!omap
+    - RORRIS:
+        access: r
+        description: This bit is 1 if another frame was completely received while
+          the RxFIFO was full
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - RTRIS:
+        access: r
+        description: This bit is 1 if the Rx FIFO is not empty, and has not been read
+          for a time-out period
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - RXRIS:
+        access: r
+        description: This bit is 1 if the Rx FIFO is at least half full
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - TXRIS:
+        access: r
+        description: This bit is 1 if the Tx FIFO is at least half empty
+        lsb: 3
+        reset_value: '1'
+        width: 1
+- SSP0_MIS:
+    fields: !!omap
+    - RORMIS:
+        access: r
+        description: This bit is 1 if another frame was completely received while
+          the RxFIFO was full, and this interrupt is enabled
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - RTMIS:
+        access: r
+        description: This bit is 1 if the Rx FIFO is not empty, has not been read
+          for a time-out period, and this interrupt is enabled
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - RXMIS:
+        access: r
+        description: This bit is 1 if the Rx FIFO is at least half full, and this
+          interrupt is enabled
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - TXMIS:
+        access: r
+        description: This bit is 1 if the Tx FIFO is at least half empty, and this
+          interrupt is enabled
+        lsb: 3
+        reset_value: '0'
+        width: 1
+- SSP1_MIS:
+    fields: !!omap
+    - RORMIS:
+        access: r
+        description: This bit is 1 if another frame was completely received while
+          the RxFIFO was full, and this interrupt is enabled
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - RTMIS:
+        access: r
+        description: This bit is 1 if the Rx FIFO is not empty, has not been read
+          for a time-out period, and this interrupt is enabled
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - RXMIS:
+        access: r
+        description: This bit is 1 if the Rx FIFO is at least half full, and this
+          interrupt is enabled
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - TXMIS:
+        access: r
+        description: This bit is 1 if the Tx FIFO is at least half empty, and this
+          interrupt is enabled
+        lsb: 3
+        reset_value: '0'
+        width: 1
+- SSP0_ICR:
+    fields: !!omap
+    - RORIC:
+        access: w
+        description: Writing a 1 to this bit clears the 'frame was received when RxFIFO
+          was full' interrupt
+        lsb: 0
+        reset_value: ''
+        width: 1
+    - RTIC:
+        access: w
+        description: Writing a 1 to this bit clears the Rx FIFO was not empty and
+          has not been read for a time-out period interrupt
+        lsb: 1
+        reset_value: ''
+        width: 1
+- SSP1_ICR:
+    fields: !!omap
+    - RORIC:
+        access: w
+        description: Writing a 1 to this bit clears the 'frame was received when RxFIFO
+          was full' interrupt
+        lsb: 0
+        reset_value: ''
+        width: 1
+    - RTIC:
+        access: w
+        description: Writing a 1 to this bit clears the Rx FIFO was not empty and
+          has not been read for a time-out period interrupt
+        lsb: 1
+        reset_value: ''
+        width: 1
+- SSP0_DMACR:
+    fields: !!omap
+    - RXDMAE:
+        access: rw
+        description: Receive DMA Enable
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - TXDMAE:
+        access: rw
+        description: Transmit DMA Enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+- SSP1_DMACR:
+    fields: !!omap
+    - RXDMAE:
+        access: rw
+        description: Receive DMA Enable
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - TXDMAE:
+        access: rw
+        description: Transmit DMA Enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
diff --git a/libopencm3/scripts/data/lpc43xx/usb.yaml b/libopencm3/scripts/data/lpc43xx/usb.yaml
new file mode 100644
index 0000000..658a806
--- /dev/null
+++ b/libopencm3/scripts/data/lpc43xx/usb.yaml
@@ -0,0 +1,1416 @@
+!!omap
+- USB0_CAPLENGTH:
+    fields: !!omap
+    - CAPLENGTH:
+        access: r
+        description: Indicates offset to add to the register base address at the beginning
+          of the Operational Register
+        lsb: 0
+        reset_value: '0x40'
+        width: 8
+    - HCIVERSION:
+        access: r
+        description: BCD encoding of the EHCI revision number supported by this host
+          controller
+        lsb: 8
+        reset_value: '0x100'
+        width: 16
+- USB0_HCSPARAMS:
+    fields: !!omap
+    - N_PORTS:
+        access: r
+        description: Number of downstream ports
+        lsb: 0
+        reset_value: '0x1'
+        width: 4
+    - PPC:
+        access: r
+        description: Port Power Control
+        lsb: 4
+        reset_value: '0x1'
+        width: 1
+    - N_PCC:
+        access: r
+        description: Number of Ports per Companion Controller
+        lsb: 8
+        reset_value: '0x0'
+        width: 4
+    - N_CC:
+        access: r
+        description: Number of Companion Controller
+        lsb: 12
+        reset_value: '0x0'
+        width: 4
+    - PI:
+        access: r
+        description: Port indicators
+        lsb: 16
+        reset_value: '0x1'
+        width: 1
+    - N_PTT:
+        access: r
+        description: Number of Ports per Transaction Translator
+        lsb: 20
+        reset_value: '0x0'
+        width: 4
+    - N_TT:
+        access: r
+        description: Number of Transaction Translators
+        lsb: 24
+        reset_value: '0x0'
+        width: 4
+- USB0_HCCPARAMS:
+    fields: !!omap
+    - ADC:
+        access: r
+        description: 64-bit Addressing Capability
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - PFL:
+        access: r
+        description: Programmable Frame List Flag
+        lsb: 1
+        reset_value: '1'
+        width: 1
+    - ASP:
+        access: r
+        description: Asynchronous Schedule Park Capability
+        lsb: 2
+        reset_value: '1'
+        width: 1
+    - IST:
+        access: r
+        description: Isochronous Scheduling Threshold
+        lsb: 4
+        reset_value: '0'
+        width: 4
+    - EECP:
+        access: r
+        description: EHCI Extended Capabilities Pointer
+        lsb: 8
+        reset_value: '0'
+        width: 4
+- USB0_DCCPARAMS:
+    fields: !!omap
+    - DEN:
+        access: r
+        description: Device Endpoint Number
+        lsb: 0
+        reset_value: '0x4'
+        width: 5
+    - DC:
+        access: r
+        description: Device Capable
+        lsb: 7
+        reset_value: '0x1'
+        width: 1
+    - HC:
+        access: r
+        description: Host Capable
+        lsb: 8
+        reset_value: '0x1'
+        width: 1
+- USB0_USBCMD_D:
+    fields: !!omap
+    - RS:
+        access: rw
+        description: Run/Stop
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - RST:
+        access: rw
+        description: Controller reset
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - SUTW:
+        access: rw
+        description: Setup trip wire
+        lsb: 13
+        reset_value: '0'
+        width: 1
+    - ATDTW:
+        access: rw
+        description: Add dTD trip wire
+        lsb: 14
+        reset_value: '0'
+        width: 1
+    - ITC:
+        access: rw
+        description: Interrupt threshold control
+        lsb: 16
+        reset_value: '0x8'
+        width: 8
+- USB0_USBCMD_H:
+    fields: !!omap
+    - RS:
+        access: rw
+        description: Run/Stop
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - RST:
+        access: rw
+        description: Controller reset
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - FS0:
+        access: ''
+        description: Bit 0 of the Frame List Size bits
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - FS1:
+        access: ''
+        description: Bit 1 of the Frame List Size bits
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - PSE:
+        access: rw
+        description: This bit controls whether the host controller skips processing
+          the periodic schedule
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - ASE:
+        access: rw
+        description: This bit controls whether the host controller skips processing
+          the asynchronous schedule
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - IAA:
+        access: rw
+        description: This bit is used as a doorbell by software to tell the host controller
+          to issue an interrupt the next time it advances asynchronous schedule
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - ASP1_0:
+        access: rw
+        description: Asynchronous schedule park mode
+        lsb: 8
+        reset_value: '0x3'
+        width: 2
+    - ASPE:
+        access: rw
+        description: Asynchronous Schedule Park Mode Enable
+        lsb: 11
+        reset_value: '1'
+        width: 1
+    - FS2:
+        access: ''
+        description: Bit 2 of the Frame List Size bits
+        lsb: 15
+        reset_value: '0'
+        width: 1
+    - ITC:
+        access: rw
+        description: Interrupt threshold control
+        lsb: 16
+        reset_value: '0x8'
+        width: 8
+- USB0_USBSTS_D:
+    fields: !!omap
+    - UI:
+        access: rwc
+        description: USB interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - UEI:
+        access: rwc
+        description: USB error interrupt
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - PCI:
+        access: rwc
+        description: Port change detect
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - URI:
+        access: rwc
+        description: USB reset received
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - SRI:
+        access: rwc
+        description: SOF received
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - SLI:
+        access: rwc
+        description: DCSuspend
+        lsb: 8
+        reset_value: '0'
+        width: 1
+    - NAKI:
+        access: r
+        description: NAK interrupt bit
+        lsb: 16
+        reset_value: '0'
+        width: 1
+- USB0_USBSTS_H:
+    fields: !!omap
+    - UI:
+        access: rwc
+        description: USB interrupt
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - UEI:
+        access: rwc
+        description: USB error interrupt
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - PCI:
+        access: rwc
+        description: Port change detect
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - FRI:
+        access: rwc
+        description: Frame list roll-over
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - AAI:
+        access: rwc
+        description: Interrupt on async advance
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - SRI:
+        access: rwc
+        description: SOF received
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - HCH:
+        access: r
+        description: HCHalted
+        lsb: 12
+        reset_value: '1'
+        width: 1
+    - RCL:
+        access: r
+        description: Reclamation
+        lsb: 13
+        reset_value: '0'
+        width: 1
+    - PS:
+        access: r
+        description: Periodic schedule status
+        lsb: 14
+        reset_value: '0'
+        width: 1
+    - AS:
+        access: ''
+        description: Asynchronous schedule status
+        lsb: 15
+        reset_value: '0'
+        width: 1
+    - UAI:
+        access: rwc
+        description: USB host asynchronous interrupt (USBHSTASYNCINT)
+        lsb: 18
+        reset_value: '0'
+        width: 1
+    - UPI:
+        access: rwc
+        description: USB host periodic interrupt (USBHSTPERINT)
+        lsb: 19
+        reset_value: '0'
+        width: 1
+- USB0_USBINTR_D:
+    fields: !!omap
+    - UE:
+        access: rw
+        description: USB interrupt enable
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - UEE:
+        access: rw
+        description: USB error interrupt enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - PCE:
+        access: rw
+        description: Port change detect enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - URE:
+        access: rw
+        description: USB reset enable
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - SRE:
+        access: rw
+        description: SOF received enable
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - SLE:
+        access: rw
+        description: Sleep enable
+        lsb: 8
+        reset_value: '0'
+        width: 1
+    - NAKE:
+        access: rw
+        description: NAK interrupt enable
+        lsb: 16
+        reset_value: '0'
+        width: 1
+- USB0_USBINTR_H:
+    fields: !!omap
+    - UE:
+        access: rw
+        description: USB interrupt enable
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - UEE:
+        access: rw
+        description: USB error interrupt enable
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - PCE:
+        access: rw
+        description: Port change detect enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - FRE:
+        access: rw
+        description: Frame list rollover enable
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - AAE:
+        access: rw
+        description: Interrupt on asynchronous advance enable
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - SRE:
+        access: ''
+        description: SOF received enable
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - UAIE:
+        access: rw
+        description: USB host asynchronous interrupt enable
+        lsb: 18
+        reset_value: '0'
+        width: 1
+    - UPIA:
+        access: rw
+        description: USB host periodic interrupt enable
+        lsb: 19
+        reset_value: '0'
+        width: 1
+- USB0_FRINDEX_D:
+    fields: !!omap
+    - FRINDEX2_0:
+        access: r
+        description: Current micro frame number
+        lsb: 0
+        reset_value: ''
+        width: 3
+    - FRINDEX13_3:
+        access: r
+        description: Current frame number of the last frame transmitted
+        lsb: 3
+        reset_value: ''
+        width: 11
+- USB0_FRINDEX_H:
+    fields: !!omap
+    - FRINDEX2_0:
+        access: rw
+        description: Current micro frame number
+        lsb: 0
+        reset_value: ''
+        width: 3
+    - FRINDEX12_3:
+        access: rw
+        description: Frame list current index
+        lsb: 3
+        reset_value: ''
+        width: 10
+- USB0_DEVICEADDR:
+    fields: !!omap
+    - USBADRA:
+        access: ''
+        description: Device address advance
+        lsb: 24
+        reset_value: '0'
+        width: 1
+    - USBADR:
+        access: rw
+        description: USB device address
+        lsb: 25
+        reset_value: '0'
+        width: 7
+- USB0_PERIODICLISTBASE:
+    fields: !!omap
+    - PERBASE31_12:
+        access: rw
+        description: Base Address (Low)
+        lsb: 12
+        reset_value: ''
+        width: 20
+- USB0_ENDPOINTLISTADDR:
+    fields: !!omap
+    - EPBASE31_11:
+        access: rw
+        description: Endpoint list pointer (low)
+        lsb: 11
+        reset_value: ''
+        width: 21
+- USB0_ASYNCLISTADDR:
+    fields: !!omap
+    - ASYBASE31_5:
+        access: rw
+        description: Link pointer (Low) LPL
+        lsb: 5
+        reset_value: ''
+        width: 27
+- USB0_TTCTRL:
+    fields: !!omap
+    - TTHA:
+        access: rw
+        description: Hub address when FS or LS device are connected directly
+        lsb: 24
+        reset_value: ''
+        width: 7
+- USB0_BURSTSIZE:
+    fields: !!omap
+    - RXPBURST:
+        access: rw
+        description: Programmable RX burst length
+        lsb: 0
+        reset_value: '0x10'
+        width: 8
+    - TXPBURST:
+        access: rw
+        description: Programmable TX burst length
+        lsb: 8
+        reset_value: '0x10'
+        width: 8
+- USB0_TXFILLTUNING:
+    fields: !!omap
+    - TXSCHOH:
+        access: rw
+        description: FIFO burst threshold
+        lsb: 0
+        reset_value: '0x2'
+        width: 8
+    - TXSCHEATLTH:
+        access: rw
+        description: Scheduler health counter
+        lsb: 8
+        reset_value: '0x0'
+        width: 5
+    - TXFIFOTHRES:
+        access: rw
+        description: Scheduler overhead
+        lsb: 16
+        reset_value: '0x0'
+        width: 6
+- USB0_BINTERVAL:
+    fields: !!omap
+    - BINT:
+        access: rw
+        description: bInterval value
+        lsb: 0
+        reset_value: '0x00'
+        width: 4
+- USB0_ENDPTNAK:
+    fields: !!omap
+    - EPRN:
+        access: rwc
+        description: Rx endpoint NAK
+        lsb: 0
+        reset_value: '0x00'
+        width: 6
+    - EPTN:
+        access: rwc
+        description: Tx endpoint NAK
+        lsb: 16
+        reset_value: '0x00'
+        width: 6
+- USB0_ENDPTNAKEN:
+    fields: !!omap
+    - EPRNE:
+        access: rw
+        description: Rx endpoint NAK enable
+        lsb: 0
+        reset_value: '0x00'
+        width: 6
+    - EPTNE:
+        access: rw
+        description: Tx endpoint NAK
+        lsb: 16
+        reset_value: '0x00'
+        width: 6
+- USB0_PORTSC1_D:
+    fields: !!omap
+    - CCS:
+        access: r
+        description: Current connect status
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - PE:
+        access: r
+        description: Port enable
+        lsb: 2
+        reset_value: '1'
+        width: 1
+    - PEC:
+        access: r
+        description: Port enable/disable change
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - FPR:
+        access: rw
+        description: Force port resume
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - SUSP:
+        access: r
+        description: Suspend
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - PR:
+        access: r
+        description: Port reset
+        lsb: 8
+        reset_value: '0'
+        width: 1
+    - HSP:
+        access: r
+        description: High-speed status
+        lsb: 9
+        reset_value: '0'
+        width: 1
+    - PIC1_0:
+        access: rw
+        description: Port indicator control
+        lsb: 14
+        reset_value: '0'
+        width: 2
+    - PTC3_0:
+        access: rw
+        description: Port test control
+        lsb: 16
+        reset_value: '0'
+        width: 4
+    - PHCD:
+        access: rw
+        description: PHY low power suspend - clock disable (PLPSCD)
+        lsb: 23
+        reset_value: '0'
+        width: 1
+    - PFSC:
+        access: rw
+        description: Port force full speed connect
+        lsb: 24
+        reset_value: '0'
+        width: 1
+    - PSPD:
+        access: r
+        description: Port speed
+        lsb: 26
+        reset_value: '0'
+        width: 2
+- USB0_PORTSC1_H:
+    fields: !!omap
+    - CCS:
+        access: rwc
+        description: Current connect status
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - CSC:
+        access: rwc
+        description: Connect status change
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - PE:
+        access: rw
+        description: Port enable
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - PEC:
+        access: rwc
+        description: Port disable/enable change
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - OCA:
+        access: r
+        description: Over-current active
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - OCC:
+        access: rwc
+        description: Over-current change
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - FPR:
+        access: rw
+        description: Force port resume
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - SUSP:
+        access: rw
+        description: Suspend
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - PR:
+        access: rw
+        description: Port reset
+        lsb: 8
+        reset_value: '0'
+        width: 1
+    - HSP:
+        access: r
+        description: High-speed status
+        lsb: 9
+        reset_value: '0'
+        width: 1
+    - LS:
+        access: r
+        description: Line status
+        lsb: 10
+        reset_value: '0x3'
+        width: 2
+    - PP:
+        access: rw
+        description: Port power control
+        lsb: 12
+        reset_value: '0'
+        width: 1
+    - PIC1_0:
+        access: rw
+        description: Port indicator control
+        lsb: 14
+        reset_value: '0'
+        width: 2
+    - PTC3_0:
+        access: rw
+        description: Port test control
+        lsb: 16
+        reset_value: '0'
+        width: 4
+    - WKCN:
+        access: rw
+        description: Wake on connect enable (WKCNNT_E)
+        lsb: 20
+        reset_value: '0'
+        width: 1
+    - WKDC:
+        access: rw
+        description: Wake on disconnect enable (WKDSCNNT_E)
+        lsb: 21
+        reset_value: '0'
+        width: 1
+    - WKOC:
+        access: rw
+        description: Wake on over-current enable (WKOC_E)
+        lsb: 22
+        reset_value: '0'
+        width: 1
+    - PHCD:
+        access: rw
+        description: PHY low power suspend - clock disable (PLPSCD)
+        lsb: 23
+        reset_value: '0'
+        width: 1
+    - PFSC:
+        access: rw
+        description: Port force full speed connect
+        lsb: 24
+        reset_value: '0'
+        width: 1
+    - PSPD:
+        access: r
+        description: Port speed
+        lsb: 26
+        reset_value: '0'
+        width: 2
+- USB0_OTGSC:
+    fields: !!omap
+    - VD:
+        access: rw
+        description: VBUS_Discharge
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - VC:
+        access: rw
+        description: VBUS_Charge
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - HAAR:
+        access: rw
+        description: Hardware assist auto_reset
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - OT:
+        access: rw
+        description: OTG termination
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - DP:
+        access: rw
+        description: Data pulsing
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - IDPU:
+        access: rw
+        description: ID pull-up
+        lsb: 5
+        reset_value: '1'
+        width: 1
+    - HADP:
+        access: rw
+        description: Hardware assist data pulse
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - HABA:
+        access: rw
+        description: Hardware assist B-disconnect to A-connect
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - ID:
+        access: r
+        description: USB ID
+        lsb: 8
+        reset_value: '0'
+        width: 1
+    - AVV:
+        access: r
+        description: A-VBUS valid
+        lsb: 9
+        reset_value: '0'
+        width: 1
+    - ASV:
+        access: r
+        description: A-session valid
+        lsb: 10
+        reset_value: '0'
+        width: 1
+    - BSV:
+        access: r
+        description: B-session valid
+        lsb: 11
+        reset_value: '0'
+        width: 1
+    - BSE:
+        access: r
+        description: B-session end
+        lsb: 12
+        reset_value: '0'
+        width: 1
+    - MS1T:
+        access: r
+        description: 1 millisecond timer toggle
+        lsb: 13
+        reset_value: '0'
+        width: 1
+    - DPS:
+        access: r
+        description: Data bus pulsing status
+        lsb: 14
+        reset_value: '0'
+        width: 1
+    - IDIS:
+        access: rwc
+        description: USB ID interrupt status
+        lsb: 16
+        reset_value: '0'
+        width: 1
+    - AVVIS:
+        access: rwc
+        description: A-VBUS valid interrupt status
+        lsb: 17
+        reset_value: '0'
+        width: 1
+    - ASVIS:
+        access: rwc
+        description: A-Session valid interrupt status
+        lsb: 18
+        reset_value: '0'
+        width: 1
+    - BSVIS:
+        access: rwc
+        description: B-Session valid interrupt status
+        lsb: 19
+        reset_value: '0'
+        width: 1
+    - BSEIS:
+        access: rwc
+        description: B-Session end interrupt status
+        lsb: 20
+        reset_value: '0'
+        width: 1
+    - MS1S:
+        access: rwc
+        description: 1 millisecond timer interrupt status
+        lsb: 21
+        reset_value: '0'
+        width: 1
+    - DPIS:
+        access: rwc
+        description: Data pulse interrupt status
+        lsb: 22
+        reset_value: '0'
+        width: 1
+    - IDIE:
+        access: rw
+        description: USB ID interrupt enable
+        lsb: 24
+        reset_value: '0'
+        width: 1
+    - AVVIE:
+        access: rw
+        description: A-VBUS valid interrupt enable
+        lsb: 25
+        reset_value: '0'
+        width: 1
+    - ASVIE:
+        access: rw
+        description: A-session valid interrupt enable
+        lsb: 26
+        reset_value: '0'
+        width: 1
+    - BSVIE:
+        access: rw
+        description: B-session valid interrupt enable
+        lsb: 27
+        reset_value: '0'
+        width: 1
+    - BSEIE:
+        access: rw
+        description: B-session end interrupt enable
+        lsb: 28
+        reset_value: '0'
+        width: 1
+    - MS1E:
+        access: rw
+        description: 1 millisecond timer interrupt enable
+        lsb: 29
+        reset_value: '0'
+        width: 1
+    - DPIE:
+        access: rw
+        description: Data pulse interrupt enable
+        lsb: 30
+        reset_value: '0'
+        width: 1
+- USB0_USBMODE_D:
+    fields: !!omap
+    - CM1_0:
+        access: rwo
+        description: Controller mode
+        lsb: 0
+        reset_value: '0'
+        width: 2
+    - ES:
+        access: rw
+        description: Endian select
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - SLOM:
+        access: rw
+        description: Setup Lockout mode
+        lsb: 3
+        reset_value: '0'
+        width: 1
+    - SDIS:
+        access: rw
+        description: Setup Lockout mode
+        lsb: 4
+        reset_value: '0'
+        width: 1
+- USB0_USBMODE_H:
+    fields: !!omap
+    - CM:
+        access: rwo
+        description: Controller mode
+        lsb: 0
+        reset_value: '0'
+        width: 2
+    - ES:
+        access: rw
+        description: Endian select
+        lsb: 2
+        reset_value: '0'
+        width: 1
+    - SDIS:
+        access: rw
+        description: Stream disable mode
+        lsb: 4
+        reset_value: '0'
+        width: 1
+    - VBPS:
+        access: rwo
+        description: VBUS power select
+        lsb: 5
+        reset_value: '0'
+        width: 1
+- USB0_ENDPTSETUPSTAT:
+    fields: !!omap
+    - ENDPTSETUPSTAT:
+        access: rwc
+        description: Setup endpoint status for logical endpoints 0 to 5
+        lsb: 0
+        reset_value: '0'
+        width: 6
+- USB0_ENDPTPRIME:
+    fields: !!omap
+    - PERB:
+        access: rws
+        description: Prime endpoint receive buffer for physical OUT endpoints 5 to
+          0
+        lsb: 0
+        reset_value: '0'
+        width: 6
+    - PETB:
+        access: rws
+        description: Prime endpoint transmit buffer for physical IN endpoints 5 to
+          0
+        lsb: 16
+        reset_value: '0'
+        width: 6
+- USB0_ENDPTFLUSH:
+    fields: !!omap
+    - FERB:
+        access: rwc
+        description: Flush endpoint receive buffer for physical OUT endpoints 5 to
+          0
+        lsb: 0
+        reset_value: '0'
+        width: 6
+    - FETB:
+        access: rwc
+        description: Flush endpoint transmit buffer for physical IN endpoints 5 to
+          0
+        lsb: 16
+        reset_value: '0'
+        width: 6
+- USB0_ENDPTSTAT:
+    fields: !!omap
+    - ERBR:
+        access: r
+        description: Endpoint receive buffer ready for physical OUT endpoints 5 to
+          0
+        lsb: 0
+        reset_value: '0'
+        width: 6
+    - ETBR:
+        access: r
+        description: Endpoint transmit buffer ready for physical IN endpoints 3 to
+          0
+        lsb: 16
+        reset_value: '0'
+        width: 6
+- USB0_ENDPTCOMPLETE:
+    fields: !!omap
+    - ERCE:
+        access: rwc
+        description: Endpoint receive complete event for physical OUT endpoints 5
+          to 0
+        lsb: 0
+        reset_value: '0'
+        width: 6
+    - ETCE:
+        access: rwc
+        description: Endpoint transmit complete event for physical IN endpoints 5
+          to 0
+        lsb: 16
+        reset_value: '0'
+        width: 6
+- USB0_ENDPTCTRL0:
+    fields: !!omap
+    - RXS:
+        access: rw
+        description: Rx endpoint stall
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - RXT1_0:
+        access: rw
+        description: Endpoint type
+        lsb: 2
+        reset_value: '0'
+        width: 2
+    - RXE:
+        access: r
+        description: Rx endpoint enable
+        lsb: 7
+        reset_value: '1'
+        width: 1
+    - TXS:
+        access: rw
+        description: Tx endpoint stall
+        lsb: 16
+        reset_value: ''
+        width: 1
+    - TXT1_0:
+        access: r
+        description: Endpoint type
+        lsb: 18
+        reset_value: '0'
+        width: 2
+    - TXE:
+        access: r
+        description: Tx endpoint enable
+        lsb: 23
+        reset_value: '1'
+        width: 1
+- USB0_ENDPTCTRL1:
+    fields: !!omap
+    - RXS:
+        access: rw
+        description: Rx endpoint stall
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - RXT:
+        access: rw
+        description: Endpoint type
+        lsb: 2
+        reset_value: '0'
+        width: 2
+    - RXI:
+        access: rw
+        description: Rx data toggle inhibit
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - RXR:
+        access: ws
+        description: Rx data toggle reset
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - RXE:
+        access: rw
+        description: Rx endpoint enable
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - TXS:
+        access: rw
+        description: Tx endpoint stall
+        lsb: 16
+        reset_value: '0'
+        width: 1
+    - TXT1_0:
+        access: r
+        description: Tx Endpoint type
+        lsb: 18
+        reset_value: '0'
+        width: 2
+    - TXI:
+        access: rw
+        description: Tx data toggle inhibit
+        lsb: 21
+        reset_value: '0'
+        width: 1
+    - TXR:
+        access: ws
+        description: Tx data toggle reset
+        lsb: 22
+        reset_value: '1'
+        width: 1
+    - TXE:
+        access: r
+        description: Tx endpoint enable
+        lsb: 23
+        reset_value: '0'
+        width: 1
+- USB0_ENDPTCTRL2:
+    fields: !!omap
+    - RXS:
+        access: rw
+        description: Rx endpoint stall
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - RXT:
+        access: rw
+        description: Endpoint type
+        lsb: 2
+        reset_value: '0'
+        width: 2
+    - RXI:
+        access: rw
+        description: Rx data toggle inhibit
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - RXR:
+        access: ws
+        description: Rx data toggle reset
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - RXE:
+        access: rw
+        description: Rx endpoint enable
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - TXS:
+        access: rw
+        description: Tx endpoint stall
+        lsb: 16
+        reset_value: '0'
+        width: 1
+    - TXT1_0:
+        access: r
+        description: Tx Endpoint type
+        lsb: 18
+        reset_value: '0'
+        width: 2
+    - TXI:
+        access: rw
+        description: Tx data toggle inhibit
+        lsb: 21
+        reset_value: '0'
+        width: 1
+    - TXR:
+        access: ws
+        description: Tx data toggle reset
+        lsb: 22
+        reset_value: '1'
+        width: 1
+    - TXE:
+        access: r
+        description: Tx endpoint enable
+        lsb: 23
+        reset_value: '0'
+        width: 1
+- USB0_ENDPTCTRL3:
+    fields: !!omap
+    - RXS:
+        access: rw
+        description: Rx endpoint stall
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - RXT:
+        access: rw
+        description: Endpoint type
+        lsb: 2
+        reset_value: '0'
+        width: 2
+    - RXI:
+        access: rw
+        description: Rx data toggle inhibit
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - RXR:
+        access: ws
+        description: Rx data toggle reset
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - RXE:
+        access: rw
+        description: Rx endpoint enable
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - TXS:
+        access: rw
+        description: Tx endpoint stall
+        lsb: 16
+        reset_value: '0'
+        width: 1
+    - TXT1_0:
+        access: r
+        description: Tx Endpoint type
+        lsb: 18
+        reset_value: '0'
+        width: 2
+    - TXI:
+        access: rw
+        description: Tx data toggle inhibit
+        lsb: 21
+        reset_value: '0'
+        width: 1
+    - TXR:
+        access: ws
+        description: Tx data toggle reset
+        lsb: 22
+        reset_value: '1'
+        width: 1
+    - TXE:
+        access: r
+        description: Tx endpoint enable
+        lsb: 23
+        reset_value: '0'
+        width: 1
+- USB0_ENDPTCTRL4:
+    fields: !!omap
+    - RXS:
+        access: rw
+        description: Rx endpoint stall
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - RXT:
+        access: rw
+        description: Endpoint type
+        lsb: 2
+        reset_value: '0'
+        width: 2
+    - RXI:
+        access: rw
+        description: Rx data toggle inhibit
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - RXR:
+        access: ws
+        description: Rx data toggle reset
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - RXE:
+        access: rw
+        description: Rx endpoint enable
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - TXS:
+        access: rw
+        description: Tx endpoint stall
+        lsb: 16
+        reset_value: '0'
+        width: 1
+    - TXT1_0:
+        access: r
+        description: Tx Endpoint type
+        lsb: 18
+        reset_value: '0'
+        width: 2
+    - TXI:
+        access: rw
+        description: Tx data toggle inhibit
+        lsb: 21
+        reset_value: '0'
+        width: 1
+    - TXR:
+        access: ws
+        description: Tx data toggle reset
+        lsb: 22
+        reset_value: '1'
+        width: 1
+    - TXE:
+        access: r
+        description: Tx endpoint enable
+        lsb: 23
+        reset_value: '0'
+        width: 1
+- USB0_ENDPTCTRL5:
+    fields: !!omap
+    - RXS:
+        access: rw
+        description: Rx endpoint stall
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - RXT:
+        access: rw
+        description: Endpoint type
+        lsb: 2
+        reset_value: '0'
+        width: 2
+    - RXI:
+        access: rw
+        description: Rx data toggle inhibit
+        lsb: 5
+        reset_value: '0'
+        width: 1
+    - RXR:
+        access: ws
+        description: Rx data toggle reset
+        lsb: 6
+        reset_value: '0'
+        width: 1
+    - RXE:
+        access: rw
+        description: Rx endpoint enable
+        lsb: 7
+        reset_value: '0'
+        width: 1
+    - TXS:
+        access: rw
+        description: Tx endpoint stall
+        lsb: 16
+        reset_value: '0'
+        width: 1
+    - TXT1_0:
+        access: r
+        description: Tx Endpoint type
+        lsb: 18
+        reset_value: '0'
+        width: 2
+    - TXI:
+        access: rw
+        description: Tx data toggle inhibit
+        lsb: 21
+        reset_value: '0'
+        width: 1
+    - TXR:
+        access: ws
+        description: Tx data toggle reset
+        lsb: 22
+        reset_value: '1'
+        width: 1
+    - TXE:
+        access: r
+        description: Tx endpoint enable
+        lsb: 23
+        reset_value: '0'
+        width: 1
diff --git a/libopencm3/scripts/data/lpc43xx/yaml_odict.py b/libopencm3/scripts/data/lpc43xx/yaml_odict.py
new file mode 100644
index 0000000..05aa269
--- /dev/null
+++ b/libopencm3/scripts/data/lpc43xx/yaml_odict.py
@@ -0,0 +1,81 @@
+import yaml
+from collections import OrderedDict
+def construct_odict(load, node):
+    """This is the same as SafeConstructor.construct_yaml_omap(),
+    except the data type is changed to OrderedDict() and setitem is
+    used instead of append in the loop.
+ 
+    >>> yaml.load('''
+    ... !!omap
+    ... - foo: bar
+    ... - mumble: quux
+    ... - baz: gorp
+    ... ''')
+    OrderedDict([('foo', 'bar'), ('mumble', 'quux'), ('baz', 'gorp')])
+ 
+    >>> yaml.load('''!!omap [ foo: bar, mumble: quux, baz : gorp ]''')
+    OrderedDict([('foo', 'bar'), ('mumble', 'quux'), ('baz', 'gorp')])
+    """
+ 
+    omap = OrderedDict()
+    yield omap
+    if not isinstance(node, yaml.SequenceNode):
+        raise yaml.constructor.ConstructorError(
+            "while constructing an ordered map",
+            node.start_mark,
+            "expected a sequence, but found %s" % node.id, node.start_mark
+        )
+    for subnode in node.value:
+        if not isinstance(subnode, yaml.MappingNode):
+            raise yaml.constructor.ConstructorError(
+                "while constructing an ordered map", node.start_mark,
+                "expected a mapping of length 1, but found %s" % subnode.id,
+                subnode.start_mark
+            )
+        if len(subnode.value) != 1:
+            raise yaml.constructor.ConstructorError(
+                "while constructing an ordered map", node.start_mark,
+                "expected a single mapping item, but found %d items" % len(subnode.value),
+                subnode.start_mark
+            )
+        key_node, value_node = subnode.value[0]
+        key = load.construct_object(key_node)
+        value = load.construct_object(value_node)
+        omap[key] = value
+ 
+yaml.add_constructor(u'tag:yaml.org,2002:omap', construct_odict)
+
+def repr_pairs(dump, tag, sequence, flow_style=None):
+    """This is the same code as BaseRepresenter.represent_sequence(),
+    but the value passed to dump.represent_data() in the loop is a
+    dictionary instead of a tuple."""
+ 
+    value = []
+    node = yaml.SequenceNode(tag, value, flow_style=flow_style)
+    if dump.alias_key is not None:
+        dump.represented_objects[dump.alias_key] = node
+    best_style = True
+    for (key, val) in sequence:
+        item = dump.represent_data({key: val})
+        if not (isinstance(item, yaml.ScalarNode) and not item.style):
+            best_style = False
+        value.append(item)
+    if flow_style is None:
+        if dump.default_flow_style is not None:
+            node.flow_style = dump.default_flow_style
+        else:
+            node.flow_style = best_style
+    return node
+
+def repr_odict(dumper, data):
+    """
+    >>> data = OrderedDict([('foo', 'bar'), ('mumble', 'quux'), ('baz', 'gorp')])
+    >>> yaml.dump(data, default_flow_style=False)
+    '!!omap\\n- foo: bar\\n- mumble: quux\\n- baz: gorp\\n'
+    >>> yaml.dump(data, default_flow_style=True)
+    '!!omap [foo: bar, mumble: quux, baz: gorp]\\n'
+    """
+    return repr_pairs(dumper, u'tag:yaml.org,2002:omap', data.iteritems())
+ 
+yaml.add_representer(OrderedDict, repr_odict)
+ 
diff --git a/libopencm3/scripts/genlink.awk b/libopencm3/scripts/genlink.awk
new file mode 100644
index 0000000..c5d32d4
--- /dev/null
+++ b/libopencm3/scripts/genlink.awk
@@ -0,0 +1,65 @@
+# This awk program generates parameters for the linker script generator feature.
+#
+# See ld/README file for more info.
+#
+
+# This file is part of the libopencm3 project.
+# 
+# Copyright (C) 2013 Frantisek Burian <Bufran@seznam.cz>
+# Copyright (C) 2013 Werner Almesberger <wpwrak>
+# 
+# This library is free software: you can redistribute it and/or modify
+# it under the terms of the GNU Lesser General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU Lesser General Public License for more details.
+# 
+# You should have received a copy of the GNU Lesser General Public License
+# along with this library. If not, see <http://www.gnu.org/licenses/>.
+
+BEGIN {
+	PAT = tolower(PAT);
+	if (length(MODE) == 0)
+		MODE = ".*";
+}
+!/^#/{
+	#remove cr on windows
+	gsub(/\r$/,"");
+
+	tmp = "^"$1"$";
+	gsub(/?/, ".", tmp);
+	gsub(/*/, ".*", tmp);
+	gsub(/+/, ".+", tmp);
+	tolower(tmp);
+
+	if (PAT ~ tmp) {
+		if ($2 != "+")
+			PAT=$2;
+
+		for (i = 3; i <= NF; i = i + 1) {
+			if ($i ~ /^-l/) {
+				if ("LIB" ~ MODE)
+					printf "%s ",$i;
+			}
+			else if ($i ~ /^-m/) {
+				if ("ARCH" ~ MODE)
+					printf "%s ",$i;
+			}
+			else if ($i ~ /^-D/) {
+				if ("DEFS" ~ MODE)
+					printf "%s ",$i;
+			}
+			else {
+				if ("DEFS" ~ MODE)
+					printf "-D_%s ",$i;
+			}
+		}
+
+		if (PAT=="END")
+			exit;
+	}
+}
diff --git a/libopencm3/scripts/genlinktest.sh b/libopencm3/scripts/genlinktest.sh
new file mode 100644
index 0000000..5117620
--- /dev/null
+++ b/libopencm3/scripts/genlinktest.sh
@@ -0,0 +1,39 @@
+#!/bin/sh
+
+# This script is intended to test the awk program genlink.awk for the linker 
+# script generator feature.
+#
+# See ld/README file for more info.
+#
+
+# This file is part of the libopencm3 project.
+# 
+# Copyright (C) 2013 Frantisek Burian <Bufran@seznam.cz>
+# Copyright (C) 2013 Werner Almesberger <wpwrak>
+# 
+# This library is free software: you can redistribute it and/or modify
+# it under the terms of the GNU Lesser General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU Lesser General Public License for more details.
+# 
+# You should have received a copy of the GNU Lesser General Public License
+# along with this library. If not, see <http://www.gnu.org/licenses/>.
+
+# run test
+PAAT=`basename $1`;
+awk -v PAT="$PAAT" -f scripts/genlink.awk $1.data > $1.out;
+
+#check test
+if ! diff -q $1.out $1.result >/dev/null; then
+	exit 1;
+fi
+
+#remove workout only if it is OK
+rm -f $1.out
+
+exit 0  
\ No newline at end of file
diff --git a/libopencm3/scripts/irq2nvic_h b/libopencm3/scripts/irq2nvic_h
new file mode 100755
index 0000000..52f1265
--- /dev/null
+++ b/libopencm3/scripts/irq2nvic_h
@@ -0,0 +1,174 @@
+#!/usr/bin/env python
+
+# This file is part of the libopencm3 project.
+# 
+# Copyright (C) 2012 chrysn <chrysn@fsfe.org>
+# 
+# This library is free software: you can redistribute it and/or modify
+# it under the terms of the GNU Lesser General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU Lesser General Public License for more details.
+# 
+# You should have received a copy of the GNU Lesser General Public License
+# along with this library. If not, see <http://www.gnu.org/licenses/>.
+
+"""Generate an nvic.h header from a small JSON file describing the interrupt
+numbers.
+
+Code generation is chosen here because the resulting C code needs to be very
+repetetive (definition of the IRQ numbers, function prototypes, weak fallback
+definition and vector table definition), all being very repetitive. No portable
+method to achive the same thing with C preprocessor is known to the author.
+(Neither is any non-portable method, for that matter.)"""
+
+import sys
+import os
+import os.path
+import json
+
+template_nvic_h = '''\
+/* This file is part of the libopencm3 project.
+ *
+ * It was generated by the irq2nvic_h script.
+ */
+
+#ifndef {includeguard}
+#define {includeguard}
+
+#include <libopencm3/cm3/nvic.h>
+
+/** @defgroup CM3_nvic_defines_{partname_doxygen} User interrupts for {partname_humanreadable}
+    @ingroup CM3_nvic_defines
+
+    @{{*/
+
+{irqdefinitions}
+
+#define NVIC_IRQ_COUNT {irqcount}
+
+/**@}}*/
+
+/** @defgroup CM3_nvic_isrprototypes_{partname_doxygen} User interrupt service routines (ISR) prototypes for {partname_humanreadable}
+    @ingroup CM3_nvic_isrprototypes
+
+    @{{*/
+
+BEGIN_DECLS
+
+{isrprototypes}
+
+END_DECLS
+
+/**@}}*/
+
+#endif /* {includeguard} */
+'''
+
+template_vector_nvic_c = '''\
+/* This file is part of the libopencm3 project.
+ *
+ * It was generated by the irq2nvic_h script.
+ *
+ * This part needs to get included in the compilation unit where
+ * blocking_handler gets defined due to the way #pragma works.
+ */
+
+
+/** @defgroup CM3_nvic_isrpragmas_{partname_doxygen} User interrupt service routines (ISR) defaults for {partname_humanreadable}
+    @ingroup CM3_nvic_isrpragmas
+
+    @{{*/
+
+{isrpragmas}
+
+/**@}}*/
+
+/* Initialization template for the interrupt vector table. This definition is
+ * used by the startup code generator (vector.c) to set the initial values for
+ * the interrupt handling routines to the chip family specific _isr weak
+ * symbols. */
+
+#define IRQ_HANDLERS \\
+    {vectortableinitialization}
+'''
+
+template_cmsis_h = '''\
+/* This file is part of the libopencm3 project.
+ *
+ * It was generated by the irq2nvic_h script.
+ *
+ * These definitions bend every interrupt handler that is defined CMSIS style
+ * to the weak symbol exported by libopencm3.
+ */
+
+{cmsisbends}
+'''
+
+def convert(infile, outfile_nvic, outfile_vectornvic, outfile_cmsis):
+    data = json.load(infile)
+
+    irq2name = list(enumerate(data['irqs']) if isinstance(data['irqs'], list) else data['irqs'].items())
+    irqnames = [v for (k,v) in irq2name]
+
+    if isinstance(data['irqs'], list):
+        data['irqcount'] = len(irq2name)
+    else:
+        data['irqcount'] = max([int(x) for x in data['irqs'].keys()]) + 1
+
+    data['irqdefinitions'] = "\n".join('#define NVIC_%s_IRQ %d'%(v.upper(),int(k)) for (k,v) in irq2name)
+    data['isrprototypes'] = "\n".join('void WEAK %s_isr(void);'%name.lower() for name in irqnames)
+    data['isrpragmas'] = "\n".join('#pragma weak %s_isr = blocking_handler'%name.lower() for name in irqnames)
+    data['vectortableinitialization'] = ', \\\n    '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames)
+    data['cmsisbends'] = "\n".join("#define %s_IRQHandler %s_isr"%(name.upper(), name.lower()) for name in irqnames)
+
+    outfile_nvic.write(template_nvic_h.format(**data))
+    outfile_vectornvic.write(template_vector_nvic_c.format(**data))
+    outfile_cmsis.write(template_cmsis_h.format(**data))
+
+def makeparentdir(filename):
+    try:
+        os.makedirs(os.path.dirname(filename))
+    except OSError:
+        # where is my 'mkdir -p'?
+        pass
+
+def needs_update(infiles, outfiles):
+    timestamp = lambda filename: os.stat(filename).st_mtime
+    return any(not os.path.exists(o) for o in outfiles) or max(map(timestamp, infiles)) > min(map(timestamp, outfiles))
+
+def main():
+    if sys.argv[1] == '--remove':
+        remove = True
+        del sys.argv[1]
+    else:
+        remove = False
+    infile = sys.argv[1]
+    if not infile.startswith('./include/libopencm3/') or not infile.endswith('/irq.json'):
+        raise ValueError("Arguent must match ./include/libopencm3/**/irq.json")
+    nvic_h = infile.replace('irq.json', 'nvic.h')
+    vector_nvic_c = infile.replace('./include/libopencm3/', './lib/').replace('irq.json', 'vector_nvic.c')
+    cmsis = infile.replace('irq.json', 'irqhandlers.h').replace('/libopencm3/', '/libopencmsis/')
+
+    if remove:
+        if os.path.exists(nvic_h):
+            os.unlink(nvic_h)
+        if os.path.exists(vector_nvic_c):
+            os.unlink(vector_nvic_c)
+        sys.exit(0)
+
+    if not needs_update([__file__, infile], [nvic_h, vector_nvic_c]):
+        sys.exit(0)
+
+    makeparentdir(nvic_h)
+    makeparentdir(vector_nvic_c)
+    makeparentdir(cmsis)
+
+    convert(open(infile), open(nvic_h, 'w'), open(vector_nvic_c, 'w'), open(cmsis, 'w'))
+
+if __name__ == "__main__":
+    main()
diff --git a/libopencm3/scripts/lpcvtcksum b/libopencm3/scripts/lpcvtcksum
new file mode 100755
index 0000000..27dc8a7
--- /dev/null
+++ b/libopencm3/scripts/lpcvtcksum
@@ -0,0 +1,51 @@
+#!/usr/bin/python
+#
+# Compute and insert the vector table checksum required for booting the
+# LPC43xx and some other NXP ARM microcontrollers.
+#
+# usage: lpcvtcksum firmware.bin
+#
+# This file is part of the libopencm3 project.
+#
+# Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
+#
+# This library is free software: you can redistribute it and/or modify
+# it under the terms of the GNU Lesser General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public License
+# along with this library.  If not, see <http://www.gnu.org/licenses/>.
+
+import sys, struct
+
+binfile = open(sys.argv[1], 'r+b')
+rawvectors = binfile.read(32)
+vectors = list(struct.unpack('<IIIIIIII', rawvectors))
+
+# compute vector table checksum
+sum = 0
+for i in range(7):
+	sum += vectors[i]
+vectors[7] = 1 + (0xffffffff ^ (0xffffffff & sum))
+
+print "computed vector table checksum: 0x%08x" % vectors[7]
+
+rawremainder = binfile.read()
+remainder = list(struct.unpack('B' * len(rawremainder), rawremainder))
+numbytes = len(remainder) + 32
+
+# pad to multiple of 4096 bytes to make GoodFET happy
+if (numbytes % 4096):
+	remainder.extend([0] * (4096 - numbytes % 4096))
+
+# rewrite file with checksum and padding
+data = vectors
+data.extend(remainder)
+binfile.seek(0)
+binfile.write(struct.pack('<IIIIIIII' + 'B' * len(remainder), *data))