/****************************************************************************** * Arch-specific dom0_ops.c * * Process command requests from domain-0 guest OS. * * Copyright (c) 2002, K A Fraser */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "cpu/mtrr/mtrr.h" #define TRC_DOM0OP_ENTER_BASE 0x00020000 #define TRC_DOM0OP_LEAVE_BASE 0x00030000 static int msr_cpu_mask; static unsigned long msr_addr; static unsigned long msr_lo; static unsigned long msr_hi; static void write_msr_for(void *unused) { if ( ((1 << smp_processor_id()) & msr_cpu_mask) ) (void)wrmsr_safe(msr_addr, msr_lo, msr_hi); } static void read_msr_for(void *unused) { if ( ((1 << smp_processor_id()) & msr_cpu_mask) ) (void)rdmsr_safe(msr_addr, msr_lo, msr_hi); } long arch_do_dom0_op(struct dom0_op *op, GUEST_HANDLE(dom0_op_t) u_dom0_op) { long ret = 0; switch ( op->cmd ) { case DOM0_MSR: { if ( op->u.msr.write ) { msr_cpu_mask = op->u.msr.cpu_mask; msr_addr = op->u.msr.msr; msr_lo = op->u.msr.in1; msr_hi = op->u.msr.in2; smp_call_function(write_msr_for, NULL, 1, 1); write_msr_for(NULL); } else { msr_cpu_mask = op->u.msr.cpu_mask; msr_addr = op->u.msr.msr; smp_call_function(read_msr_for, NULL, 1, 1); read_msr_for(NULL); op->u.msr.out1 = msr_lo; op->u.msr.out2 = msr_hi; copy_to_guest(u_dom0_op, op, 1); } ret = 0; } break; case DOM0_SHADOW_CONTROL: { struct domain *d; ret = -ESRCH; d = find_domain_by_id(op->u.shadow_control.domain); if ( d != NULL ) { ret = shadow_mode_control(d, &op->u.shadow_control); put_domain(d); copy_to_guest(u_dom0_op, op, 1); } } break; case DOM0_ADD_MEMTYPE: { ret = mtrr_add_page( op->u.add_memtype.mfn, op->u.add_memtype.nr_mfns, op->u.add_memtype.type, 1); if ( ret > 0 ) { op->u.add_memtype.handle = 0; op->u.add_memtype.reg = ret; (void)copy_to_guest(u_dom0_op, op, 1); ret = 0; } } break; case DOM0_DEL_MEMTYPE: { if (op->u.del_memtype.handle == 0 /* mtrr/main.c otherwise does a lookup */ && (int)op->u.del_memtype.reg >= 0) { ret = mtrr_del_page(op->u.del_memtype.reg, 0, 0); if (ret > 0) ret = 0; } else ret = -EINVAL; } break; case DOM0_READ_MEMTYPE: { unsigned long mfn; unsigned int nr_mfns; mtrr_type type; ret = -EINVAL; if ( op->u.read_memtype.reg < num_var_ranges ) { mtrr_if->get(op->u.read_memtype.reg, &mfn, &nr_mfns, &type); op->u.read_memtype.mfn = mfn; op->u.read_memtype.nr_mfns = nr_mfns; op->u.read_memtype.type = type; (void)copy_to_guest(u_dom0_op, op, 1); ret = 0; } } break; case DOM0_MICROCODE: { extern int microcode_update(void *buf, unsigned long len); ret = microcode_update(op->u.microcode.data.p, op->u.microcode.length); } break; case DOM0_IOPORT_PERMISSION: { struct domain *d; unsigned int fp = op->u.ioport_permission.first_port; unsigned int np = op->u.ioport_permission.nr_ports; ret = -EINVAL; if ( (fp + np) > 65536 ) break; ret = -ESRCH; if ( unlikely((d = find_domain_by_id( op->u.ioport_permission.domain)) == NULL) ) break; if ( np == 0 ) ret = 0; else if ( op->u.ioport_permission.allow_access ) ret = ioports_permit_access(d, fp, fp + np - 1); else ret = ioports_deny_access(d, fp, fp + np - 1); put_domain(d); } break; case DOM0_PHYSINFO: { dom0_physinfo_t *pi = &op->u.physinfo; pi->threads_per_core = cpus_weight(cpu_sibling_map[0]); pi->cores_per_socket = cpus_weight(cpu_core_map[0]) / pi->threads_per_core; pi->sockets_per_node = num_online_cpus() / cpus_weight(cpu_core_map[0]); pi->nr_nodes = 1; pi->total_pages = total_pages; pi->free_pages = avail_domheap_pages(); pi->cpu_khz 
//-----------------------------------------------------
// Design Name : cam
// File Name   : cam.v
// Function    : CAM
// Coder       : Deepak Kumar Tala
//-----------------------------------------------------
module cam (
clk         , // Cam clock
cam_enable  , // Cam enable
cam_data_in , // Cam data to match
cam_hit_out , // Cam match has happened
cam_addr_out  // Cam output address 
);

parameter ADDR_WIDTH  = 8;
parameter DEPTH       = 1 << ADDR_WIDTH;
//------------Input Ports--------------
input                    clk;      
input                    cam_enable;   
input  [DEPTH-1:0]       cam_data_in;  
//----------Output Ports--------------
output                   cam_hit_out;  
output [ADDR_WIDTH-1:0]  cam_addr_out;  
//------------Internal Variables--------
reg [ADDR_WIDTH-1:0]  cam_addr_out;
reg                   cam_hit_out;
reg [ADDR_WIDTH-1:0]  cam_addr_combo;
reg                   cam_hit_combo;
reg                   found_match;
integer               i;
//-------------Code Starts Here-------
always @(cam_data_in) begin
  cam_addr_combo   = {ADDR_WIDTH{1'b0}};
  found_match      = 1'b0;
  cam_hit_combo    = 1'b0;
  for (i=0; i<DEPTH; i=i+1) begin
    if (cam_data_in[i] && !found_match) begin
      found_match     = 1'b1;
      cam_hit_combo   = 1'b1;
      cam_addr_combo  = i;
    end else begin
      found_match     = found_match;
      cam_hit_combo   = cam_hit_combo;
      cam_addr_combo  = cam_addr_combo;
    end
  end
end

// Register the outputs 
always @(posedge clk) begin
  if (cam_enable) begin
    cam_hit_out  <=  cam_hit_combo;
    cam_addr_out <=  cam_addr_combo;
  end else begin
    cam_hit_out  <=  1'b0;
    cam_addr_out <=  {ADDR_WIDTH{1'b0}};
  end
end

endmodule
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