/******************************************************************************* Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. The full GNU General Public License is included in this distribution in the file called LICENSE. Contact Information: Linux NICS Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 *******************************************************************************/ /* e1000_hw.c * Shared functions for accessing and configuring the MAC */ #include "e1000_hw.h" static int32_t e1000_setup_fiber_link(struct e1000_hw *hw); static int32_t e1000_setup_copper_link(struct e1000_hw *hw); static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw); static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw); static int32_t e1000_force_mac_fc(struct e1000_hw *hw); static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count); static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw); static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw); static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd); static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd); static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count); static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw); static void e1000_setup_eeprom(struct e1000_hw *hw); static void e1000_clock_eeprom(struct e1000_hw *hw); static void e1000_cleanup_eeprom(struct e1000_hw *hw); static void e1000_standby_eeprom(struct e1000_hw *hw); static int32_t e1000_id_led_init(struct e1000_hw * hw); /****************************************************************************** * Set the mac type member in the hw struct. * * hw - Struct containing variables accessed by shared code *****************************************************************************/ int32_t e1000_set_mac_type(struct e1000_hw *hw) { DEBUGFUNC("e1000_set_mac_type"); switch (hw->device_id) { case E1000_DEV_ID_82542: switch (hw->revision_id) { case E1000_82542_2_0_REV_ID: hw->mac_type = e1000_82542_rev2_0; break; case E1000_82542_2_1_REV_ID: hw->mac_type = e1000_82542_rev2_1; break; default: /* Invalid 82542 revision ID */ return -E1000_ERR_MAC_TYPE; } break; case E1000_DEV_ID_82543GC_FIBER: case E1000_DEV_ID_82543GC_COPPER: hw->mac_type = e1000_82543; break; case E1000_DEV_ID_82544EI_COPPER: case E1000_DEV_ID_82544EI_FIBER: case E1000_DEV_ID_82544GC_COPPER: case E1000_DEV_ID_82544GC_LOM: hw->mac_type = e1000_82544; break; case E1000_DEV_ID_82540EM: case E1000_DEV_ID_82540EM_LOM: case E1000_DEV_ID_82540EP: case E1000_DEV_ID_82540EP_LOM: case E1000_DEV_ID_82540EP_LP: hw->mac_type = e1000_82540; break; case E1000_DEV_ID_82545EM_COPPER: case E1000_DEV_ID_82545EM_FIBER: hw->mac_type = e1000_82545; break; case E1000_DEV_ID_82546EB_COPPER: case E1000_DEV_ID_82546EB_FIBER: hw->mac_type = e1000_82546; break; default: /* Should never have loaded on this device */ return -E1000_ERR_MAC_TYPE; } return E1000_SUCCESS; } /****************************************************************************** * Reset the transmit and receive units; mask and clear all interrupts. * * hw - Struct containing variables accessed by shared code *****************************************************************************/ void e1000_reset_hw(struct e1000_hw *hw) { uint32_t ctrl; uint32_t ctrl_ext; uint32_t icr; uint32_t manc; DEBUGFUNC("e1000_reset_hw"); /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ if(hw->mac_type == e1000_82542_rev2_0) { DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); e1000_pci_clear_mwi(hw); } /* Clear interrupt mask to stop board from generating interrupts */ DEBUGOUT("Masking off all interrupts\n"); E1000_WRITE_REG(hw, IMC, 0xffffffff); /* Disable the Transmit and Receive units. Then delay to allow * any pending transactions to complete before we hit the MAC with * the global reset. */ E1000_WRITE_REG(hw, RCTL, 0); E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); E1000_WRITE_FLUSH(hw); /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ hw->tbi_compatibility_on = FALSE; /* Delay to allow any outstanding PCI transactions to complete before * resetting the device */ DEBUGOUT("Before delay\n"); msec_delay(10); /* Issue a global reset to the MAC. This will reset the chip's * transmit, receive, DMA, and link units. It will not effect * the current PCI configuration. The global reset bit is self- * clearing, and should clear within a microsecond. */ DEBUGOUT("Issuing a global reset to MAC\n"); ctrl = E1000_READ_REG(hw, CTRL); if(hw->mac_type > e1000_82543) E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); else E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); /* Force a reload from the EEPROM if necessary */ if(hw->mac_type < e1000_82540) { /* Wait for reset to complete */ udelay(10); ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); ctrl_ext |= E1000_CTRL_EXT_EE_RST; E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); E1000_WRITE_FLUSH(hw); /* Wait for EEPROM reload */ msec_delay(2); } else { /* Wait for EEPROM reload (it happens automatically) */ msec_delay(4); /* Dissable HW ARPs on ASF enabled adapters */ manc = E1000_READ_REG(hw, MANC); manc &= ~(E1000_MANC_ARP_EN); E1000_WRITE_REG(hw, MANC, manc); } /* Clear interrupt mask to stop board from generating interrupts */ DEBUGOUT("Masking off all interrupts\n"); E1000_WRITE_REG(hw, IMC, 0xffffffff); /* Clear any pending interrupt events. */ icr = E1000_READ_REG(hw, ICR); /* If MWI was previously enabled, reenable it. */ if(hw->mac_type == e1000_82542_rev2_0) { if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) e1000_pci_set_mwi(hw); } } /****************************************************************************** * Performs basic configuration of the adapter. * * hw - Struct containing variables accessed by shared code * * Assumes that the controller has previously been reset and is in a * post-reset uninitialized state. Initializes the receive address registers, * multicast table, and VLAN filter table. Calls routines to setup link * configuration and flow control settings. Clears all on-chip counters. Leaves * the transmit and receive units disabled and uninitialized. *****************************************************************************/ int32_t e1000_init_hw(struct e1000_hw *hw) { uint32_t ctrl, status; uint32_t i; int32_t ret_val; uint16_t pcix_cmd_word; uint16_t pcix_stat_hi_word; uint16_t cmd_mmrbc; uint16_t stat_mmrbc; DEBUGFUNC("e1000_init_hw"); /* Initialize Identification LED */ ret_val = e1000_id_led_init(hw); if(ret_val < 0) { DEBUGOUT("Error Initializing Identification LED\n"); return ret_val; } /* Set the Media Type and exit with error if it is not valid. */ if(hw->mac_type != e1000_82543) { /* tbi_compatibility is only valid on 82543 */ hw->tbi_compatibility_en = FALSE; } if(hw->mac_type >= e1000_82543) { status = E1000_READ_REG(hw, STATUS); if(status & E1000_STATUS_TBIMODE) { hw->media_type = e1000_media_type_fiber; /* tbi_compatibility not valid on fiber */ hw->tbi_compatibility_en = FALSE; } else { hw->media_type = e1000_media_type_copper; } } else { /* This is an 82542 (fiber only) */ hw->media_type = e1000_media_type_fiber; } /* Disabling VLAN filtering. */ DEBUGOUT("Initializing the IEEE VLAN\n"); E1000_WRITE_REG(hw, VET, 0); e1000_clear_vfta(hw); /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ if(hw->mac_type == e1000_82542_rev2_0) { DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); e1000_pci_clear_mwi(hw); E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); E1000_WRITE_FLUSH(hw); msec_delay(5); } /* Setup the receive address. This involves initializing all of the Receive * Address Registers (RARs 0 - 15). */ e1000_init_rx_addrs(hw); /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ if(hw->mac_type == e1000_82542_rev2_0) { E1000_WRITE_REG(hw, RCTL, 0); E1000_WRITE_FLUSH(hw); msec_delay(1); if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) e1000_pci_set_mwi(hw); } /* Zero out the Multicast HASH table */ DEBUGOUT("Zeroing the MTA\n"); for(i = 0; i < E1000_MC_TBL_SIZE; i++) E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); /* Set the PCI priority bit correctly in the CTRL register. This * determines if the adapter gives priority to receives, or if it * gives equal priority to transmits and receives. */ if(hw->dma_fairness) { ctrl = E1000_READ_REG(hw, CTRL); E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); } /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ if(hw->bus_type == e1000_bus_type_pcix) { e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> PCIX_COMMAND_MMRBC_SHIFT; stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> PCIX_STATUS_HI_MMRBC_SHIFT; if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; if(cmd_mmrbc > stat_mmrbc) { pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); } } /* Call a subroutine to configure the link and setup flow control. */ ret_val = e1000_setup_link(hw); /* Set the transmit descriptor write-back policy */ if(hw->mac_type > e1000_82544) { ctrl = E1000_READ_REG(hw, TXDCTL); ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; E1000_WRITE_REG(hw, TXDCTL, ctrl); } /* Clear all of the statistics registers (clear on read). It is * important that we do this after we have tried to establish link * because the symbol error count will increment wildly if there * is no link. */ e1000_clear_hw_cntrs(hw); return ret_val; } /****************************************************************************** * Configures flow control and link settings. * * hw - Struct containing variables accessed by shared code * * Determines which flow control settings to use. Calls the apropriate media- * specific link configuration function. Configures the flow control settings. * Assuming the adapter has a valid link partner, a valid link should be * established. Assumes the hardware has previously been reset and the * transmitter and receiver are not enabled. *****************************************************************************/ int32_t e1000_setup_link(struct e1000_hw *hw) { uint32_t ctrl_ext; int32_t ret_val; uint16_t eeprom_data; DEBUGFUNC("e1000_setup_link"); /* Read and store word 0x0F of the EEPROM. This word contains bits * that determine the hardware's default PAUSE (flow control) mode, * a bit that determines whether the HW defaults to enabling or * disabling auto-negotiation, and the direction of the * SW defined pins. If there is no SW over-ride of the flow * control setting, then the variable hw->fc will * be initialized based on a value in the EEPROM. */ if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, &eeprom_data) < 0) { DEBUGOUT("EEPROM Read Error\n"); return -E1000_ERR_EEPROM; } if(hw->fc == e1000_fc_default) { if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) hw->fc = e1000_fc_none; else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == EEPROM_WORD0F_ASM_DIR) hw->fc = e1000_fc_tx_pause; else hw->fc = e1000_fc_full; } /* We want to save off the original Flow Control configuration just * in case we get disconnected and then reconnected into a different * hub or switch with different Flow Control capabilities. */ if(hw->mac_type == e1000_82542_rev2_0) hw->fc &= (~e1000_fc_tx_pause); if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) hw->fc &= (~e1000_fc_rx_pause); hw->original_fc = hw->fc; DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); /* Take the 4 bits from EEPROM word 0x0F that determine the initial * polarity value for the SW controlled pins, and setup the * Extended Device Control reg with that info. * This is needed because one of the SW controlled pins is used for * signal detection. So this should be done before e1000_setup_pcs_link() * or e1000_phy_setup() is called. */ if(hw->mac_type == e1000_82543) { ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << SWDPIO__EXT_SHIFT); E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); } /* Call the necessary subroutine to configure the link. */ ret_val = (hw->media_type == e1000_media_type_fiber) ? e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw); /* Initialize the flow control address, type, and PAUSE timer * registers to their default values. This is done even if flow * control is disabled, because it does not hurt anything to * initialize these registers. */ DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); /* Set the flow control receive threshold registers. Normally, * these registers will be set to a default threshold that may be * adjusted later by the driver's runtime code. However, if the * ability to transmit pause frames in not enabled, then these * registers will be set to 0. */ if(!(hw->fc & e1000_fc_tx_pause)) { E1000_WRITE_REG(hw, FCRTL, 0); E1000_WRITE_REG(hw, FCRTH, 0); } else { /* We need to set up the Receive Threshold high and low water marks * as well as (optionally) enabling the transmission of XON frames. */ if(hw->fc_send_xon) { E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); } else { E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); } } return ret_val; } /****************************************************************************** * Sets up link for a fiber based adapter * * hw - Struct containing variables accessed by shared code * * Manipulates Physical Coding Sublayer functions in order to configure * link. Assumes the hardware has been previously reset and the transmitter * and receiver are not enabled. *****************************************************************************/ static int32_t e1000_setup_fiber_link(struct e1000_hw *hw) { uint32_t ctrl; uint32_t status; uint32_t txcw = 0; uint32_t i; uint32_t signal; int32_t ret_val; DEBUGFUNC("e1000_setup_fiber_link"); /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be * set when the optics detect a signal. On older adapters, it will be * cleared when there is a signal */ ctrl = E1000_READ_REG(hw, CTRL); if(hw->mac_type > e1000_82544) signal = E1000_CTRL_SWDPIN1; else signal = 0; /* Take the link out of reset */ ctrl &= ~(E1000_CTRL_LRST); e1000_config_collision_dist(hw); /* Check for a software override of the flow control settings, and setup * the device accordingly. If auto-negotiation is enabled, then software * will have to set the "PAUSE" bits to the correct value in the Tranmsit * Config Word Register (TXCW) and re-start auto-negotiation. However, if * auto-negotiation is disabled, then software will have to manually * configure the two flow control enable bits in the CTRL register. * * The possible values of the "fc" parameter are: * 0: Flow control is completely disabled * 1: Rx flow control is enabled (we can receive pause frames, but * not send pause frames). * 2: Tx flow control is enabled (we can send pause frames but we do * not support receiving pause frames). * 3: Both Rx and TX flow control (symmetric) are enabled. */ switch (hw->fc) { case e1000_fc_none: /* Flow control is completely disabled by a software over-ride. */ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); break; case e1000_fc_rx_pause: /* RX Flow control is enabled and TX Flow control is disabled by a * software over-ride. Since there really isn't a way to advertise * that we are capable of RX Pause ONLY, we will advertise that we * support both symmetric and asymmetric RX PAUSE. Later, we will * disable the adapter's ability to send PAUSE frames. */ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); break; case e1000_fc_tx_pause: /* TX Flow control is enabled, and RX Flow control is disabled, by a * software over-ride. */ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); break; case e1000_fc_full: /* Flow control (both RX and TX) is enabled by a software over-ride. */ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); break; default: DEBUGOUT("Flow control param set incorrectly\n"); return -E1000_ERR_CONFIG; break; } /* Since auto-negotiation is enabled, take the link out of reset (the link * will be in reset, because we previously reset the chip). This will * restart auto-negotiation. If auto-neogtiation is successful then the * link-up status bit will be set and the flow control enable bits (RFCE * and TFCE) will be set according to their negotiated value. */ DEBUGOUT("Auto-negotiation enabled\n"); E1000_WRITE_REG(hw, TXCW, txcw); E1000_WRITE_REG(hw, CTRL, ctrl); E1000_WRITE_FLUSH(hw); hw->txcw = txcw; msec_delay(1); /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" * indication in the Device Status Register. Time-out if a link isn't * seen in 500 milliseconds seconds (Auto-negotiation should complete in * less than 500 milliseconds even if the other end is doing it in SW). */ if((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { DEBUGOUT("Looking for Link\n"); for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { msec_delay(10); status = E1000_READ_REG(hw, STATUS); if(status & E1000_STATUS_LU) break; } if(i == (LINK_UP_TIMEOUT / 10)) { /* AutoNeg failed to achieve a link, so we'll call * e1000_check_for_link. This routine will force the link up if we * detect a signal. This will allow us to communicate with * non-autonegotiating link partners. */ DEBUGOUT("Never got a valid link from auto-neg!!!\n"); hw->autoneg_failed = 1; ret_val = e1000_check_for_link(hw); if(ret_val < 0) { DEBUGOUT("Error while checking for link\n"); return ret_val; } hw->autoneg_failed = 0; } else { hw->autoneg_failed = 0; DEBUGOUT("Valid Link Found\n"); } } else { DEBUGOUT("No Signal Detected\n"); } return 0; } /****************************************************************************** * Detects which PHY is present and the speed and duplex * * hw - Struct containing variables accessed by shared code ******************************************************************************/ static int32_t e1000_setup_copper_link(struct e1000_hw *hw) { uint32_t ctrl; int32_t ret_val; uint16_t i; uint16_t phy_data; DEBUGFUNC("e1000_setup_copper_link"); ctrl = E1000_READ_REG(hw, CTRL); /* With 82543, we need to force speed and duplex on the MAC equal to what * the PHY speed and duplex configuration is. In addition, we need to * perform a hardware reset on the PHY to take it out of reset. */ if(hw->mac_type > e1000_82543) { ctrl |= E1000_CTRL_SLU; ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); E1000_WRITE_REG(hw, CTRL, ctrl); } else { ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); E1000_WRITE_REG(hw, CTRL, ctrl); e1000_phy_hw_reset(hw); } /* Make sure we have a valid PHY */ ret_val = e1000_detect_gig_phy(hw); if(ret_val < 0) { DEBUGOUT("Error, did not detect valid phy.\n"); return ret_val; } DEBUGOUT1("Phy ID = %x \n", hw->phy_id); /* Enable CRS on TX. This must be set for half-duplex operation. */ if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) { DEBUGOUT("PHY Read Error\n"); return -E1000_ERR_PHY; } phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; /* Options: * MDI/MDI-X = 0 (default) * 0 - Auto for all speeds * 1 - MDI mode * 2 - MDI-X mode * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) */ phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; switch (hw->mdix) { case 1: phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; break; case 2: phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; break; case 3: phy_data |= M88E1000_PSCR_AUTO_X_1000T; break; case 0: default: phy_data |= M88E1000_PSCR_AUTO_X_MODE; break; } /* Options: * disable_polarity_correction = 0 (default) * Automatic Correction for Reversed Cable Polarity * 0 - Disabled * 1 - Enabled */ phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; if(hw->disable_polarity_correction == 1) phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; if(e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) { DEBUGOUT("PHY Write Error\n"); return -E1000_ERR_PHY; } /* Force TX_CLK in the Extended PHY Specific Control Register * to 25MHz clock. */ if(e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) { DEBUGOUT("PHY Read Error\n"); return -E1000_ERR_PHY; } phy_data |= M88E1000_EPSCR_TX_CLK_25; if (hw->phy_revision < M88E1011_I_REV_4) { /* Configure Master and Slave downshift values */ phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); if(e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) { DEBUGOUT("PHY Write Error\n"); return -E1000_ERR_PHY; } } /* SW Reset the PHY so all changes take effect */ ret_val = e1000_phy_reset(hw); if(ret_val < 0) { DEBUGOUT("Error Resetting the PHY\n"); return ret_val; } /* Options: * autoneg = 1 (default) * PHY will advertise value(s) parsed from * autoneg_advertised and fc * autoneg = 0 * PHY will be set to 10H, 10F, 100H, or 100F * depending on value parsed from forced_speed_duplex. */ /* Is autoneg enabled? This is enabled by default or by software override. * If so, call e1000_phy_setup_autoneg routine to parse the * autoneg_advertised and fc options. If autoneg is NOT enabled, then the * user should have provided a speed/duplex override. If so, then call * e1000_phy_force_speed_duplex to parse and set this up. */ if(hw->autoneg) { /* Perform some bounds checking on the hw->autoneg_advertised * parameter. If this variable is zero, then set it to the default. */ hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; /* If autoneg_advertised is zero, we assume it was not defaulted * by the calling code so we set to advertise full capability. */ if(hw->autoneg_advertised == 0) hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); ret_val = e1000_phy_setup_autoneg(hw); if(ret_val < 0) { DEBUGOUT("Error Setting up Auto-Negotiation\n"); return ret_val; } DEBUGOUT("Restarting Auto-Neg\n"); /* Restart auto-negotiation by setting the Auto Neg Enable bit and * the Auto Neg Restart bit in the PHY control register. */ if(e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) { DEBUGOUT("PHY Read Error\n"); return -E1000_ERR_PHY; } phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); if(e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) { DEBUGOUT("PHY Write Error\n"); return -E1000_ERR_PHY; } /* Does the user want to wait for Auto-Neg to complete here, or * check at a later time (for example, callback routine). */ if(hw->wait_autoneg_complete) { ret_val = e1000_wait_autoneg(hw); if(ret_val < 0) { DEBUGOUT("Error while waiting for autoneg to complete\n"); return ret_val; } } } else { DEBUGOUT("Forcing speed and duplex\n"); ret_val = e1000_phy_force_speed_duplex(hw); if(ret_val < 0) { DEBUGOUT("Error Forcing Speed and Duplex\n"); return ret_val; } } /* Check link status. Wait up to 100 microseconds for link to become * valid. */ for(i = 0; i < 10; i++) { if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { DEBUGOUT("PHY Read Error\n"); return -E1000_ERR_PHY; } if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { DEBUGOUT("PHY Read Error\n"); return -E1000_ERR_PHY; } if(phy_data & MII_SR_LINK_STATUS) { /* We have link, so we need to finish the config process: * 1) Set up the MAC to the current PHY speed/duplex * if we are on 82543. If we * are on newer silicon, we only need to configure * collision distance in the Transmit Control Register. * 2) Set up flow control on the MAC to that established with * the link partner. */ if(hw->mac_type >= e1000_82544) { e1000_config_collision_dist(hw); } else { ret_val = e1000_config_mac_to_phy(hw); if(ret_val < 0) { DEBUGOUT("Error configuring MAC to PHY settings\n"); return ret_val; } } ret_val = e1000_config_fc_after_link_up(hw); if(ret_val < 0) { DEBUGOUT("Error Configuring Flow Control\n"); return ret_val; } DEBUGOUT("Valid link established!!!\n"); return 0; } udelay(10); } DEBUGOUT("Unable to establish link!!!\n"); return 0; } /****************************************************************************** * Configures PHY autoneg and flow control advertisement settings * * hw - Struct containing variables accessed by shared code ******************************************************************************/ int32_t e1000_phy_setup_autoneg(struct e1000_hw *hw) { uint16_t mii_autoneg_adv_reg; uint16_t mii_1000t_ctrl_reg; DEBUGFUNC("e1000_phy_setup_autoneg"); /* Read the MII Auto-Neg Advertisement Register (Address 4). */ if(e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg) < 0) { DEBUGOUT("PHY Read Error\n"); return -E1000_ERR_PHY; } /* Read the MII 1000Base-T Control Register (Address 9). */ if(e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg) < 0) { DEBUGOUT("PHY Read Error\n"); return -E1000_ERR_PHY; } /* Need to parse both autoneg_advertised and fc and set up * the appropriate PHY registers. First we will parse for * autoneg_advertised software override. Since we can advertise * a plethora of combinations, we need to check each bit * individually. */ /* First we clear all the 10/100 mb speed bits in the Auto-Neg * Advertisement Register (Address 4) and the 1000 mb speed bits in * the 1000Base-T Control Register (Address 9). */ mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); /* Do we want to advertise 10 Mb Half Duplex? */ if(hw->autoneg_advertised & ADVERTISE_10_HALF) { DEBUGOUT("Advertise 10mb Half duplex\n"); mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; } /* Do we want to advertise 10 Mb Full Duplex? */ if(hw->autoneg_advertised & ADVERTISE_10_FULL) { DEBUGOUT("Advertise 10mb Full duplex\n"); mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; } /* Do we want to advertise 100 Mb Half Duplex? */ if(hw->autoneg_advertised & ADVERTISE_100_HALF) { DEBUGOUT("Advertise 100mb Half duplex\n"); mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; } /* Do we want to advertise 100 Mb Full Duplex? */ if(hw->autoneg_advertised & ADVERTISE_100_FULL) { DEBUGOUT("Advertise 100mb Full duplex\n"); mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; } /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ if(hw->autoneg_advertised & ADVERTISE_1000_HALF) { DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); } /* Do we want to advertise 1000 Mb Full Duplex? */ if(hw->autoneg_advertised & ADVERTISE_1000_FULL) { DEBUGOUT("Advertise 1000mb Full duplex\n"); mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; } /* Check for a software override of the flow control settings, and * setup the PHY advertisement registers accordingly. If * auto-negotiation is enabled, then software will have to set the * "PAUSE" bits to the correct value in the Auto-Negotiation * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. * * The possible values of the "fc" parameter are: * 0: Flow control is completely disabled * 1: Rx flow control is enabled (we can receive pause frames * but not send pause frames). * 2: Tx flow control is enabled (we can send pause frames * but we do not support receiving pause frames). * 3: Both Rx and TX flow control (symmetric) are enabled. * other: No software override. The flow control configuration * in the EEPROM is used. */ switch (hw->fc) { case e1000_fc_none: /* 0 */ /* Flow control (RX & TX) is completely disabled by a * software over-ride. */ mii_autoneg_adv_reg &= ~(NWAY_AR
// LUT RAMs for Virtex 5, Virtex 6, Spartan 6, Series 7, Ultrascale.
// The definitions are in lutrams_xc5v.txt (everything but Ultrascale)
// and lutrams_xcu.txt (Ultrascale).


module $__XILINX_LUTRAM_SP_ (...);

parameter INIT = 0;
parameter OPTION_ABITS = 5;
parameter WIDTH = 8;
parameter BITS_USED = 0;

output [WIDTH-1:0] PORT_RW_RD_DATA;
input [WIDTH-1:0] PORT_RW_WR_DATA;
input [OPTION_ABITS-1:0] PORT_RW_ADDR;
input PORT_RW_WR_EN;
input PORT_RW_CLK;

function [(1 << OPTION_ABITS)-1:0] init_slice;
	input integer idx;
	integer i;
	for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
		init_slice[i] = INIT[i * WIDTH + idx];
endfunction

function [(2 << OPTION_ABITS)-1:0] init_slice2;
	input integer idx;
	integer i;
	for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
		init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2];
endfunction

generate
case(OPTION_ABITS)
5: if (WIDTH == 8)
	RAM32M
	#(
		.INIT_D(init_slice2(0)),
		.INIT_C(init_slice2(1)),
		.INIT_B(init_slice2(2)),
		.INIT_A(init_slice2(3)),
	)
	_TECHMAP_REPLACE_
	(
		.DOA(PORT_RW_RD_DATA[7:6]),
		.DOB(PORT_RW_RD_DATA[5:4]),
		.DOC(PORT_RW_RD_DATA[3:2]),
		.DOD(PORT_RW_RD_DATA[1:0]),
		.DIA(PORT_RW_WR_DATA[7:6]),
		.DIB(PORT_RW_WR_DATA[5:4]),
		.DIC(PORT_RW_WR_DATA[3:2]),
		.DID(PORT_RW_WR_DATA[1:0]),
		.ADDRA(PORT_RW_ADDR),
		.ADDRB(PORT_RW_ADDR),
		.ADDRC(PORT_RW_ADDR),
		.ADDRD(PORT_RW_ADDR),
		.WE(PORT_RW_WR_EN),
		.WCLK(PORT_RW_CLK),
	);
else
	RAM32M16
	#(
		.INIT_H(init_slice2(0)),
		.INIT_G(init_slice2(1)),
		.INIT_F(init_slice2(2)),
		.INIT_E(init_slice2(3)),
		.INIT_D(init_slice2(4)),
		.INIT_C(init_slice2(5)),
		.INIT_B(init_slice2(6)),
		.INIT_A(init_slice2(7)),
	)
	_TECHMAP_REPLACE_
	(
		.DOA(PORT_RW_RD_DATA[15:14]),
		.DOB(PORT_RW_RD_DATA[13:12]),
		.DOC(PORT_RW_RD_DATA[11:10]),
		.DOD(PORT_RW_RD_DATA[9:8]),
		.DOE(PORT_RW_RD_DATA[7:6]),
		.DOF(PORT_RW_RD_DATA[5:4]),
		.DOG(PORT_RW_RD_DATA[3:2]),
		.DOH(PORT_RW_RD_DATA[1:0]),
		.DIA(PORT_RW_WR_DATA[15:14]),
		.DIB(PORT_RW_WR_DATA[13:12]),
		.DIC(PORT_RW_WR_DATA[11:10]),
		.DID(PORT_RW_WR_DATA[9:8]),
		.DIE(PORT_RW_WR_DATA[7:6]),
		.DIF(PORT_RW_WR_DATA[5:4]),
		.DIG(PORT_RW_WR_DATA[3:2]),
		.DIH(PORT_RW_WR_DATA[1:0]),
		.ADDRA(PORT_RW_ADDR),
		.ADDRB(PORT_RW_ADDR),
		.ADDRC(PORT_RW_ADDR),
		.ADDRD(PORT_RW_ADDR),
		.ADDRE(PORT_RW_ADDR),
		.ADDRF(PORT_RW_ADDR),
		.ADDRG(PORT_RW_ADDR),
		.ADDRH(PORT_RW_ADDR),
		.WE(PORT_RW_WR_EN),
		.WCLK(PORT_RW_CLK),
	);
6: begin
	genvar i;
	for (i = 0; i < WIDTH; i = i + 1)
		if (BITS_USED[i])
			RAM64X1S
			#(
				.INIT(init_slice(i)),
			)
			slice
			(
				.A0(PORT_RW_ADDR[0]),
				.A1(PORT_RW_ADDR[1]),
				.A2(PORT_RW_ADDR[2]),
				.A3(PORT_RW_ADDR[3]),
				.A4(PORT_RW_ADDR[4]),
				.A5(PORT_RW_ADDR[5]),
				.D(PORT_RW_WR_DATA[i]),
				.O(PORT_RW_RD_DATA[i]),
				.WE(PORT_RW_WR_EN),
				.WCLK(PORT_RW_CLK),
			);
end
7: begin
	genvar i;
	for (i = 0; i < WIDTH; i = i + 1)
		if (BITS_USED[i])
			RAM128X1S
			#(
				.INIT(init_slice(i)),
			)
			slice
			(
				.A0(PORT_RW_ADDR[0]),
				.A1(PORT_RW_ADDR[1]),
				.A2(PORT_RW_ADDR[2]),
				.A3(PORT_RW_ADDR[3]),
				.A4(PORT_RW_ADDR[4]),
				.A5(PORT_RW_ADDR[5]),
				.A6(PORT_RW_ADDR[6]),
				.D(PORT_RW_WR_DATA[i]),
				.O(PORT_RW_RD_DATA[i]),
				.WE(PORT_RW_WR_EN),
				.WCLK(PORT_RW_CLK),
			);
end
8: begin
	genvar i;
	for (i = 0; i < WIDTH; i = i + 1)
		if (BITS_USED[i])
			RAM256X1S
			#(
				.INIT(init_slice(i)),
			)
			slice
			(
				.A(PORT_RW_ADDR),
				.D(PORT_RW_WR_DATA[i]),
				.O(PORT_RW_RD_DATA[i]),
				.WE(PORT_RW_WR_EN),
				.WCLK(PORT_RW_CLK),
			);
end
9: begin
	genvar i;
	for (i = 0; i < WIDTH; i = i + 1)
		if (BITS_USED[i])
			RAM512X1S
			#(
				.INIT(init_slice(i)),
			)
			slice
			(
				.A(PORT_RW_ADDR),
				.D(PORT_RW_WR_DATA[i]),
				.O(PORT_RW_RD_DATA[i]),
				.WE(PORT_RW_WR_EN),
				.WCLK(PORT_RW_CLK),
			);
end
default:
	$error("invalid OPTION_ABITS/WIDTH combination");
endcase
endgenerate

endmodule


module $__XILINX_LUTRAM_DP_ (...);

parameter INIT = 0;
parameter OPTION_ABITS = 5;
parameter WIDTH = 4;
parameter BITS_USED = 0;

output [WIDTH-1:0] PORT_RW_RD_DATA;
input [WIDTH-1:0] PORT_RW_WR_DATA;
input [OPTION_ABITS-1:0] PORT_RW_ADDR;
input PORT_RW_WR_EN;
input PORT_RW_CLK;

output [WIDTH-1:0] PORT_R_RD_DATA;
input [OPTION_ABITS-1:0] PORT_R_ADDR;

function [(1 << OPTION_ABITS)-1:0] init_slice;
	input integer idx;
	integer i;
	for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
		init_slice[i] = INIT[i * WIDTH + idx];
endfunction

function [(2 << OPTION_ABITS)-1:0] init_slice2;
	input integer idx;
	integer i;
	for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
		init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2];
endfunction

generate
case (OPTION_ABITS)
5: if (WIDTH == 4)
	RAM32M
	#(
		.INIT_D(init_slice2(0)),
		.INIT_C(init_slice2(0)),
		.INIT_B(init_slice2(1)),
		.INIT_A(init_slice2(1)),
	)
	_TECHMAP_REPLACE_
	(
		.DOA(PORT_R_RD_DATA[3:2]),
		.DOB(PORT_RW_RD_DATA[3:2]),
		.DOC(PORT_R_RD_DATA[1:0]),
		.DOD(PORT_RW_RD_DATA[1:0]),
		.DIA(PORT_RW_WR_DATA[3:2]),
		.DIB(PORT_RW_WR_DATA[3:2]),
		.DIC(PORT_RW_WR_DATA[1:0]),
		.DID(PORT_RW_WR_DATA[1:0]),
		.ADDRA(PORT_R_ADDR),
		.ADDRB(PORT_RW_ADDR),
		.ADDRC(PORT_R_ADDR),
		.ADDRD(PORT_RW_ADDR),
		.WE(PORT_RW_WR_EN),
		.WCLK(PORT_RW_CLK),
	);
else
	RAM32M16
	#(
		.INIT_H(init_slice2(0)),
		.INIT_G(init_slice2(0)),
		.INIT_F(init_slice2(1)),
		.INIT_E(init_slice2(1)),
		.INIT_D(init_slice2(2)),
		.INIT_C(init_slice2(2)),
		.INIT_B(init_slice2(3)),
		.INIT_A(init_slice2(3)),
	)
	_TECHMAP_REPLACE_
	(
		.DOA(PORT_R_RD_DATA[7:6]),
		.DOB(PORT_RW_RD_DATA[7:6]),
		.DOC(PORT_R_RD_DATA[5:4]),
		.DOD(PORT_RW_RD_DATA[5:4]),
		.DOE(PORT_R_RD_DATA[3:2]),
		.DOF(PORT_RW_RD_DATA[3:2]),
		.DOG(PORT_R_RD_DATA[1:0]),
		.DOH(PORT_RW_RD_DATA[1:0]),
		.DIA(PORT_RW_WR_DATA[7:6]),
		.DIB(PORT_RW_WR_DATA[7:6]),
		.DIC(PORT_RW_WR_DATA[5:4]),
		.DID(PORT_RW_WR_DATA[5:4]),
		.DIE(PORT_RW_WR_DATA[3:2]),
		.DIF(PORT_RW_WR_DATA[3:2]),
		.DIG(PORT_RW_WR_DATA[1:0]),
		.DIH(PORT_RW_WR_DATA[1:0]),
		.ADDRA(PORT_R_ADDR),
		.ADDRB(PORT_RW_ADDR),
		.ADDRC(PORT_R_ADDR),
		.ADDRD(PORT_RW_ADDR),
		.ADDRE(PORT_R_ADDR),
		.ADDRF(PORT_RW_ADDR),
		.ADDRG(PORT_R_ADDR),
		.ADDRH(PORT_RW_ADDR),
		.WE(PORT_RW_WR_EN),
		.WCLK(PORT_RW_CLK),
	);
6: begin
	genvar i;
	for (i = 0; i < WIDTH; i = i + 1)
		if (BITS_USED[i])
			RAM64X1D
			#(
				.INIT(init_slice(i)),
			)
			slice
			(
				.A0(PORT_RW_ADDR[0]),
				.A1(PORT_RW_ADDR[1]),
				.A2(PORT_RW_ADDR[2]),
				.A3(PORT_RW_ADDR[3]),
				.A4(PORT_RW_ADDR[4]),
				.A5(PORT_RW_ADDR[5]),
				.D(PORT_RW_WR_DATA[i]),
				.SPO(PORT_RW_RD_DATA[i]),
				.WE(PORT_RW_WR_EN),
				.WCLK(PORT_RW_CLK),
				.DPRA0(PORT_R_ADDR[0]),
				.DPRA1(PORT_R_ADDR[1]),
				.DPRA2(PORT_R_ADDR[2]),
				.DPRA3(PORT_R_ADDR[3]),
				.DPRA4(PORT_R_ADDR[4]),
				.DPRA5(PORT_R_ADDR[5]),
				.DPO(PORT_R_RD_DATA[i]),
			);
end
7: begin
	genvar i;
	for (i = 0; i < WIDTH; i = i + 1)
		if (BITS_USED[i])
			RAM128X1D
			#(
				.INIT(init_slice(i)),
			)
			slice
			(
				.A(PORT_RW_ADDR),
				.D(PORT_RW_WR_DATA[i]),
				.SPO(PORT_RW_RD_DATA[i]),
				.WE(PORT_RW_WR_EN),
				.WCLK(PORT_RW_CLK),
				.DPRA(PORT_R_ADDR),
				.DPO(PORT_R_RD_DATA[i]),
			);
end
8: begin
	genvar i;
	for (i = 0; i < WIDTH; i = i + 1)
		if (BITS_USED[i])
			RAM256X1D
			#(
				.INIT(init_slice(i)),
			)
			slice
			(
				.A(PORT_RW_ADDR),
				.D(PORT_RW_WR_DATA[i]),
				.SPO(PORT_RW_RD_DATA[i]),
				.WE(PORT_RW_WR_EN),
				.WCLK(PORT_RW_CLK),
				.DPRA(PORT_R_ADDR),
				.DPO(PORT_R_RD_DATA[i]),
			);
end
default:
	$error("invalid OPTION_ABITS/WIDTH combination");
endcase
endgenerate

endmodule


module $__XILINX_LUTRAM_QP_ (...);

parameter INIT = 0;
parameter OPTION_ABITS = 5;
parameter WIDTH = 2;
parameter BITS_USED = 0;

output [WIDTH-1:0] PORT_RW_RD_DATA;
input [WIDTH-1:0] PORT_RW_WR_DATA;
input [OPTION_ABITS-1:0] PORT_RW_ADDR;
input PORT_RW_WR_EN;
input PORT_RW_CLK;

output [WIDTH-1:0] PORT_R0_RD_DATA;
input [OPTION_ABITS-1:0] PORT_R0_ADDR;
output [WIDTH-1:0] PORT_R1_RD_DATA;
input [OPTION_ABITS-1:0] PORT_R1_ADDR;
output [WIDTH-1:0] PORT_R2_RD_DATA;
input [OPTION_ABITS-1:0] PORT_R2_ADDR;

function [(1 << OPTION_ABITS)-1:0] init_slice;
	input integer idx;
	integer i;
	for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
		init_slice[i] = INIT[i * WIDTH + idx];
endfunction

function [(2 << OPTION_ABITS)-1:0] init_slice2;
	input integer idx;
	integer i;
	for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
		init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2];
endfunction

generate
case (OPTION_ABITS)
5: if (WIDTH == 2)
	RAM32M
	#(
		.INIT_D(init_slice2(0)),
		.INIT_C(init_slice2(0)),
		.INIT_B(init_slice2(0)),
		.INIT_A(init_slice2(0)),
	)
	_TECHMAP_REPLACE_
	(
		.DOA(PORT_R2_RD_DATA[1:0]),
		.DOB(PORT_R1_RD_DATA[1:0]),
		.DOC(PORT_R0_RD_DATA[1:0]),
		.DOD(PORT_RW_RD_DATA[1:0]),
		.DIA(PORT_RW_WR_DATA[1:0]),
		.DIB(PORT_RW_WR_DATA[1:0]),
		.DIC(PORT_RW_WR_DATA[1:0]),
		.DID(PORT_RW_WR_DATA[1:0]),
		.ADDRA(PORT_R2_ADDR),
		.ADDRB(PORT_R1_ADDR),
		.ADDRC(PORT_R0_ADDR),
		.ADDRD(PORT_RW_ADDR),
		.WE(PORT_RW_WR_EN),
		.WCLK(PORT_RW_CLK),
	);
else
	RAM32M16
	#(
		.INIT_H(init_slice2(0)),
		.INIT_G(init_slice2(0)),
		.INIT_F(init_slice2(0)),
		.INIT_E(init_slice2(0)),
		.INIT_D(init_slice2(1)),
		.INIT_C(init_slice2(1)),
		.INIT_B(init_slice2(1)),
		.INIT_A(init_slice2(1)),
	)
	_TECHMAP_REPLACE_
	(
		.DOA(PORT_R2_RD_DATA[3:2]),
		.DOB(PORT_R1_RD_DATA[3:2]),
		.DOC(PORT_R0_RD_DATA[3:2]),
		.DOD(PORT_RW_RD_DATA[3:2]),
		.DOE(PORT_R2_RD_DATA[1:0]),
		.DOF(PORT_R1_RD_DATA[1:0]),
		.DOG(PORT_R0_RD_DATA[1:0]),
		.DOH(PORT_RW_RD_DATA[1:0]),
		.DIA(PORT_RW_WR_DATA[3:2]),
		.DIB(PORT_RW_WR_DATA[3:2]),
		.DIC(PORT_RW_WR_DATA[3:2]),
		.DID(PORT_RW_WR_DATA[3:2]),
		.DIE(PORT_RW_WR_DATA[1:0]),
		.DIF(PORT_RW_WR_DATA[1:0]),
		.DIG(PORT_RW_WR_DATA[1:0]),
		.DIH(PORT_RW_WR_DATA[1:0]),
		.ADDRA(PORT_R2_ADDR),
		.ADDRB(PORT_R1_ADDR),
		.ADDRC(PORT_R0_ADDR),
		.ADDRD(PORT_RW_ADDR),
		.ADDRE(PORT_R2_ADDR),
		.ADDRF(PORT_R1_ADDR),
		.ADDRG(PORT_R0_ADDR),
		.ADDRH(PORT_RW_ADDR),
		.WE(PORT_RW_WR_EN),
		.WCLK(PORT_RW_CLK),
	);
6: if (WIDTH == 1)
	RAM64M
	#(
		.INIT_D(init_slice(0)),
		.INIT_C(init_slice(0)),
		.INIT_B(init_slice(0)),
		.INIT_A(init_slice(0)),
	)
	_TECHMAP_REPLACE_
	(
		.DOA(PORT_R2_RD_DATA[0]),
		.DOB(PORT_R1_RD_DATA[0]),
		.DOC(PORT_R0_RD_DATA[0]),
		.DOD(PORT_RW_RD_DATA[0]),
		.DIA(PORT_RW_WR_DATA[0]),
		.DIB(PORT_RW_WR_DATA[0]),
		.DIC(PORT_RW_WR_DATA[0]),
		.DID(PORT_RW_WR_DATA[0]),
		.ADDRA(PORT_R2_ADDR),
		.ADDRB(PORT_R1_ADDR),
		.ADDRC(PORT_R0_ADDR),
		.ADDRD(PORT_RW_ADDR),
		.WE(PORT_RW_WR_EN),
		.WCLK(PORT_RW_CLK),
	);
else
	RAM64M8
	#(
		.INIT_H(init_slice(0)),
		.INIT_G(init_slice(0)),
		.INIT_F(init_slice(0)),
		.INIT_E(init_slice(0)),
		.INIT_D(init_slice(1)),
		.INIT_C(init_slice(1)),
		.INIT_B(init_slice(1)),
		.INIT_A(init_slice(1)),
	)
	_TECHMAP_REPLACE_
	(
		.DOA(PORT_R2_RD_DATA[1]),
		.DOB(PORT_R1_RD_DATA[1]),
		.DOC(PORT_R0_RD_DATA[1]),
		.DOD(PORT_RW_RD_DATA[1]),
		.DOE(PORT_R2_RD_DATA[0]),
		.DOF(PORT_R1_RD_DATA[0]),
		.DOG(PORT_R0_RD_DATA[0]),
		.DOH(PORT_RW_RD_DATA[0]),
		.DIA(PORT_RW_WR_DATA[1]),
		.DIB(PORT_RW_WR_DATA[1]),
		.DIC(PORT_RW_WR_DATA[1]),
		.DID(PORT_RW_WR_DATA[1]),
		.DIE(PORT_RW_WR_DATA[0]),
		.DIF(PORT_RW_WR_DATA[0]),
		.DIG(PORT_RW_WR_DATA[0]),
		.DIH(PORT_RW_WR_DATA[0]),
		.ADDRA(PORT_R2_ADDR),
		.ADDRB(PORT_R1_ADDR),
		.ADDRC(PORT_R0_ADDR),
		.ADDRD(PORT_RW_ADDR),
		.ADDRE(PORT_R2_ADDR),
		.ADDRF(PORT_R1_ADDR),
		.ADDRG(PORT_R0_ADDR),
		.ADDRH(PORT_RW_ADDR),
		.WE(PORT_RW_WR_EN),
		.WCLK(PORT_RW_CLK),
	);
default:
	$error("invalid OPTION_ABITS/WIDTH combination");
endcase
endgenerate

endmodule


module $__XILINX_LUTRAM_OP_ (...);

parameter INIT = 0;
parameter OPTION_ABITS = 5;
parameter WIDTH = 2;
parameter BITS_USED = 0;

output [WIDTH-1:0] PORT_RW_RD_DATA;
input [WIDTH-1:0] PORT_RW_WR_DATA;
input [OPTION_ABITS-1:0] PORT_RW_ADDR;
input PORT_RW_WR_EN;
input PORT_RW_CLK;

output [WIDTH-1:0] PORT_R0_RD_DATA;
input [OPTION_ABITS-1:0] PORT_R0_ADDR;
output [WIDTH-1:0] PORT_R1_RD_DATA;
input [OPTION_ABITS-1:0] PORT_R1_ADDR;
output [WIDTH-1:0] PORT_R2_RD_DATA;
input [OPTION_ABITS-1:0] PORT_R2_ADDR;
output [WIDTH-1:0] PORT_R3_RD_DATA;
input [OPTION_ABITS-1:0] PORT_R3_ADDR;
output [WIDTH-1:0] PORT_R4_RD_DATA;
input [OPTION_ABITS-1:0] PORT_R4_ADDR;
output [WIDTH-1:0] PORT_R5_RD_DATA;
input [OPTION_ABITS-1:0] PORT_R5_ADDR;
output [WIDTH-1:0] PORT_R6_RD_DATA;
input [OPTION_ABITS-1:0] PORT_R6_ADDR;

generate
case (OPTION_ABITS)
5:	RAM32M16
	#(
		.INIT_H(INIT),
		.INIT_G(INIT),
		.INIT_F(INIT),
		.INIT_E(INIT),
		.INIT_D(INIT),
		.INIT_C(INIT),
		.INIT_B(INIT),
		.INIT_A(INIT),
	)
	_TECHMAP_REPLACE_
	(
		.DOA(PORT_R6_RD_DATA),
		.DOB(PORT_R5_RD_DATA),
		.DOC(PORT_R4_RD_DATA),
		.DOD(PORT_R3_RD_DATA),
		.DOE(PORT_R2_RD_DATA),
		.DOF(PORT_R1_RD_DATA),
		.DOG(PORT_R0_RD_DATA),
		.DOH(PORT_RW_RD_DATA),
		.DIA(PORT_RW_WR_DATA),
		.DIB(PORT_RW_WR_DATA),
		.DIC(PORT_RW_WR_DATA),
		.DID(PORT_RW_WR_DATA),
		.DIE(PORT_RW_WR_DATA),
		.DIF(PORT_RW_WR_DATA),
		.DIG(PORT_RW_WR_DATA),
		.DIH(PORT_RW_WR_DATA),
		.ADDRA(PORT_R6_ADDR),
		.ADDRB(PORT_R5_ADDR),
		.ADDRC(PORT_R4_ADDR),
		.ADDRD(PORT_R3_ADDR),
		.ADDRE(PORT_R2_ADDR),
		.ADDRF(PORT_R1_ADDR),
		.ADDRG(PORT_R0_ADDR),
		.ADDRH(PORT_RW_ADDR),
		.WE(PORT_RW_WR_EN),
		.WCLK(PORT_RW_CLK),
	);
6:	RAM64M8
	#(
		.INIT_H(INIT),
		.INIT_G(INIT),
		.INIT_F(INIT),
		.INIT_E(INIT),
		.INIT_D(INIT),
		.INIT_C(INIT),
		.INIT_B(INIT),
		.INIT_A(INIT),
	)
	_TECHMAP_REPLACE_
	(
		.DOA(PORT_R6_RD_DATA),
		.DOB(PORT_R5_RD_DATA),
		.DOC(PORT_R4_RD_DATA),
		.DOD(PORT_R3_RD_DATA),
		.DOE(PORT_R2_RD_DATA),
		.DOF(PORT_R1_RD_DATA),
		.DOG(PORT_R0_RD_DATA),
		.DOH(PORT_RW_RD_DATA),
		.DIA(PORT_RW_WR_DATA),
		.DIB(PORT_RW_WR_DATA),
		.DIC(PORT_RW_WR_DATA),
		.DID(PORT_RW_WR_DATA),
		.DIE(PORT_RW_WR_DATA),
		.DIF(PORT_RW_WR_DATA),
		.DIG(PORT_RW_WR_DATA),
		.DIH(PORT_RW_WR_DATA),
		.ADDRA(PORT_R6_ADDR),
		.ADDRB(PORT_R5_ADDR),
		.ADDRC(PORT_R4_ADDR),
		.ADDRD(PORT_R3_ADDR),
		.ADDRE(PORT_R2_ADDR),
		.ADDRF(PORT_R1_ADDR),
		.ADDRG(PORT_R0_ADDR),
		.ADDRH(PORT_RW_ADDR),
		.WE(PORT_RW_WR_EN),
		.WCLK(PORT_RW_CLK),
	);
default:
	$error("invalid OPTION_ABITS/WIDTH combination");
endcase
endgenerate

endmodule


module $__XILINX_LUTRAM_SDP_ (...);

parameter INIT = 0;
parameter OPTION_ABITS = 5;
parameter WIDTH = 6;
parameter BITS_USED = 0;

input [WIDTH-1:0] PORT_W_WR_DATA;
input [OPTION_ABITS-1:0] PORT_W_ADDR;
input PORT_W_WR_EN;
input PORT_W_CLK;

output [WIDTH-1:0] PORT_R_RD_DATA;
input [OPTION_ABITS-1:0] PORT_R_ADDR;

function [(1 << OPTION_ABITS)-1:0] init_slice;
	input integer idx;
	integer i;
	for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
		init_slice[i] = INIT[i * WIDTH + idx];
endfunction

function [(2 << OPTION_ABITS)-1:0] init_slice2;
	input integer idx;
	integer i;
	for (i = 0; i < (1 << OPTION_ABITS); i = i + 1)
		init_slice2[2 * i +: 2] = INIT[i * WIDTH + idx * 2 +: 2];
endfunction

generate
case (OPTION_ABITS)
5: if (WIDTH == 6)
	RAM32M
	#(
		.INIT_C(init_slice2(0)),
		.INIT_B(init_slice2(1)),
		.INIT_A(init_slice2(2)),
	)
	_TECHMAP_REPLACE_
	(
		.DOA(PORT_R_RD_DATA[5:4]),
		.DOB(PORT_R_RD_DATA[3:2]),
		.DOC(PORT_R_RD_DATA[1:0]),
		.DIA(PORT_W_WR_DATA[5:4]),
		.DIB(PORT_W_WR_DATA[3:2]),
		.DIC(PORT_W_WR_DATA[1:0]),
		.ADDRA(PORT_R_ADDR),
		.ADDRB(PORT_R_ADDR),
		.ADDRC(PORT_R_ADDR),
		.ADDRD(PORT_W_ADDR),
		.WE(PORT_W_WR_EN),
		.WCLK(PORT_W_CLK),
	);
else
	RAM32M16
	#(
		.INIT_G(init_slice2(0)),
		.INIT_F(init_slice2(1)),
		.INIT_E(init_slice2(2)),
		.INIT_D(init_slice2(3)),
		.INIT_C(init_slice2(4)),
		.INIT_B(init_slice2(5)),
		.INIT_A(init_slice2(6)),
	)
	_TECHMAP_REPLACE_
	(
		.DOA(PORT_R_RD_DATA[13:12]),
		.DOB(PORT_R_RD_DATA[11:10]),
		.DOC(PORT_R_RD_DATA[9:8]),
		.DOD(PORT_R_RD_DATA[7:6]),
		.DOE(PORT_R_RD_DATA[5:4]),
		.DOF(PORT_R_RD_DATA[3:2]),
		.DOG(PORT_R_RD_DATA[1:0]),
		.DIA(PORT_W_WR_DATA[13:12]),
		.DIB(PORT_W_WR_DATA[11:10]),
		.DIC(PORT_W_WR_DATA[9:8]),
		.DID(PORT_W_WR_DATA[7:6]),
		.DIE(PORT_W_WR_DATA[5:4]),
		.DIF(PORT_W_WR_DATA[3:2]),
		.DIG(PORT_W_WR_DATA[1:0]),
		.ADDRA(PORT_R_ADDR),
		.ADDRB(PORT_R_ADDR),
		.ADDRC(PORT_R_ADDR),
		.ADDRD(PORT_R_ADDR),
		.ADDRE(PORT_R_ADDR),
		.ADDRF(PORT_R_ADDR),
		.ADDRG(PORT_R_ADDR),
		.ADDRH(PORT_W_ADDR),
		.WE(PORT_W_WR_EN),
		.WCLK(PORT_W_CLK),
	);
6: if (WIDTH == 3)
	RAM64M
	#(
		.INIT_C(init_slice(0)),
		.INIT_B(init_slice(1)),
		.INIT_A(init_slice(2)),
	)
	_TECHMAP_REPLACE_
	(
		.DOA(PORT_R_RD_DATA[2]),
		.DOB(PORT_R_RD_DATA[1]),
		.DOC(PORT_R_RD_DATA[0]),
		.DIA(PORT_W_WR_DATA[2]),
		.DIB(PORT_W_WR_DATA[1]),
		.DIC(PORT_W_WR_DATA[0]),
		.ADDRA(PORT_R_ADDR),
		.ADDRB(PORT_R_ADDR),
		.ADDRC(PORT_R_ADDR),
		.ADDRD(PORT_W_ADDR),
		.WE(PORT_W_WR_EN),
		.WCLK(PORT_W_CLK),
	);
else
	RAM64M8
	#(
		.INIT_G(init_slice(0)),
		.INIT_F(init_slice(1)),
		.INIT_E(init_slice(2)),
		.INIT_D(init_slice(3)),
		.INIT_C(init_slice(4)),
		.INIT_B(init_slice(5)),
		.INIT_A(init_slice(6)),
	)
	_TECHMAP_REPLACE_
	(
		.DOA(PORT_R_RD_DATA[6]),
		.DOB(PORT_R_RD_DATA[5]),
		.DOC(PORT_R_RD_DATA[4]),
		.DOD(PORT_R_RD_DATA[3]),
		.DOE(PORT_R_RD_DATA[2]),
		.DOF(PORT_R_RD_DATA[1]),
		.DOG(PORT_R_RD_DATA[0]),
		.DIA(PORT_W_WR_DATA[6]),
		.DIB(PORT_W_WR_DATA[5]),
		.DIC(PORT_W_WR_DATA[4]),
		.DID(PORT_W_WR_DATA[3]),
		.DIE(PORT_W_WR_DATA[2]),
		.DIF(PORT_W_WR_DATA[1]),
		.DIG(PORT_W_WR_DATA[0]),
		.ADDRA(PORT_R_ADDR),
		.ADDRB(PORT_R_ADDR),
		.ADDRC(PORT_R_ADDR),
		.ADDRD(PORT_R_ADDR),
		.ADDRE(PORT_R_ADDR),
		.ADDRF(PORT_R_ADDR),
		.ADDRG(PORT_R_ADDR),
		.ADDRH(PORT_W_ADDR),
		.WE(PORT_W_WR_EN),
		.WCLK(PORT_W_CLK),
	);
default:
	$error("invalid OPTION_ABITS/WIDTH combination");
endcase
endgenerate

endmodule


module $__XILINX_LUTRAM_64X8SW_ (...);

parameter INIT = 0;
parameter OPTION_ABITS = 9;
parameter PORT_RW_WR_WIDTH = 1;
parameter PORT_RW_RD_WIDTH = 8;

output [PORT_RW_RD_WIDTH-1:0] PORT_RW_RD_DATA;
input [PORT_RW_WR_WIDTH-1:0] PORT_RW_WR_DATA;
input [OPTION_ABITS-1:0] PORT_RW_ADDR;
input PORT_RW_WR_EN;
input PORT_RW_CLK;

function [63:0] init_slice;
	input integer idx;
	integer i;
	for (i = 0; i < 64; i = i + 1)
		init_slice[i] = INIT[i * 8 + idx];
endfunction

RAM64X8SW
#(
	.INIT_A(init_slice(7)),
	.INIT_B(init_slice(6)),
	.INIT_C(init_slice(5)),
	.INIT_D(init_slice(4)),
	.INIT_E(init_slice(3)),
	.INIT_F(init_slice(2)),
	.INIT_G(init_slice(1)),
	.INIT_H(init_slice(0)),
)
_TECHMAP_REPLACE_
(
	.A(PORT_RW_ADDR[8:3]),
	.WSEL(PORT_RW_ADDR[2:0]),
	.D(PORT_RW_WR_DATA),
	.O(PORT_RW_RD_DATA),
	.WE(PORT_RW_WR_EN),
	.WCLK(PORT_RW_CLK),
);

endmodule


module $__XILINX_LUTRAM_32X16DR8_ (...);

parameter OPTION_ABITS = 6;
parameter BITS_USED = 0;
parameter PORT_W_WIDTH = 14;
parameter PORT_R_WIDTH = 7;

input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
input [OPTION_ABITS-1:0] PORT_W_ADDR;
input PORT_W_WR_EN;
input PORT_W_CLK;

output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
input [OPTION_ABITS-1:0] PORT_R_ADDR;

RAM32X16DR8 _TECHMAP_REPLACE_
(
	.DOA(PORT_R_RD_DATA[6]),
	.DOB(PORT_R_RD_DATA[5]),
	.DOC(PORT_R_RD_DATA[4]),
	.DOD(PORT_R_RD_DATA[3]),
	.DOE(PORT_R_RD_DATA[2]),
	.DOF(PORT_R_RD_DATA[1]),
	.DOG(PORT_R_RD_DATA[0]),
	.DIA({PORT_W_WR_DATA[13], PORT_W_WR_DATA[6]}),
	.DIB({PORT_W_WR_DATA[12], PORT_W_WR_DATA[5]}),
	.DIC({PORT_W_WR_DATA[11], PORT_W_WR_DATA[4]}),
	.DID({PORT_W_WR_DATA[10], PORT_W_WR_DATA[3]}),
	.DIE({PORT_W_WR_DATA[9], PORT_W_WR_DATA[2]}),
	.DIF({PORT_W_WR_DATA[8], PORT_W_WR_DATA[1]}),
	.DIG({PORT_W_WR_DATA[7], PORT_W_WR_DATA[0]}),
	.ADDRA(PORT_R_ADDR),
	.ADDRB(PORT_R_ADDR),
	.ADDRC(PORT_R_ADDR),
	.ADDRD(PORT_R_ADDR),
	.ADDRE(PORT_R_ADDR),
	.ADDRF(PORT_R_ADDR),
	.ADDRG(PORT_R_ADDR),
	.ADDRH(PORT_W_ADDR[5:1]),
	.WE(PORT_W_WR_EN),
	.WCLK(PORT_W_CLK),
);

endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-12 10:23:02 +0000