/* * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Claire Xenia Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #ifndef COST_H #define COST_H #include "kernel/yosys.h" YOSYS_NAMESPACE_BEGIN struct CellCosts { static const dict& default_gate_cost() { static const dict db = { { ID($_BUF_), 1 }, { ID($_NOT_), 2 }, { ID($_AND_), 4 }, { ID($_NAND_), 4 }, { ID($_OR_), 4 }, { ID($_NOR_), 4 }, { ID($_ANDNOT_), 4 }, { ID($_ORNOT_), 4 }, { ID($_XOR_), 5 }, { ID($_XNOR_), 5 }, { ID($_AOI3_), 6 }, { ID($_OAI3_), 6 }, { ID($_AOI4_), 7 }, { ID($_OAI4_), 7 }, { ID($_MUX_), 4 }, { ID($_NMUX_), 4 } }; return db; } static const dict& cmos_gate_cost() { static const dict db = { { ID($_BUF_), 1 }, { ID($_NOT_), 2 }, { ID($_AND_), 6 }, { ID($_NAND_), 4 }, { ID($_OR_), 6 }, { ID($_NOR_), 4 }, { ID($_ANDNOT_), 6 }, { ID($_ORNOT_), 6 }, { ID($_XOR_), 12 }, { ID($_XNOR_), 12 }, { ID($_AOI3_), 6 }, { ID($_OAI3_), 6 }, { ID($_AOI4_), 8 }, { ID($_OAI4_), 8 }, { ID($_MUX_), 12 }, { ID($_NMUX_), 10 } }; return db; } dict mod_cost_cache; const dict *gate_cost = nullptr; Design *design = nullptr; int get(RTLIL::IdString type) const { if (gate_cost && gate_cost->count(type)) return gate_cost->at(type); log_warning("Can't determine cost of %s cell.\n", log_id(type)); return 1; } int get(RTLIL::Cell *cell) { if (gate_cost && gate_cost->count(cell->type)) return gate_cost->at(cell->type); if (design && design->module(cell->type) && cell->parameters.empty()) { RTLIL::Module *mod = design->module(cell->type); if (mod->attributes.count(ID(cost))) return mod->attributes.at(ID(cost)).as_int(); if (mod_cost_cache.count(mod->name)) return mod_cost_cache.at(mod->name); int module_cost = 1; for (auto c : mod->cells()) module_cost += get(c); mod_cost_cache[mod->name] = module_cost; return module_cost; } log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(cell->type), GetSize(cell->parameters)); return 1; } }; YOSYS_NAMESPACE_END #endif >1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

module \$__XILINX_RAM64X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
	parameter [63:0] INIT = 64'bx;
	parameter CLKPOL2 = 1;
	input CLK1;

	input [5:0] A1ADDR;
	output A1DATA;

	input [5:0] B1ADDR;
	input B1DATA;
	input B1EN;

	RAM64X1D #(
		.INIT(INIT),
		.IS_WCLK_INVERTED(!CLKPOL2)
	) _TECHMAP_REPLACE_ (
		.DPRA0(A1ADDR[0]),
		.DPRA1(A1ADDR[1]),
		.DPRA2(A1ADDR[2]),
		.DPRA3(A1ADDR[3]),
		.DPRA4(A1ADDR[4]),
		.DPRA5(A1ADDR[5]),
		.DPO(A1DATA),

		.A0(B1ADDR[0]),
		.A1(B1ADDR[1]),
		.A2(B1ADDR[2]),
		.A3(B1ADDR[3]),
		.A4(B1ADDR[4]),
		.A5(B1ADDR[5]),
		.D(B1DATA),
		.WCLK(CLK1),
		.WE(B1EN)
	);
endmodule

module \$__XILINX_RAM128X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
	parameter [127:0] INIT = 128'bx;
	parameter CLKPOL2 = 1;
	input CLK1;

	input [6:0] A1ADDR;
	output A1DATA;

	input [6:0] B1ADDR;
	input B1DATA;
	input B1EN;

	RAM128X1D #(
		.INIT(INIT),
		.IS_WCLK_INVERTED(!CLKPOL2)
	) _TECHMAP_REPLACE_ (
		.DPRA(A1ADDR),
		.DPO(A1DATA),

		.A(B1ADDR),
		.D(B1DATA),
		.WCLK(CLK1),
		.WE(B1EN)
	);
endmodule