/* * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ module VCC (output V); assign V = 1'b1; endmodule // VCC module GND (output G); assign G = 1'b0; endmodule // GND /* Altera MAX10 devices Input Buffer Primitive */ module fiftyfivenm_io_ibuf (output o, input i, input ibar); assign ibar = ibar; assign o = i; endmodule // fiftyfivenm_io_ibuf /* Altera MAX10 devices Output Buffer Primitive */ module fiftyfivenm_io_obuf (output o, input i, input oe); assign o = i; assign oe = oe; endmodule // fiftyfivenm_io_obuf /* Altera MAX10 4-input non-fracturable LUT Primitive */ module fiftyfivenm_lcell_comb (output combout, cout, input dataa, datab, datac, datad, cin); /* Internal parameters which define the behaviour of the LUT primitive. lut_mask define the lut function, can be expressed in 16-digit bin or hex. sum_lutc_input define the type of LUT (combinational | arithmetic). dont_touch for retiming || carry options. lpm_type for WYSIWYG */ parameter lut_mask = 16'hFFFF; parameter dont_touch = "off"; parameter lpm_type = "fiftyfivenm_lcell_comb"; parameter sum_lutc_input = "datac"; reg [1:0] lut_type; reg cout_rt; reg combout_rt; wire dataa_w; wire datab_w; wire datac_w; wire datad_w; wire cin_w; assign dataa_w = dataa; assign datab_w = datab; assign datac_w = datac; assign datad_w = datad; function lut_data; input [15:0] mask; input dataa, datab, datac, datad; reg [7:0] s3; reg [3:0] s2; reg [1:0] s1; begin s3 = datad ? mask[15:8] : mask[7:0]; s2 = datac ? s3[7:4] : s3[3:0]; s1 = datab ? s2[3:2] : s2[1:0]; lut_data = dataa ? s1[1] : s1[0]; end endfunction initial begin if (sum_lutc_input == "datac") lut_type = 0; else if (sum_lutc_input == "cin") lut_type = 1; else begin $error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input); $finish(); end end always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin if (lut_type == 0) begin // logic function combout_rt = lut_data(lut_mask, dataa_w, datab_w, datac_w, datad_w); end else if (lut_type == 1) begin // arithmetic function combout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, datad_w); end cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0); end assign combout = combout_rt & 1'b1; assign cout = cout_rt & 1'b1; endmodule // fiftyfivenm_lcell_comb /* Altera D Flip-Flop Primitive */ module dffeas (output q, input d, clk, clrn, prn, ena, input asdata, aload, sclr, sload); // Timing simulation is not covered parameter power_up="dontcare"; parameter is_wysiwyg="false"; reg q_tmp; wire reset; reg [7:0] debug_net; assign reset = (prn && sclr && ~clrn && ena); assign q = q_tmp & 1'b1; always @(posedge clk, posedge aload) begin if(reset) q_tmp <= 0; else q_tmp <= d; end assign q = q_tmp; endmodule // dffeas /* MAX10 altpll clearbox model */ (* blackbox *) module fiftyfivenm_pll (inclk, fbin, fbout, clkswitch, areset, pfdena, scanclk, scandata, scanclkena, configupdate, clk, phasecounterselect, phaseupdown, phasestep, clkbad, activeclock, locked, scandataout, scandone, phasedone, vcooverrange, vcounderrange); parameter operation_mode = "normal"; parameter pll_type = "auto"; parameter compensate_clock = "clock0"; parameter inclk0_input_frequency = 0; parameter inclk1_input_frequency = 0; parameter self_reset_on_loss_lock = "off"; parameter switch_over_type = "auto"; parameter switch_over_counter = 1; parameter enable_switch_over_counter = "off"; parameter bandwidth = 0; parameter bandwidth_type = "auto"; parameter use_dc_coupling = "false"; parameter lock_high = 0; parameter lock_low = 0; parameter lock_window_ui = "0.05"; parameter test_bypass_lock_detect = "off"; parameter clk0_output_frequency = 0; parameter clk0_multiply_by = 0; parameter clk0_divide_by = 0; parameter clk0_phase_shift = "0"; parameter clk0_duty_cycle = 50; parameter clk1_output_frequency = 0; parameter clk1_multiply_by = 0; parameter clk1_divide_by = 0; parameter clk1_phase_shift = "0"; parameter clk1_duty_cycle = 50; parameter clk2_output_frequency = 0; parameter clk2_multiply_by = 0; parameter clk2_divide_by = 0; parameter clk2_phase_shift = "0"; parameter clk2_duty_cycle = 50; parameter clk3_output_frequency = 0; parameter clk3_multiply_by = 0; parameter clk3_divide_by = 0; parameter clk3_phase_shift = "0"; parameter clk3_duty_cycle = 50; parameter clk4_output_frequency = 0; parameter clk4_multiply_by = 0; parameter clk4_divide_by = 0; parameter clk4_phase_shift = "0"; parameter clk4_duty_cycle = 50; parameter pfd_min = 0; parameter pfd_max = 0; parameter vco_min = 0; parameter vco_max = 0; parameter vco_center = 0; // Advanced user parameters parameter m_initi
/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
 *
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */
// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
// > Intel FPGA technology mapping. User must first simulate the generated \
// > netlist before going to test it on board.
// > Changelog: 1) The missing power_up parameter in the techmap introduces a problem in Quartus mapper. Fixed.

// Normal mode DFF negedge clk, negedge reset
module  \$_DFF_N_ (input D, C, output Q);
   parameter WYSIWYG="TRUE";
   parameter power_up=1'bx;
   dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Normal mode DFF
module  \$_DFF_P_ (input D, C, output Q);
   parameter WYSIWYG="TRUE";
   parameter power_up=1'bx;
   dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule

// Async Active Low Reset DFF
module  \$_DFF_PN0_ (input D, C, R, output Q);
   parameter WYSIWYG="TRUE";
   parameter power_up=1'bx;
   dffeas #(.is_wysiwyg(WYSIWYG), .power_up("power_up")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
// Async Active High Reset DFF
module  \$_DFF_PP0_ (input D, C, R, output Q);
   parameter WYSIWYG="TRUE";
   parameter power_up=1'bx;
   wire R_i = ~ R;
   dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule

module  \$__DFFE_PP0 (input D, C, E, R, output Q);
   parameter WYSIWYG="TRUE";
   parameter power_up=1'bx;
   wire E_i = ~ E;
   dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
endmodule

// Input buffer map
module \$__inpad (input I, output O);
   cycloneive_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
endmodule

// Output buffer map
module \$__outpad (input I, output O);
   cycloneive_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
endmodule

// LUT Map
/* 0 -> datac
 1 -> cin */
module \$lut (A, Y);
   parameter WIDTH  = 0;
   parameter LUT    = 0;
   input [WIDTH-1:0] A;
   output            Y;
   generate
      if (WIDTH == 1) begin
	 assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
      end else
        if (WIDTH == 2) begin
           cycloneive_lcell_comb #(.lut_mask({4{LUT}}),
                                   .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
                                                                                .dataa(A[0]),
                                                                                .datab(A[1]),
                                                                                .datac(1'b1),
                                                                                .datad(1'b1));
        end else
          if(WIDTH == 3) begin
	     cycloneive_lcell_comb #(.lut_mask({2{LUT}}),
                                     .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
                                                                                  .dataa(A[0]),
                                                                                  .datab(A[1]),
                                                                                  .datac(A[2]),
                                                                                  .datad(1'b1));
          end else
            if(WIDTH == 4) begin
	       cycloneive_lcell_comb #(.lut_mask(LUT),
                                       .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
                                                                                    .dataa(A[0]),
                                                                                    .datab(A[1]),
                                                                                    .datac(A[2]),
                                                                                    .datad(A[3]));
            end else
	             wire _TECHMAP_FAIL_ = 1;
   endgenerate

endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-10 14:59:55 +0000