Index: ioemu/Makefile.target
===================================================================
--- ioemu.orig/Makefile.target 2007-05-10 16:22:45.000000000 +0100
+++ ioemu/Makefile.target 2007-05-11 10:00:33.000000000 +0100
@@ -332,7 +332,7 @@
endif
# must use static linking to avoid leaving stuff in virtual address space
-VL_OBJS=vl.o osdep.o readline.o monitor.o pci.o console.o loader.o isa_mmio.o
+VL_OBJS=vl.o osdep.o readline.o monitor.o pci.o console.o isa_mmio.o
VL_OBJS+=cutils.o
VL_OBJS+=block.o block-raw.o
VL_OBJS+=block-cow.o block-qcow.o aes.o block-vmdk.o block-cloop.o block-dmg.o block-bochs.o block-vpc.o block-vvfat.o block-qcow2.o
Index: ioemu/configure
===================================================================
--- ioemu.orig/configure 2007-05-10 16:22:45.000000000 +0100
+++ ioemu/configure 2007-05-11 10:00:33.000000000 +0100
@@ -77,8 +77,8 @@
bigendian="no"
mingw32="no"
EXESUF=""
-gdbstub="yes"
-slirp="yes"
+gdbstub="no"
+slirp="no"
adlib="no"
oss="no"
dsound="no"
@@ -812,6 +812,8 @@
if expr $target : '.*-softmmu' > /dev/null ; then
target_softmmu="yes"
fi
+#for support 256M guest
+target_softmmu="yes"
target_user_only="no"
if expr $target : '.*-user' > /dev/null ; then
target_user_only="yes"
Index: ioemu/cpu-all.h
===================================================================
--- ioemu.orig/cpu-all.h 2007-05-10 16:22:44.000000000 +0100
+++ ioemu/cpu-all.h 2007-05-11 10:00:33.000000000 +0100
@@ -690,7 +690,9 @@
void page_set_flags(target_ulong start, target_ulong end, int flags);
void page_unprotect_range(target_ulong data, target_ulong data_size);
+#ifdef CONFIG_DM
#define SINGLE_CPU_DEFINES
+#endif
#ifdef SINGLE_CPU_DEFINES
#if defined(TARGET_I386)
@@ -752,6 +754,12 @@
#endif
+#else /* SINGLE_CPU_DEFINES */
+
+#define CPUState CPUX86State
+#define cpu_init cpu_x86_init
+int main_loop(void);
+
#endif /* SINGLE_CPU_DEFINES */
void cpu_dump_state(CPUState *env, FILE *f,
Index: ioemu/disas.h
===================================================================
--- ioemu.orig/disas.h 2007-05-10 16:22:44.000000000 +0100
+++ ioemu/disas.h 2007-05-10 16:22:45.000000000 +0100
@@ -1,6 +1,7 @@
#ifndef _QEMU_DISAS_H
#define _QEMU_DISAS_H
+#ifndef CONFIG_DM
/* Disassemble this for me please... (debugging). */
void disas(FILE *out, void *code, unsigned long size);
void target_disas(FILE *out, target_ulong code, target_ulong size, int flags);
@@ -17,5 +18,6 @@
const char *disas_strtab;
struct syminfo *next;
} *syminfos;
+#endif /* !CONFIG_DM */
#endif /* _QEMU_DISAS_H */
Index: ioemu/exec-all.h
===================================================================
--- ioemu.orig/exec-all.h 2007-05-10 16:22:44.000000000 +0100
+++ ioemu/exec-all.h 2007-05-11 10:00:54.000000000 +0100
@@ -519,7 +519,7 @@
extern int tb_invalidated_flag;
-#if !defined(CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY) && !defined(CONFIG_DM)
void tlb_fill(target_ulong addr, int is_write, int is_user,
void *retaddr);
@@ -546,7 +546,7 @@
#endif
-#if defined(CONFIG_USER_ONLY)
+#if defined(CONFIG_USER_ONLY) || defined(CONFIG_DM)
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
{
return addr;
Index: ioemu/hw/pc.c
===================================================================
--- ioemu.orig/hw/pc.c 2007-05-10 16:22:44.000000000 +0100
+++ ioemu/hw/pc.c 2007-05-11 10:00:33.000000000 +0100
@@ -74,6 +74,7 @@
}
}
+#ifndef CONFIG_DM
/* SMM support */
void cpu_smm_update(CPUState *env)
{
@@ -98,6 +99,7 @@
intno = pic_read_irq(isa_pic);
return intno;
}
+#endif /* CONFIG_DM */
static void pic_irq_request(void *opaque, int level)
{
@@ -463,12 +465,14 @@
/* init CPUs */
for(i = 0; i < smp_cpus; i++) {
env = cpu_init();
+#ifndef CONFIG_DM
if (i != 0)
env->hflags |= HF_HALTED_MASK;
if (smp_cpus > 1) {
/* XXX: enable it in all cases */
env->cpuid_features |= CPUID_APIC;
}
+#endif /* !CONFIG_DM */
register_savevm("cpu", i, 4, cpu_save, cpu_load, env);
qemu_register_reset(main_cpu_reset, env);
if (pci_enabled) {
@@ -541,6 +545,7 @@
bochs_bios_init();
+#ifndef CONFIG_DM
if (linux_boot) {
uint8_t bootsect[512];
uint8_t old_bootsect[512];
@@ -596,6 +601,7 @@
/* loader type */
stw_raw(phys_ram_base + KERNEL_PARAMS_ADDR + 0x210, 0x01);
}
+#endif /* !CONFIG_DM */
if (pci_enabled) {
pci_bus = i440fx_init(&i440fx_state);
@@ -639,9 +645,11 @@
isa_pic = pic_init(pic_irq_request, first_cpu);
pit = pit_init(0x40, 0);
pcspk_init(pit);
+#ifndef CONFIG_DM
if (pci_enabled) {
pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic);
}
+#endif /* !CONFIG_DM */
for(i = 0; i < MAX_SERIAL_PORTS; i++) {
if (serial_hds[i]) {
Index: ioemu/hw/vga_int.h
===================================================================
--- ioemu.orig/hw/vga_int.h 2007-05-10 16:22:44.000000000 +0100
+++ ioemu/hw/vga_int.h 2007-05-11 10:00:32.000000000 +0100
@@ -28,7 +28,7 @@
#define ST01_DISP_ENABLE 0x01
/* bochs VBE support */
-#define CONFIG_BOCHS_VBE
+//#define CONFIG_BOCHS_VBE
#define VBE_DISPI_MAX_XRES 1600
#define VBE_DISPI_MAX_YRES 1200
Index: ioemu/monitor.c
===================================================================
--- ioemu.orig/monitor.c 2007-05-10 16:22:44.000000000 +0100
+++ ioemu/monitor.c 2007-05-11 10:00:33.000000000 +0100
@@ -69,6 +69,12 @@
void term_flush(void)
{
+#ifdef CONFIG_DM
+ if (term_outbuf_index > 0 && !monitor_hd) {
+ fwrite(term_outbuf, term_outbuf_index, 1, stderr);
+ term_outbuf_index = 0;
+ }
+#endif
if (term_outbuf_index > 0) {
qemu_chr_write(monitor_hd, term_outbuf, term_outbuf_index);
term_outbuf_index = 0;
@@ -134,6 +140,7 @@
}
}
+#ifndef CONFIG_DM
static int monitor_fprintf(FILE *stream, const char *fmt, ...)
{
va_list ap;
@@ -142,6 +149,7 @@
va_end(ap);
return 0;
}
+#endif /* !CONFIG_DM */
static int compare_cmd(const char *name, const char *list)
{
@@ -258,6 +266,7 @@
return mon_cpu;
}
+#ifndef CONFIG_DM
static void do_info_registers(void)
{
CPUState *env;
@@ -311,6 +320,7 @@
{
dump_exec_info(NULL, monitor_fprintf);
}
+#endif /* !CONFIG_DM */
static void do_info_history (void)
{
@@ -408,6 +418,7 @@
cpu_set_log(mask);
}
+#ifndef CONFIG_DM
static void do_stop(void)
{
vm_stop(EXCP_INTERRUPT);
@@ -672,6 +683,7 @@
}
fclose(f);
}
+#endif /* !CONFIG_DM */
static void do_sum(uint32_t start, uint32_t size)
{
@@ -890,6 +902,7 @@
kbd_mouse_event(0, 0, 0, mouse_button_state);
}
+#ifndef CONFIG_DM
static void do_ioport_read(int count, int format, int size, int addr, int has_index, int index)
{
uint32_t val;
@@ -1080,6 +1093,7 @@
term_printf("kqemu support: not compiled\n");
#endif
}
+#endif /* !CONFIG_DM */
#ifdef CONFIG_PROFILER
@@ -1201,6 +1215,7 @@
"filename", "save screen into PPM image 'filename'" },
{ "log", "s", do_log,
"item1[,...]", "activate logging of the specified items to '/tmp/qemu.log'" },
+#ifndef CONFIG_DM
{ "savevm", "s?", do_savevm,
"tag|id", "save a VM snapshot. If no tag or id are provided, a new snapshot is created" },
{ "loadvm", "s", do_loadvm,
@@ -1223,21 +1238,26 @@
"/fmt expr", "print expression value (use $reg for CPU register access)", },
{ "i", "/ii.", do_ioport_read,
"/fmt addr", "I/O port read" },
+#endif/* !CONFIG_DM */
{ "sendkey", "s", do_send_key,
"keys", "send keys to the VM (e.g. 'sendkey ctrl-alt-f1')" },
+#ifndef CONFIG_DM
{ "system_reset", "", do_system_reset,
"", "reset the system" },
{ "system_powerdown", "", do_system_powerdown,
"", "send system power down event" },
+#endif /* !CONFIG_DM */
{ "sum", "ii", do_sum,
"addr size", "compute the checksum of a memory region" },
{ "usb_add", "s", do_usb_add,
"device", "add USB device (e.g. 'host:bus.addr' or 'host:vendor_id:product_id')" },
{ "usb_del", "s", do_usb_del,
"device", "remove USB device 'bus.addr'" },
+#ifndef CONFIG_DM
{ "cpu", "i", do_cpu_set,
"index", "set the default CPU" },
+#endif /* !CONFIG_DM */
{ "mouse_move", "sss?", do_mouse_move,
"dx dy [dz]", "send mouse move events" },
{ "mouse_button", "i", do_mouse_button,
@@ -1251,8 +1271,10 @@
#endif
{ "stopcapture", "i", do_stop_capture,
"capture index", "stop capture" },
+#ifndef CONFIG_DM
{ "memsave", "lis", do_memory_save,
"addr size file", "save to disk virtual memory dump starting at 'addr' of size 'size'", },
+#endif /* !CONFIG_DM */
{ NULL, NULL, },
};
@@ -1263,10 +1285,12 @@
"", "show the network state" },
{ "block", "", do_info_block,
"", "show the block devices" },
+#ifndef CONFIG_DM
{ "registers", "", do_info_registers,
"", "show the cpu registers" },
{ "cpus", "", do_info_cpus,
"", "show infos for each CPU" },
+#endif /* !CONFIG_DM */
{ "history", "", do_info_history,
"", "show the command line history", },
{ "irq", "", irq_info,
@@ -1275,6 +1299,7 @@
"", "show i8259 (PIC) state", },
{ "pci", "", pci_info,
"", "show PCI info", },
+#ifndef CONFIG_DM
#if defined(TARGET_I386)
{ "tlb", "", tlb_info,
"", "show virtual to physical memory mappings", },
@@ -1285,6 +1310,7 @@
"", "show dynamic compiler info", },
{ "kqemu", "", do_info_kqemu,
"", "show kqemu information", },
+#endif /* !CONFIG_DM */
{ "usb", "", usb_info,
"", "show guest USB devices", },
{ "usbhost", "", usb_host_info,
@@ -1304,6 +1330,7 @@
/*******************************************************************/
+#ifndef CONFIG_DM
static const char *pch;
static jmp_buf expr_env;
@@ -1847,6 +1874,7 @@
*pp = pch;
return 0;
}
+#endif /* !CONFIG_DM */
static int get_str(char *buf, int buf_size, const char **pp)
{
@@ -1913,8 +1941,10 @@
return 0;
}
+#ifndef CONFIG_DM
static int default_fmt_format = 'x';
static int default_fmt_size = 4;
+#endif /* !CONFIG_DM */
#define MAX_ARGS 16
@@ -1922,7 +1952,10 @@
{
const char *p, *pstart, *typestr;
char *q;
- int c, nb_args, len, i, has_arg;
+ int c, nb_args, len, i;
+#ifndef CONFIG_DM
+ int has_arg;
+#endif /* !CONFIG_DM */
term_cmd_t *cmd;
char cmdname[256];
char buf[1024];
@@ -2014,6 +2047,7 @@
args[nb_args++] = str;
}
break;
+#ifndef CONFIG_DM
case '/':
{
int count, format, size;
@@ -2146,6 +2180,7 @@
}
}
break;
+#endif /* !CONFIG_DM */
case '-':
{
int has_option;
@@ -2172,6 +2207,11 @@
args[nb_args++] = (void *)has_option;
}
break;
+#ifdef CONFIG_DM
+ /* TODO: add more commands we need here to support hvm device model */
+ case '/':
+ case 'i':
+#endif /* CONFIG_DM */
default:
bad_type:
term_printf("%s: unknown type '%c'\n", cmdname, c);
@@ -2222,6 +2262,7 @@
return;
}
+#ifndef CONFIG_DM
static void cmd_completion(const char *name, const char *list)
{
const char *p, *pstart;
@@ -2415,6 +2456,11 @@
for(i = 0; i < nb_args; i++)
qemu_free(args[i]);
}
+#else
+void readline_find_completion(const char *cmdline)
+{
+}
+#endif /* !CONFIG_DM */
static int term_can_read(void *opaque)
{
Index: ioemu/vl.c
===================================================================
--- ioemu.orig/vl.c 2007-05-10 16:22:44.000000000 +0100
+++ ioemu/vl.c 2007-05-11 10:00:33.000000000 +0100
@@ -396,12 +396,15 @@
void hw_error(const char *fmt, ...)
{
va_list ap;
+#ifndef CONFIG_DM
CPUState *env;
+#endif /* !CONFIG_DM */
va_start(ap, fmt);
fprintf(stderr, "qemu: hardware error: ");
vfprintf(stderr, fmt, ap);
fprintf(stderr, "\n");
+#ifndef CONFIG_DM
for(env = first_cpu; env != NULL; env = env->next_cpu) {
fprintf(stderr, "CPU #%d:\n", env->cpu_index);
#ifdef TARGET_I386
@@ -410,6 +413,7 @@
cpu_dump_state(env, stderr, fprintf, 0);
#endif
}
+#endif /* !CONFIG_DM */
va_end(ap);
abort();
}
@@ -4953,6 +4957,7 @@
qemu_free(sn_tab);
}
+#ifndef CONFIG_DM
/***********************************************************/
/* cpu save/restore */
@@ -5582,6 +5587,25 @@
ram_decompress_close(s);
return 0;
}
+#else /* CONFIG_DM */
+void cpu_save(QEMUFile *f, void *opaque)
+{
+}
+
+int cpu_load(QEMUFile *f, void *opaque, int version_id)
+{
+ return 0;
+}
+
+static void ram_save(QEMUFile *f, void *opaque)
+{
+}
+
+static int ram_load(QEMUFile *f, void *opaque, int version_id)
+{
+ return 0;
+}
+#endif /* CONFIG_DM */
/***********************************************************/
/* bottom halves (can be seen as timers which expire ASAP) */
@@ -6580,15 +6604,19 @@
#endif
cyls = heads = secs = 0;
translation = BIOS_ATA_TRANSLATION_AUTO;
- pstrcpy(monitor_device, sizeof(monitor_device), "vc");
+ pstrcpy(monitor_device, sizeof(monitor_device), "null");
- pstrcpy(serial_devices[0], sizeof(serial_devices[0]), "vc");
- for(i = 1; i < MAX_SERIAL_PORTS; i++)
+ for(i = 0; i < MAX_SERIAL_PORTS; i++)
serial_devices[i][0] = '\0';
serial_device_index = 0;
-
+
+#ifndef CONFIG_DM
pstrcpy(parallel_devices[0], sizeof(parallel_devices[0]), "vc");
for(i = 1; i < MAX_PARALLEL_PORTS; i++)
+#else
+ /* Xen steals IRQ7 for PCI. Disable LPT1 by default. */
+ for(i = 0; i < MAX_PARALLEL_PORTS; i++)
+#endif
parallel_devices[i][0] = '\0';
parallel_device_index = 0;
@@ -7040,6 +7068,7 @@
socket_init();
#endif
+#ifndef CONFIG_DM
/* init network clients */
if (nb_net_clients == 0) {
/* if no clients, we use a default config */
@@ -7049,6 +7078,7 @@
"user");
nb_net_clients = 2;
}
+#endif /* !CONFIG_DM */
for(i = 0;i < nb_net_clients; i++) {
if (net_client_init(net_clients[i]) < 0)
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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/register.h"
#include "kernel/log.h"
#include <sstream>
#include <set>
#include <stdlib.h>
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct MemoryMapWorker
{
RTLIL::Design *design;
RTLIL::Module *module;
std::map<std::pair<RTLIL::SigSpec, RTLIL::SigSpec>, RTLIL::SigBit> decoder_cache;
std::string genid(RTLIL::IdString name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "")
{
std::stringstream sstr;
sstr << "$memory" << name.str() << token1;
if (i >= 0)
sstr << "[" << i << "]";
sstr << token2;
if (j >= 0)
sstr << "[" << j << "]";
sstr << token3;
if (k >= 0)
sstr << "[" << k << "]";
sstr << token4 << "$" << (autoidx++);
return sstr.str();
}
RTLIL::Wire *addr_decode(RTLIL::SigSpec addr_sig, RTLIL::SigSpec addr_val)
{
std::pair<RTLIL::SigSpec, RTLIL::SigSpec> key(addr_sig, addr_val);
log_assert(GetSize(addr_sig) == GetSize(addr_val));
if (decoder_cache.count(key) == 0) {
if (GetSize(addr_sig) < 2) {
decoder_cache[key] = module->Eq(NEW_ID, addr_sig, addr_val);
} else {
int split_at = GetSize(addr_sig) / 2;
RTLIL::SigBit left_eq = addr_decode(addr_sig.extract(0, split_at), addr_val.extract(0, split_at));
RTLIL::SigBit right_eq = addr_decode(addr_sig.extract(split_at, GetSize(addr_sig) - split_at), addr_val.extract(split_at, GetSize(addr_val) - split_at));
decoder_cache[key] = module->And(NEW_ID, left_eq, right_eq);
}
}
RTLIL::SigBit bit = decoder_cache.at(key);
log_assert(bit.wire != nullptr && GetSize(bit.wire) == 1);
return bit.wire;
}
void handle_cell(RTLIL::Cell *cell)
{
std::set<int> static_ports;
std::map<int, RTLIL::SigSpec> static_cells_map;
int wr_ports = cell->parameters["\\WR_PORTS"].as_int();
int rd_ports = cell->parameters["\\RD_PORTS"].as_int();
int mem_size = cell->parameters["\\SIZE"].as_int();
int mem_width = cell->parameters["\\WIDTH"].as_int();
int mem_offset = cell->parameters["\\OFFSET"].as_int();
int mem_abits = cell->parameters["\\ABITS"].as_int();
SigSpec init_data = cell->getParam("\\INIT");
init_data.extend_u0(mem_size*mem_width, true);
// delete unused memory cell
if (wr_ports == 0 && rd_ports == 0) {
module->remove(cell);
return;
}
// all write ports must share the same clock
RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK");
RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"];
RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"];
clocks_pol.bits.resize(wr_ports);
clocks_en.bits.resize(wr_ports);
RTLIL::SigSpec refclock;
RTLIL::State refclock_pol = RTLIL::State::Sx;
for (int i = 0; i < clocks.size(); i++) {
RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(i * mem_width, mem_width);
if (wr_en.is_fully_const() && !wr_en.as_bool()) {
static_ports.insert(i);
continue;
}
if (clocks_en.bits[i] != RTLIL::State::S1) {
RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(i*mem_abits, mem_abits);
RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(i*mem_width, mem_width);
if (wr_addr.is_fully_const()) {
// FIXME: Actually we should check for wr_en.is_fully_const() also and
// create a $adff cell with this ports wr_en input as reset pin when wr_en
// is not a simple static 1.
static_cells_map[wr_addr.as_int() - mem_offset] = wr_data;
static_ports.insert(i);
continue;
}
log("Not mapping memory cell %s in module %s (write port %d has no clock).\n",
cell->name.c_str(), module->name.c_str(), i);
return;
}
if (refclock.size() == 0) {
refclock = clocks.extract(i, 1);
refclock_pol = clocks_pol.bits[i];
}
if (clocks.extract(i, 1) != refclock || clocks_pol.bits[i] != refclock_pol) {
log("Not mapping memory cell %s in module %s (write clock %d is incompatible with other clocks).\n",
cell->name.c_str(), module->name.c_str(), i);
return;
}
}
log("Mapping memory cell %s in module %s:\n", cell->name.c_str(), module->name.c_str());
std::vector<RTLIL::SigSpec> data_reg_in;
std::vector<RTLIL::SigSpec> data_reg_out;
int count_static = 0;
for (int i = 0; i < mem_size; i++)
{
if (static_cells_map.count(i) > 0)
{
data_reg_in.push_back(RTLIL::SigSpec(RTLIL::State::Sz, mem_width));
data_reg_out.push_back(static_cells_map[i]);
count_static++;
}
else
{
RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), "$dff");
c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
if (clocks_pol.bits.size() > 0) {
c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]);
c->setPort("\\CLK", clocks.extract(0, 1));
} else {
c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1);
c->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::S0));
}
RTLIL::Wire *w_in = module->addWire(genid(cell->name, "", i, "$d"), mem_width);
data_reg_in.push_back(RTLIL::SigSpec(w_in));
c->setPort("\\D", data_reg_in.back());
std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i);
if (module->wires_.count(w_out_name) > 0)
w_out_name = genid(cell->name, "", i, "$q");
RTLIL::Wire *w_out = module->addWire(w_out_name, mem_width);
SigSpec w_init = init_data.extract(i*mem_width, mem_width);
if (!w_init.is_fully_undef())
w_out->attributes["\\init"] = w_init.as_const();
data_reg_out.push_back(RTLIL::SigSpec(w_out));
c->setPort("\\Q", data_reg_out.back());
}
}
log(" created %d $dff cells and %d static cells of width %d.\n", mem_size-count_static, count_static, mem_width);
int count_dff = 0, count_mux = 0, count_wrmux = 0;
for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++)
{
RTLIL::SigSpec rd_addr = cell->getPort("\\RD_ADDR").extract(i*mem_abits, mem_abits);
if (mem_offset)
rd_addr = module->Sub(NEW_ID, rd_addr, SigSpec(mem_offset, GetSize(rd_addr)));
std::vector<RTLIL::SigSpec> rd_signals;
rd_signals.push_back(cell->getPort("\\RD_DATA").extract(i*mem_width, mem_width));
if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1)
{
if (cell->parameters["\\RD_TRANSPARENT"].bits[i] == RTLIL::State::S1)
{
RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits);
c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
c->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1));
c->setPort("\\D", rd_addr);
count_dff++;
RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$q"), mem_abits);
c->setPort("\\Q", RTLIL::SigSpec(w));
rd_addr = RTLIL::SigSpec(w);
}
else
{
RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
c->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1));
c->setPort("\\Q", rd_signals.back());
count_dff++;
RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$d"), mem_width);
rd_signals.clear();
rd_signals.push_back(RTLIL::SigSpec(w));
c->setPort("\\D", rd_signals.back());
}
}
for (int j = 0; j < mem_abits; j++)
{
std::vector<RTLIL::SigSpec> next_rd_signals;
for (size_t k = 0; k < rd_signals.size(); k++)
{
RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux");
c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
c->setPort("\\Y", rd_signals[k]);
c->setPort("\\S", rd_addr.extract(mem_abits-j-1, 1));
count_mux++;
c->setPort("\\A", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width));
c->setPort("\\B", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width));
next_rd_signals.push_back(c->getPort("\\A"));
next_rd_signals.push_back(c->getPort("\\B"));
}
next_rd_signals.swap(rd_signals);
}
for (int j = 0; j < mem_size; j++)
module->connect(RTLIL::SigSig(rd_signals[j], data_reg_out[j]));
}
log(" read interface: %d $dff and %d $mux cells.\n", count_dff, count_mux);
for (int i = 0; i < mem_size; i++)
{
if (static_cells_map.count(i) > 0)
continue;
RTLIL::SigSpec sig = data_reg_out[i];
for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++)
{
RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(j*mem_abits, mem_abits);
RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(j*mem_width, mem_width);
RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(j*mem_width, mem_width);
if (mem_offset)
wr_addr = module->Sub(NEW_ID, wr_addr, SigSpec(mem_offset, GetSize(wr_addr)));
RTLIL::Wire *w_seladdr = addr_decode(wr_addr, RTLIL::SigSpec(i, mem_abits));
int wr_offset = 0;
while (wr_offset < wr_en.size())
{
int wr_width = 1;
RTLIL::SigSpec wr_bit = wr_en.extract(wr_offset, 1);
while (wr_offset + wr_width < wr_en.size()) {
RTLIL::SigSpec next_wr_bit = wr_en.extract(wr_offset + wr_width, 1);
if (next_wr_bit != wr_bit)
break;
wr_width++;
}
RTLIL::Wire *w = w_seladdr;
if (wr_bit != RTLIL::SigSpec(1, 1))
{
RTLIL::Cell *c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and");
c->parameters["\\A_SIGNED"] = RTLIL::Const(0);
c->parameters["\\B_SIGNED"] = RTLIL::Const(0);
c->parameters["\\A_WIDTH"] = RTLIL::Const(1);
c->parameters["\\B_WIDTH"] = RTLIL::Const(1);
c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
c->setPort("\\A", w);
c->setPort("\\B", wr_bit);
w = module->addWire(genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y"));
c->setPort("\\Y", RTLIL::SigSpec(w));
}
RTLIL::Cell *c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux");
c->parameters["\\WIDTH"] = wr_width;
c->setPort("\\A", sig.extract(wr_offset, wr_width));
c->setPort("\\B", wr_data.extract(wr_offset, wr_width));
c->setPort("\\S", RTLIL::SigSpec(w));
w = module->addWire(genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"), wr_width);
c->setPort("\\Y", w);
sig.replace(wr_offset, w);
wr_offset += wr_width;
count_wrmux++;
}
}
module->connect(RTLIL::SigSig(data_reg_in[i], sig));
}
log(" write interface: %d write mux blocks.\n", count_wrmux);
module->remove(cell);
}
MemoryMapWorker(RTLIL::Design *design, RTLIL::Module *module) : design(design), module(module)
{
std::vector<RTLIL::Cell*> cells;
for (auto cell : module->selected_cells())
if (cell->type == "$mem" && design->selected(module, cell))
cells.push_back(cell);
for (auto cell : cells)
handle_cell(cell);
}
};
struct MemoryMapPass : public Pass {
MemoryMapPass() : Pass("memory_map", "translate multiport memories to basic cells") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" memory_map [selection]\n");
log("\n");
log("This pass converts multiport memory cells as generated by the memory_collect\n");
log("pass to word-wide DFFs and address decoders.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n");
extra_args(args, 1, design);
for (auto mod : design->selected_modules())
MemoryMapWorker(design, mod);
}
} MemoryMapPass;
PRIVATE_NAMESPACE_END
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