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<div class='path'>path: <a href='/cgit.cgi/openwrt/upstream/commit/?id=470442ea0fb78333c92bea8e62a87a0cfaa6ba8c'>root</a>/<a href='/cgit.cgi/openwrt/upstream/commit/include?id=470442ea0fb78333c92bea8e62a87a0cfaa6ba8c'>include</a></div><div class='content'><div class='cgit-panel'><b>diff options</b><form method='get'><input type='hidden' name='id' value='470442ea0fb78333c92bea8e62a87a0cfaa6ba8c'/><table><tr><td colspan='2'/></tr><tr><td class='label'>context:</td><td class='ctrl'><select name='context' onchange='this.form.submit();'><option value='1'>1</option><option value='2'>2</option><option value='3' selected='selected'>3</option><option value='4'>4</option><option value='5'>5</option><option value='6'>6</option><option value='7'>7</option><option value='8'>8</option><option value='9'>9</option><option value='10'>10</option><option value='15'>15</option><option value='20'>20</option><option value='25'>25</option><option value='30'>30</option><option value='35'>35</option><option value='40'>40</option></select></td></tr><tr><td class='label'>space:</td><td class='ctrl'><select name='ignorews' onchange='this.form.submit();'><option value='0' selected='selected'>include</option><option value='1'>ignore</option></select></td></tr><tr><td class='label'>mode:</td><td class='ctrl'><select name='dt' onchange='this.form.submit();'><option value='0' selected='selected'>unified</option><option value='1'>ssdiff</option><option value='2'>stat only</option></select></td></tr><tr><td/><td class='ctrl'><noscript><input type='submit' value='reload'/></noscript></td></tr></table></form></div><table summary='commit info' class='commit-info'>
<tr><th>author</th><td>Felix Fietkau &lt;nbd@nbd.name&gt;</td><td class='right'>2016-05-16 11:20:17 +0200</td></tr>
<tr><th>committer</th><td>Felix Fietkau &lt;nbd@nbd.name&gt;</td><td class='right'>2016-05-16 11:20:26 +0200</td></tr>
<tr><th>commit</th><td colspan='2' class='sha1'><a href='/cgit.cgi/openwrt/upstream/commit/include?id=470442ea0fb78333c92bea8e62a87a0cfaa6ba8c'>470442ea0fb78333c92bea8e62a87a0cfaa6ba8c</a> (<a href='/cgit.cgi/openwrt/upstream/patch/include?id=470442ea0fb78333c92bea8e62a87a0cfaa6ba8c'>patch</a>)</td></tr>
<tr><th>tree</th><td colspan='2' class='sha1'><a href='/cgit.cgi/openwrt/upstream/tree/?id=470442ea0fb78333c92bea8e62a87a0cfaa6ba8c'>5589a92003a85e6b0ad29ef737aa2a7b5ff957bc</a> /<a href='/cgit.cgi/openwrt/upstream/tree/include?id=470442ea0fb78333c92bea8e62a87a0cfaa6ba8c'>include</a></td></tr>
<tr><th>parent</th><td colspan='2' class='sha1'><a href='/cgit.cgi/openwrt/upstream/commit/include?id=34b05087f73dce512dd6df9f1b755bc70fd5b74a'>34b05087f73dce512dd6df9f1b755bc70fd5b74a</a> (<a href='/cgit.cgi/openwrt/upstream/diff/include?id=470442ea0fb78333c92bea8e62a87a0cfaa6ba8c&amp;id2=34b05087f73dce512dd6df9f1b755bc70fd5b74a'>diff</a>)</td></tr><tr><th>download</th><td colspan='2' class='sha1'><a href='/cgit.cgi/openwrt/upstream/snapshot/upstream-470442ea0fb78333c92bea8e62a87a0cfaa6ba8c.tar.gz'>upstream-470442ea0fb78333c92bea8e62a87a0cfaa6ba8c.tar.gz</a><br/><a href='/cgit.cgi/openwrt/upstream/snapshot/upstream-470442ea0fb78333c92bea8e62a87a0cfaa6ba8c.tar.bz2'>upstream-470442ea0fb78333c92bea8e62a87a0cfaa6ba8c.tar.bz2</a><br/><a href='/cgit.cgi/openwrt/upstream/snapshot/upstream-470442ea0fb78333c92bea8e62a87a0cfaa6ba8c.zip'>upstream-470442ea0fb78333c92bea8e62a87a0cfaa6ba8c.zip</a><br/></td></tr></table>
<div class='commit-subject'>build: fix make download in the SDK</div><div class='commit-msg'>Signed-off-by: Felix Fietkau &lt;nbd@nbd.name&gt;
</div><div class='diffstat-header'><a href='/cgit.cgi/openwrt/upstream/diff/?id=470442ea0fb78333c92bea8e62a87a0cfaa6ba8c'>Diffstat</a> (limited to 'include')</div><table summary='diffstat' class='diffstat'><tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit.cgi/openwrt/upstream/diff/include/toplevel.mk?id=470442ea0fb78333c92bea8e62a87a0cfaa6ba8c'>include/toplevel.mk</a></td><td class='right'>11</td><td class='graph'><table summary='file diffstat' width='11%'><tr><td class='add' style='width: 63.6%;'/><td class='rem' style='width: 36.4%;'/><td class='none' style='width: 0.0%;'/></tr></table></td></tr>
</table><div class='diffstat-summary'>1 files changed, 7 insertions, 4 deletions</div><table summary='diff' class='diff'><tr><td><div class='head'>diff --git a/include/toplevel.mk b/include/toplevel.mk<br/>index 535ac0e065..7ef5c6186a 100644<br/>--- a/<a href='/cgit.cgi/openwrt/upstream/tree/include/toplevel.mk?id=34b05087f73dce512dd6df9f1b755bc70fd5b74a'>include/toplevel.mk</a><br/>+++ b/<a href='/cgit.cgi/openwrt/upstream/tree/include/toplevel.mk?id=470442ea0fb78333c92bea8e62a87a0cfaa6ba8c'>include/toplevel.mk</a></div><div class='hunk'>@@ -165,11 +165,14 @@ staging_dir/host/.prereq-build: include/prereq-build.mk</div><div class='ctx'> printdb: FORCE</div><div class='ctx'> 	@$(_SINGLE)$(NO_TRACE_MAKE) -p $@ V=99 DUMP_TARGET_DB=1 2&gt;&amp;1</div><div class='ctx'> </div><div class='add'>+ifndef SDK</div><div class='add'>+  DOWNLOAD_DIRS = tools/download toolchain/download package/download target/download</div><div class='add'>+else</div><div class='add'>+  DOWNLOAD_DIRS = package/download</div><div class='add'>+endif</div><div class='add'>+</div><div class='ctx'> download: .config FORCE</div><div class='del'>-	@+$(SUBMAKE) tools/download</div><div class='del'>-	@+$(SUBMAKE) toolchain/download</div><div class='del'>-	@+$(SUBMAKE) package/download</div><div class='del'>-	@+$(SUBMAKE) target/download</div><div class='add'>+	@+$(foreach dir,$(DOWNLOAD_DIRS),$(SUBMAKE) $(dir);)</div><div class='ctx'> </div><div class='ctx'> clean dirclean: .config</div><div class='ctx'> 	@+$(SUBMAKE) -r $@</div></td></tr></table></div> <!-- class=content -->
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</pre></td>
<td class='lines'><pre><code><style>pre { line-height: 125%; margin: 0; }
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.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */</style><div class="highlight"><pre><span></span><span class="k">\documentclass</span><span class="na">[oneside,a4paper]</span><span class="nb">{</span>book<span class="nb">}</span>

<span class="k">\usepackage</span><span class="na">[T1]</span><span class="nb">{</span>fontenc<span class="nb">}</span>   <span class="c">% required for luximono!</span>
<span class="k">\usepackage</span><span class="nb">{</span>lmodern<span class="nb">}</span>
<span class="k">\usepackage</span><span class="na">[scaled=0.8]</span><span class="nb">{</span>luximono<span class="nb">}</span>  <span class="c">% typewriter font with bold face</span>

<span class="c">% To install the luximono font files:</span>
<span class="c">% getnonfreefonts-sys --all        or</span>
<span class="c">% getnonfreefonts-sys luximono</span>
<span class="c">%</span>
<span class="c">% when there are trouble you might need to:</span>
<span class="c">% - Create /etc/texmf/updmap.d/99local-luximono.cfg</span>
<span class="c">%   containing the single line: Map ul9.map</span>
<span class="c">% - Run update-updmap followed by mktexlsr and updmap-sys</span>
<span class="c">%</span>
<span class="c">% This commands must be executed as root with a root environment</span>
<span class="c">% (i.e. run &quot;sudo su&quot; and then execute the commands in the root</span>
<span class="c">% shell, don&#39;t just prefix the commands with &quot;sudo&quot;).</span>

<span class="c">% formats the text according the set language</span>
<span class="k">\usepackage</span><span class="na">[english]</span><span class="nb">{</span>babel<span class="nb">}</span>
<span class="k">\usepackage</span><span class="na">[table,usenames]</span><span class="nb">{</span>xcolor<span class="nb">}</span>
<span class="c">% generates indices with the &quot;\index&quot; command</span>
<span class="k">\usepackage</span><span class="nb">{</span>makeidx<span class="nb">}</span>
<span class="c">% enables import of graphics. We use pdflatex here so do the pdf optimisation.</span>
<span class="c">%\usepackage[dvips]{graphicx}</span>
<span class="k">\usepackage</span><span class="na">[pdftex]</span><span class="nb">{</span>graphicx<span class="nb">}</span>
<span class="k">\usepackage</span><span class="nb">{</span>pdfpages<span class="nb">}</span>
<span class="c">% includes floating objects like tables and figures.</span>
<span class="k">\usepackage</span><span class="nb">{</span>float<span class="nb">}</span>
<span class="c">% for generating subfigures with ohne indented captions</span>
<span class="k">\usepackage</span><span class="na">[hang]</span><span class="nb">{</span>subfigure<span class="nb">}</span>
<span class="c">% redefines and smartens captions of figures and tables (indentation, smaller and boldface)</span>
<span class="k">\usepackage</span><span class="na">[hang,small,bf,center]</span><span class="nb">{</span>caption<span class="nb">}</span>
<span class="c">% enables tabstops and the numeration of lines</span>
<span class="k">\usepackage</span><span class="nb">{</span>moreverb<span class="nb">}</span>
<span class="c">% enables user defined header and footer lines (former &quot;fancyheadings&quot;)</span>
<span class="k">\usepackage</span><span class="nb">{</span>fancyhdr<span class="nb">}</span>
<span class="c">% Some smart mathematical stuff</span>
<span class="k">\usepackage</span><span class="nb">{</span>amsmath<span class="nb">}</span>
<span class="c">% Package for rotating several objects</span>
<span class="k">\usepackage</span><span class="nb">{</span>rotating<span class="nb">}</span>
<span class="k">\usepackage</span><span class="nb">{</span>natbib<span class="nb">}</span>
<span class="k">\usepackage</span><span class="nb">{</span>epsf<span class="nb">}</span>
<span class="k">\usepackage</span><span class="nb">{</span>dsfont<span class="nb">}</span>
<span class="k">\usepackage</span><span class="na">[algochapter, boxruled, vlined]</span><span class="nb">{</span>algorithm2e<span class="nb">}</span>
<span class="c">%Activating and setting of character protruding - if you like</span>
<span class="c">%\usepackage[activate,DVIoutput]{pdfcprot}</span>
<span class="c">% If you really need special chars...</span>
<span class="k">\usepackage</span><span class="na">[latin1]</span><span class="nb">{</span>inputenc<span class="nb">}</span>
<span class="c">% Hyperlinks</span>
<span class="k">\usepackage</span>[colorlinks,hyperindex,plainpages=false,<span class="c">%</span>
pdftitle=<span class="nb">{</span>Yosys Manual<span class="nb">}</span>,<span class="c">%</span>
pdfauthor=<span class="nb">{</span>Clifford Wolf<span class="nb">}</span>,<span class="c">%</span>
<span class="c">%pdfkeywords={keyword},%</span>
pdfpagelabels,<span class="c">%</span>
pagebackref,<span class="c">%</span>
bookmarksopen=false<span class="c">%</span>
]<span class="nb">{</span>hyperref<span class="nb">}</span>
<span class="c">% For the two different reference lists ...</span>
<span class="k">\usepackage</span><span class="nb">{</span>multibib<span class="nb">}</span>
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<span class="k">\begin</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\bf\Huge</span> Yosys Manual

<span class="k">\bigskip</span>
<span class="k">\large</span> Clifford Wolf
<span class="k">\end</span><span class="nb">{</span>center<span class="nb">}</span>

<span class="k">\vfil\null</span>
<span class="k">\eject</span>

<span class="k">\chapter*</span><span class="nb">{</span>Abstract<span class="nb">}</span>
Most of today&#39;s digital design is done in HDL code (mostly Verilog or VHDL) and
with the help of HDL synthesis tools.

In special cases such as synthesis for coarse-grain cell libraries or when
testing new synthesis algorithms it might be necessary to write a custom HDL
synthesis tool or add new features to an existing one. In these cases the
availability of a Free and Open Source (FOSS) synthesis tool that can be used
as basis for custom tools would be helpful.

In the absence of such a tool, the Yosys Open SYnthesis Suite (Yosys) was
developed. This document covers the design and implementation of this tool.
At the moment the main focus of Yosys lies on the high-level aspects of
digital synthesis. The pre-existing FOSS logic-synthesis tool ABC is used
by Yosys to perform advanced gate-level optimizations.

An evaluation of Yosys based on real-world designs is included. It is shown
that Yosys can be used as-is to synthesize such designs. The results produced
by Yosys in this tests where successfully verified using formal verification
and are comparable in quality to the results produced by a commercial
synthesis tool.

<span class="k">\bigskip</span>

This document was originally published as bachelor thesis at the Vienna
University of Technology <span class="k">\cite</span><span class="nb">{</span>BACC<span class="nb">}</span>.

<span class="k">\chapter*</span><span class="nb">{</span>Abbreviations<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}{</span>ll<span class="nb">}</span>
AIG         <span class="nb">&amp;</span> And-Inverter-Graph <span class="k">\\</span>
ASIC        <span class="nb">&amp;</span> Application-Specific Integrated Circuit <span class="k">\\</span>
AST         <span class="nb">&amp;</span> Abstract Syntax Tree <span class="k">\\</span>
BDD         <span class="nb">&amp;</span> Binary Decision Diagram <span class="k">\\</span>
BLIF        <span class="nb">&amp;</span> Berkeley Logic Interchange Format <span class="k">\\</span>
EDA         <span class="nb">&amp;</span> Electronic Design Automation <span class="k">\\</span>
EDIF        <span class="nb">&amp;</span> Electronic Design Interchange Format <span class="k">\\</span>
ER Diagram  <span class="nb">&amp;</span> Entity-Relationship Diagram <span class="k">\\</span>
FOSS        <span class="nb">&amp;</span> Free and Open-Source Software <span class="k">\\</span>
FPGA        <span class="nb">&amp;</span> Field-Programmable Gate Array <span class="k">\\</span>
FSM         <span class="nb">&amp;</span> Finite-state machine <span class="k">\\</span>
HDL         <span class="nb">&amp;</span> Hardware Description Language <span class="k">\\</span>
LPM         <span class="nb">&amp;</span> Library of Parameterized Modules <span class="k">\\</span>
RTLIL       <span class="nb">&amp;</span> RTL Intermediate Language <span class="k">\\</span>
RTL         <span class="nb">&amp;</span> Register Transfer Level <span class="k">\\</span>
SAT         <span class="nb">&amp;</span> Satisfiability Problem <span class="k">\\</span>
<span class="c">% SSA       &amp; Static Single Assignment Form \\</span>
VHDL        <span class="nb">&amp;</span> VHSIC Hardware Description Language <span class="k">\\</span>
VHSIC       <span class="nb">&amp;</span> Very-High-Speed Integrated Circuit <span class="k">\\</span>
YOSYS       <span class="nb">&amp;</span> Yosys Open SYnthesis Suite <span class="k">\\</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>

<span class="k">\tableofcontents</span>

<span class="k">\include</span><span class="nb">{</span>CHAPTER<span class="nb">_</span>Intro<span class="nb">}</span>
<span class="k">\include</span><span class="nb">{</span>CHAPTER<span class="nb">_</span>Basics<span class="nb">}</span>
<span class="k">\include</span><span class="nb">{</span>CHAPTER<span class="nb">_</span>Approach<span class="nb">}</span>
<span class="k">\include</span><span class="nb">{</span>CHAPTER<span class="nb">_</span>Overview<span class="nb">}</span>
<span class="k">\include</span><span class="nb">{</span>CHAPTER<span class="nb">_</span>CellLib<span class="nb">}</span>
<span class="k">\include</span><span class="nb">{</span>CHAPTER<span class="nb">_</span>Prog<span class="nb">}</span>

<span class="k">\include</span><span class="nb">{</span>CHAPTER<span class="nb">_</span>Verilog<span class="nb">}</span>
<span class="k">\include</span><span class="nb">{</span>CHAPTER<span class="nb">_</span>Optimize<span class="nb">}</span>
<span class="k">\include</span><span class="nb">{</span>CHAPTER<span class="nb">_</span>Techmap<span class="nb">}</span>
<span class="c">% \include{CHAPTER_Eval}</span>

<span class="k">\appendix</span>

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<span class="k">\include</span><span class="nb">{</span>CHAPTER<span class="nb">_</span>Auxprogs<span class="nb">}</span>

<span class="k">\chapter</span><span class="nb">{</span>Command Reference Manual<span class="nb">}</span>
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<span class="k">\include</span><span class="nb">{</span>CHAPTER<span class="nb">_</span>Appnotes<span class="nb">}</span>
<span class="c">% \include{CHAPTER_StateOfTheArt}</span>

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<span class="k">\end</span><span class="nb">{</span>document<span class="nb">}</span>
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