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<div class='content'><div class='cgit-panel'><b>diff options</b><form method='get'><input type='hidden' name='h' value='openwrt-18.06'/><input type='hidden' name='id' value='891bba8f77192aec9d3e4d50a17525c33efd873a'/><table><tr><td colspan='2'/></tr><tr><td class='label'>context:</td><td class='ctrl'><select name='context' onchange='this.form.submit();'><option value='1'>1</option><option value='2'>2</option><option value='3' selected='selected'>3</option><option value='4'>4</option><option value='5'>5</option><option value='6'>6</option><option value='7'>7</option><option value='8'>8</option><option value='9'>9</option><option value='10'>10</option><option value='15'>15</option><option value='20'>20</option><option value='25'>25</option><option value='30'>30</option><option value='35'>35</option><option value='40'>40</option></select></td></tr><tr><td class='label'>space:</td><td class='ctrl'><select name='ignorews' onchange='this.form.submit();'><option value='0' selected='selected'>include</option><option value='1'>ignore</option></select></td></tr><tr><td class='label'>mode:</td><td class='ctrl'><select name='dt' onchange='this.form.submit();'><option value='0' selected='selected'>unified</option><option value='1'>ssdiff</option><option value='2'>stat only</option></select></td></tr><tr><td/><td class='ctrl'><noscript><input type='submit' value='reload'/></noscript></td></tr></table></form></div><table summary='commit info' class='commit-info'>
<tr><th>author</th><td>Koen Vandeputte &lt;koen.vandeputte@ncentric.com&gt;</td><td class='right'>2020-01-14 14:44:24 +0100</td></tr>
<tr><th>committer</th><td>Koen Vandeputte &lt;koen.vandeputte@ncentric.com&gt;</td><td class='right'>2020-01-20 13:44:38 +0100</td></tr>
<tr><th>commit</th><td colspan='2' class='sha1'><a href='/cgit.cgi/openwrt/upstream/commit/?h=openwrt-18.06&amp;id=891bba8f77192aec9d3e4d50a17525c33efd873a'>891bba8f77192aec9d3e4d50a17525c33efd873a</a> (<a href='/cgit.cgi/openwrt/upstream/patch/?id=891bba8f77192aec9d3e4d50a17525c33efd873a'>patch</a>)</td></tr>
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<tr><th>parent</th><td colspan='2' class='sha1'><a href='/cgit.cgi/openwrt/upstream/commit/?h=openwrt-18.06&amp;id=ab9d1bf608170c17dd8a372bc42806b9703a20ce'>ab9d1bf608170c17dd8a372bc42806b9703a20ce</a> (<a href='/cgit.cgi/openwrt/upstream/diff/?h=openwrt-18.06&amp;id=891bba8f77192aec9d3e4d50a17525c33efd873a&amp;id2=ab9d1bf608170c17dd8a372bc42806b9703a20ce'>diff</a>)</td></tr><tr><th>download</th><td colspan='2' class='sha1'><a href='/cgit.cgi/openwrt/upstream/snapshot/upstream-891bba8f77192aec9d3e4d50a17525c33efd873a.tar.gz'>upstream-891bba8f77192aec9d3e4d50a17525c33efd873a.tar.gz</a><br/><a href='/cgit.cgi/openwrt/upstream/snapshot/upstream-891bba8f77192aec9d3e4d50a17525c33efd873a.tar.bz2'>upstream-891bba8f77192aec9d3e4d50a17525c33efd873a.tar.bz2</a><br/><a href='/cgit.cgi/openwrt/upstream/snapshot/upstream-891bba8f77192aec9d3e4d50a17525c33efd873a.zip'>upstream-891bba8f77192aec9d3e4d50a17525c33efd873a.zip</a><br/></td></tr></table>
<div class='commit-subject'>kernel: bump 4.9 to 4.9.209</div><div class='commit-msg'>Refreshed all patches.

Compile-tested on: ar71xx
Runtime-tested on: ar71xx

Signed-off-by: Koen Vandeputte &lt;koen.vandeputte@ncentric.com&gt;
</div><div class='diffstat-header'><a href='/cgit.cgi/openwrt/upstream/diff/?h=openwrt-18.06&amp;id=891bba8f77192aec9d3e4d50a17525c33efd873a'>Diffstat</a></div><table summary='diffstat' class='diffstat'><tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit.cgi/openwrt/upstream/diff/include/kernel-version.mk?h=openwrt-18.06&amp;id=891bba8f77192aec9d3e4d50a17525c33efd873a'>include/kernel-version.mk</a></td><td class='right'>4</td><td class='graph'><table summary='file diffstat' width='4%'><tr><td class='add' style='width: 50.0%;'/><td class='rem' style='width: 50.0%;'/><td class='none' style='width: 0.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit.cgi/openwrt/upstream/diff/target/linux/ar71xx/patches-4.9/910-unaligned_access_hacks.patch?h=openwrt-18.06&amp;id=891bba8f77192aec9d3e4d50a17525c33efd873a'>target/linux/ar71xx/patches-4.9/910-unaligned_access_hacks.patch</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='4%'><tr><td class='add' style='width: 25.0%;'/><td class='rem' style='width: 25.0%;'/><td class='none' style='width: 50.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit.cgi/openwrt/upstream/diff/target/linux/generic/backport-4.9/022-net-add-devm-version-of-alloc_etherdev_mqs-function.patch?h=openwrt-18.06&amp;id=891bba8f77192aec9d3e4d50a17525c33efd873a'>target/linux/generic/backport-4.9/022-net-add-devm-version-of-alloc_etherdev_mqs-function.patch</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='4%'><tr><td class='add' style='width: 25.0%;'/><td class='rem' style='width: 25.0%;'/><td class='none' style='width: 50.0%;'/></tr></table></td></tr>
<tr><td class='mode'>-rw-r--r--</td><td class='upd'><a href='/cgit.cgi/openwrt/upstream/diff/target/linux/layerscape/patches-4.9/301-arch-support-layerscape.patch?h=openwrt-18.06&amp;id=891bba8f77192aec9d3e4d50a17525c33efd873a'>target/linux/layerscape/patches-4.9/301-arch-support-layerscape.patch</a></td><td class='right'>2</td><td class='graph'><table summary='file diffstat' width='4%'><tr><td class='add' style='width: 25.0%;'/><td class='rem' style='width: 25.0%;'/><td class='none' style='width: 50.0%;'/></tr></table></td></tr>
</table><div class='diffstat-summary'>4 files changed, 5 insertions, 5 deletions</div><table summary='diff' class='diff'><tr><td><div class='head'>diff --git a/include/kernel-version.mk b/include/kernel-version.mk<br/>index 88649e6309a..d9ade329420 100644<br/>--- a/<a href='/cgit.cgi/openwrt/upstream/tree/include/kernel-version.mk?h=openwrt-18.06&amp;id=ab9d1bf608170c17dd8a372bc42806b9703a20ce'>include/kernel-version.mk</a><br/>+++ b/<a href='/cgit.cgi/openwrt/upstream/tree/include/kernel-version.mk?h=openwrt-18.06&amp;id=891bba8f77192aec9d3e4d50a17525c33efd873a'>include/kernel-version.mk</a></div><div class='hunk'>@@ -2,10 +2,10 @@</div><div class='ctx'> </div><div class='ctx'> LINUX_RELEASE?=1</div><div class='ctx'> </div><div class='del'>-LINUX_VERSION-4.9 = .208</div><div class='add'>+LINUX_VERSION-4.9 = .209</div><div class='ctx'> LINUX_VERSION-4.14 = .162</div><div class='ctx'> </div><div class='del'>-LINUX_KERNEL_HASH-4.9.208 = b7ad1c9841d671d026c55a4c91c77205f8b488ca5f980f838591c68662e0525a</div><div class='add'>+LINUX_KERNEL_HASH-4.9.209 = 0258d5bef915fddcdd584a26ae91bafa996d7e400e725d36329ee44041aa59e1</div><div class='ctx'> LINUX_KERNEL_HASH-4.14.162 = f65170224cd4359ce8b2793b492bd8127abdd0b91350484e001bce13f0c98b4b</div><div class='ctx'> </div><div class='ctx'> remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1))))</div><div class='head'>diff --git a/target/linux/ar71xx/patches-4.9/910-unaligned_access_hacks.patch b/target/linux/ar71xx/patches-4.9/910-unaligned_access_hacks.patch<br/>index 6008be38d3d..3e367589f91 100644<br/>--- a/<a href='/cgit.cgi/openwrt/upstream/tree/target/linux/ar71xx/patches-4.9/910-unaligned_access_hacks.patch?h=openwrt-18.06&amp;id=ab9d1bf608170c17dd8a372bc42806b9703a20ce'>target/linux/ar71xx/patches-4.9/910-unaligned_access_hacks.patch</a><br/>+++ b/<a href='/cgit.cgi/openwrt/upstream/tree/target/linux/ar71xx/patches-4.9/910-unaligned_access_hacks.patch?h=openwrt-18.06&amp;id=891bba8f77192aec9d3e4d50a17525c33efd873a'>target/linux/ar71xx/patches-4.9/910-unaligned_access_hacks.patch</a></div><div class='hunk'>@@ -795,7 +795,7 @@</div><div class='ctx'>  </div><div class='ctx'> --- a/net/ipv4/tcp_input.c</div><div class='ctx'> +++ b/net/ipv4/tcp_input.c</div><div class='del'>-@@ -3926,14 +3926,16 @@ static bool tcp_parse_aligned_timestamp(</div><div class='add'>+@@ -3929,14 +3929,16 @@ static bool tcp_parse_aligned_timestamp(</div><div class='ctx'>  {</div><div class='ctx'>  	const __be32 *ptr = (const __be32 *)(th + 1);</div><div class='ctx'>  </div><div class='head'>diff --git a/target/linux/generic/backport-4.9/022-net-add-devm-version-of-alloc_etherdev_mqs-function.patch b/target/linux/generic/backport-4.9/022-net-add-devm-version-of-alloc_etherdev_mqs-function.patch<br/>index c5d65b7105e..b553dfaa3f1 100644<br/>--- a/<a href='/cgit.cgi/openwrt/upstream/tree/target/linux/generic/backport-4.9/022-net-add-devm-version-of-alloc_etherdev_mqs-function.patch?h=openwrt-18.06&amp;id=ab9d1bf608170c17dd8a372bc42806b9703a20ce'>target/linux/generic/backport-4.9/022-net-add-devm-version-of-alloc_etherdev_mqs-function.patch</a><br/>+++ b/<a href='/cgit.cgi/openwrt/upstream/tree/target/linux/generic/backport-4.9/022-net-add-devm-version-of-alloc_etherdev_mqs-function.patch?h=openwrt-18.06&amp;id=891bba8f77192aec9d3e4d50a17525c33efd873a'>target/linux/generic/backport-4.9/022-net-add-devm-version-of-alloc_etherdev_mqs-function.patch</a></div><div class='hunk'>@@ -32,7 +32,7 @@ Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;</div><div class='ctx'>  int eth_gro_complete(struct sk_buff *skb, int nhoff);</div><div class='ctx'> --- a/net/ethernet/eth.c</div><div class='ctx'> +++ b/net/ethernet/eth.c</div><div class='del'>-@@ -391,6 +391,34 @@ struct net_device *alloc_etherdev_mqs(in</div><div class='add'>+@@ -396,6 +396,34 @@ struct net_device *alloc_etherdev_mqs(in</div><div class='ctx'>  }</div><div class='ctx'>  EXPORT_SYMBOL(alloc_etherdev_mqs);</div><div class='ctx'>  </div><div class='head'>diff --git a/target/linux/layerscape/patches-4.9/301-arch-support-layerscape.patch b/target/linux/layerscape/patches-4.9/301-arch-support-layerscape.patch<br/>index 52dfced2b89..473990ddaa7 100644<br/>--- a/<a href='/cgit.cgi/openwrt/upstream/tree/target/linux/layerscape/patches-4.9/301-arch-support-layerscape.patch?h=openwrt-18.06&amp;id=ab9d1bf608170c17dd8a372bc42806b9703a20ce'>target/linux/layerscape/patches-4.9/301-arch-support-layerscape.patch</a><br/>+++ b/<a href='/cgit.cgi/openwrt/upstream/tree/target/linux/layerscape/patches-4.9/301-arch-support-layerscape.patch?h=openwrt-18.06&amp;id=891bba8f77192aec9d3e4d50a17525c33efd873a'>target/linux/layerscape/patches-4.9/301-arch-support-layerscape.patch</a></div><div class='hunk'>@@ -345,7 +345,7 @@ Signed-off-by: Yangbo Lu &lt;yangbo.lu@nxp.com&gt;</div><div class='ctx'>  #define PROT_SECT_NORMAL	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))</div><div class='ctx'> --- a/arch/arm64/include/asm/pgtable.h</div><div class='ctx'> +++ b/arch/arm64/include/asm/pgtable.h</div><div class='del'>-@@ -370,6 +370,11 @@ static inline int pmd_protnone(pmd_t pmd</div><div class='add'>+@@ -366,6 +366,11 @@ static inline int pmd_protnone(pmd_t pmd</div><div class='ctx'>  	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)</div><div class='ctx'>  #define pgprot_writecombine(prot) \</div><div class='ctx'>  	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)</div></td></tr></table></div> <!-- class=content -->
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</pre></td>
<td class='lines'><pre><code><style>pre { line-height: 125%; margin: 0; }
td.linenos pre { color: #000000; background-color: #f0f0f0; padding: 0 5px 0 5px; }
span.linenos { color: #000000; background-color: #f0f0f0; padding: 0 5px 0 5px; }
td.linenos pre.special { color: #000000; background-color: #ffffc0; padding: 0 5px 0 5px; }
span.linenos.special { color: #000000; background-color: #ffffc0; padding: 0 5px 0 5px; }
.highlight .hll { background-color: #ffffcc }
.highlight { background: #ffffff; }
.highlight .c { color: #888888 } /* Comment */
.highlight .err { color: #a61717; background-color: #e3d2d2 } /* Error */
.highlight .k { color: #008800; font-weight: bold } /* Keyword */
.highlight .ch { color: #888888 } /* Comment.Hashbang */
.highlight .cm { color: #888888 } /* Comment.Multiline */
.highlight .cp { color: #cc0000; font-weight: bold } /* Comment.Preproc */
.highlight .cpf { color: #888888 } /* Comment.PreprocFile */
.highlight .c1 { color: #888888 } /* Comment.Single */
.highlight .cs { color: #cc0000; font-weight: bold; background-color: #fff0f0 } /* Comment.Special */
.highlight .gd { color: #000000; background-color: #ffdddd } /* Generic.Deleted */
.highlight .ge { font-style: italic } /* Generic.Emph */
.highlight .gr { color: #aa0000 } /* Generic.Error */
.highlight .gh { color: #333333 } /* Generic.Heading */
.highlight .gi { color: #000000; background-color: #ddffdd } /* Generic.Inserted */
.highlight .go { color: #888888 } /* Generic.Output */
.highlight .gp { color: #555555 } /* Generic.Prompt */
.highlight .gs { font-weight: bold } /* Generic.Strong */
.highlight .gu { color: #666666 } /* Generic.Subheading */
.highlight .gt { color: #aa0000 } /* Generic.Traceback */
.highlight .kc { color: #008800; font-weight: bold } /* Keyword.Constant */
.highlight .kd { color: #008800; font-weight: bold } /* Keyword.Declaration */
.highlight .kn { color: #008800; font-weight: bold } /* Keyword.Namespace */
.highlight .kp { color: #008800 } /* Keyword.Pseudo */
.highlight .kr { color: #008800; font-weight: bold } /* Keyword.Reserved */
.highlight .kt { color: #888888; font-weight: bold } /* Keyword.Type */
.highlight .m { color: #0000DD; font-weight: bold } /* Literal.Number */
.highlight .s { color: #dd2200; background-color: #fff0f0 } /* Literal.String */
.highlight .na { color: #336699 } /* Name.Attribute */
.highlight .nb { color: #003388 } /* Name.Builtin */
.highlight .nc { color: #bb0066; font-weight: bold } /* Name.Class */
.highlight .no { color: #003366; font-weight: bold } /* Name.Constant */
.highlight .nd { color: #555555 } /* Name.Decorator */
.highlight .ne { color: #bb0066; font-weight: bold } /* Name.Exception */
.highlight .nf { color: #0066bb; font-weight: bold } /* Name.Function */
.highlight .nl { color: #336699; font-style: italic } /* Name.Label */
.highlight .nn { color: #bb0066; font-weight: bold } /* Name.Namespace */
.highlight .py { color: #336699; font-weight: bold } /* Name.Property */
.highlight .nt { color: #bb0066; font-weight: bold } /* Name.Tag */
.highlight .nv { color: #336699 } /* Name.Variable */
.highlight .ow { color: #008800 } /* Operator.Word */
.highlight .w { color: #bbbbbb } /* Text.Whitespace */
.highlight .mb { color: #0000DD; font-weight: bold } /* Literal.Number.Bin */
.highlight .mf { color: #0000DD; font-weight: bold } /* Literal.Number.Float */
.highlight .mh { color: #0000DD; font-weight: bold } /* Literal.Number.Hex */
.highlight .mi { color: #0000DD; font-weight: bold } /* Literal.Number.Integer */
.highlight .mo { color: #0000DD; font-weight: bold } /* Literal.Number.Oct */
.highlight .sa { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Affix */
.highlight .sb { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Backtick */
.highlight .sc { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Char */
.highlight .dl { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Delimiter */
.highlight .sd { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Doc */
.highlight .s2 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Double */
.highlight .se { color: #0044dd; background-color: #fff0f0 } /* Literal.String.Escape */
.highlight .sh { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Heredoc */
.highlight .si { color: #3333bb; background-color: #fff0f0 } /* Literal.String.Interpol */
.highlight .sx { color: #22bb22; background-color: #f0fff0 } /* Literal.String.Other */
.highlight .sr { color: #008800; background-color: #fff0ff } /* Literal.String.Regex */
.highlight .s1 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Single */
.highlight .ss { color: #aa6600; background-color: #fff0f0 } /* Literal.String.Symbol */
.highlight .bp { color: #003388 } /* Name.Builtin.Pseudo */
.highlight .fm { color: #0066bb; font-weight: bold } /* Name.Function.Magic */
.highlight .vc { color: #336699 } /* Name.Variable.Class */
.highlight .vg { color: #dd7700 } /* Name.Variable.Global */
.highlight .vi { color: #3333bb } /* Name.Variable.Instance */
.highlight .vm { color: #336699 } /* Name.Variable.Magic */
.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */</style><div class="highlight"><pre><span></span><span class="k">\section</span><span class="nb">{</span>Writing Yosys extensions in C++<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>
<span class="k">\sectionpage</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Program Components and Data Formats<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>[scale=0.6, every node/.style=<span class="nb">{</span>transform shape<span class="nb">}</span>]
	<span class="k">\tikzstyle</span><span class="nb">{</span>process<span class="nb">}</span> = [draw, fill=green!10, rectangle, minimum height=3em, minimum width=10em, node distance=15em]
	<span class="k">\tikzstyle</span><span class="nb">{</span>data<span class="nb">}</span> = [draw, fill=blue!10, ellipse, minimum height=3em, minimum width=7em, node distance=15em]
	<span class="k">\node</span><span class="na">[process]</span> (vlog) <span class="nb">{</span>Verilog Frontend<span class="nb">}</span>;
	<span class="k">\node</span><span class="na">[process, dashed, fill=green!5]</span> (vhdl) [right of=vlog] <span class="nb">{</span>VHDL Frontend<span class="nb">}</span>;
	<span class="k">\node</span><span class="na">[process]</span> (ilang) [right of=vhdl] <span class="nb">{</span>Other Frontends<span class="nb">}</span>;
	<span class="k">\node</span><span class="na">[data]</span> (ast) [below of=vlog, node distance=5em, xshift=7.5em] <span class="nb">{</span>AST<span class="nb">}</span>;
	<span class="k">\node</span><span class="na">[process]</span> (astfe) [below of=ast, node distance=5em] <span class="nb">{</span>AST Frontend<span class="nb">}</span>;
	<span class="k">\node</span><span class="na">[data]</span> (rtlil) [below of=astfe, node distance=5em, xshift=7.5em] <span class="nb">{</span>RTLIL<span class="nb">}</span>;
	<span class="k">\node</span><span class="na">[process]</span> (pass) [right of=rtlil, node distance=5em, xshift=7.5em] <span class="nb">{</span>Passes<span class="nb">}</span>;
	<span class="k">\node</span><span class="na">[process]</span> (vlbe) [below of=rtlil, node distance=7em, xshift=-13em] <span class="nb">{</span>Verilog Backend<span class="nb">}</span>;
	<span class="k">\node</span><span class="na">[process]</span> (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] <span class="nb">{</span>ILANG Backend<span class="nb">}</span>;
	<span class="k">\node</span><span class="na">[process, fill=green!5]</span> (otherbe) [below of=rtlil, node distance=7em, xshift=+13em] <span class="nb">{</span>Other Backends<span class="nb">}</span>;

	<span class="k">\draw</span><span class="na">[-latex]</span> (vlog) -- (ast);
	<span class="k">\draw</span><span class="na">[-latex]</span> (vhdl) -- (ast);
	<span class="k">\draw</span><span class="na">[-latex]</span> (ast) -- (astfe);
	<span class="k">\draw</span><span class="na">[-latex]</span> (astfe) -- (rtlil);
	<span class="k">\draw</span><span class="na">[-latex]</span> (ilang) -- (rtlil);
	<span class="k">\draw</span><span class="na">[latex-latex]</span> (rtlil) -- (pass);
	<span class="k">\draw</span><span class="na">[-latex]</span> (rtlil) -- (vlbe);
	<span class="k">\draw</span><span class="na">[-latex]</span> (rtlil) -- (ilangbe);
	<span class="k">\draw</span><span class="na">[-latex]</span> (rtlil) -- (otherbe);
<span class="k">\end</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Simplified RTLIL Entity-Relationship Diagram<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
Between passses and frontends/backends the design is stored in Yosys&#39; internal
RTLIL (RTL Intermediate Language) format. For writing Yosys extensions it is
key to understand this format.

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>[scale=0.6, every node/.style=<span class="nb">{</span>transform shape<span class="nb">}</span>]
	<span class="k">\tikzstyle</span><span class="nb">{</span>entity<span class="nb">}</span> = [draw, fill=gray!10, rectangle, minimum height=3em, minimum width=7em, node distance=5em, font=<span class="nb">{</span><span class="k">\ttfamily</span><span class="nb">}</span>]
	<span class="k">\node</span><span class="na">[entity]</span> (design) <span class="nb">{</span>RTLIL::Design<span class="nb">}</span>;
	<span class="k">\node</span><span class="na">[entity]</span> (module) [right of=design, node distance=11em] <span class="nb">{</span>RTLIL::Module<span class="nb">}</span> edge [-latex] node[above] <span class="nb">{</span><span class="k">\tiny</span> 1 <span class="k">\hskip</span>3em N<span class="nb">}</span> (design);

	<span class="k">\node</span><span class="na">[entity]</span> (process) [fill=green!10, right of=module, node distance=10em] <span class="nb">{</span>RTLIL::Process<span class="nb">}</span> (process.west) edge [-latex] (module);
	<span class="k">\node</span><span class="na">[entity]</span> (memory) [fill=red!10, below of=process] <span class="nb">{</span>RTLIL::Memory<span class="nb">}</span> edge [-latex] (module);
	<span class="k">\node</span><span class="na">[entity]</span> (wire) [fill=blue!10, above of=process] <span class="nb">{</span>RTLIL::Wire<span class="nb">}</span> (wire.west) edge [-latex] (module);
	<span class="k">\node</span><span class="na">[entity]</span> (cell) [fill=blue!10, above of=wire] <span class="nb">{</span>RTLIL::Cell<span class="nb">}</span> (cell.west) edge [-latex] (module);

	<span class="k">\node</span><span class="na">[entity]</span> (case) [fill=green!10, right of=process, node distance=10em] <span class="nb">{</span>RTLIL::CaseRule<span class="nb">}</span> edge [latex-latex] (process);
	<span class="k">\node</span><span class="na">[entity]</span> (sync) [fill=green!10, above of=case] <span class="nb">{</span>RTLIL::SyncRule<span class="nb">}</span> edge [-latex] (process);
	<span class="k">\node</span><span class="na">[entity]</span> (switch) [fill=green!10, below of=case] <span class="nb">{</span>RTLIL::SwitchRule<span class="nb">}</span> edge [-latex] (case);
	<span class="k">\draw</span><span class="na">[latex-]</span> (switch.east) -- ++(1em,0) |- (case.east);
<span class="k">\end</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>RTLIL without memories and processes<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">}</span>
After the commands <span class="nb">{</span><span class="k">\tt</span> proc<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> memory<span class="nb">}</span> (or <span class="nb">{</span><span class="k">\tt</span> memory -nomap<span class="nb">}</span>), we are
left with a much simpler version of RTLIL:

<span class="k">\begin</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>[scale=0.6, every node/.style=<span class="nb">{</span>transform shape<span class="nb">}</span>]
	<span class="k">\tikzstyle</span><span class="nb">{</span>entity<span class="nb">}</span> = [draw, fill=gray!10, rectangle, minimum height=3em, minimum width=7em, node distance=5em, font=<span class="nb">{</span><span class="k">\ttfamily</span><span class="nb">}</span>]
	<span class="k">\node</span><span class="na">[entity]</span> (design) <span class="nb">{</span>RTLIL::Design<span class="nb">}</span>;
	<span class="k">\node</span><span class="na">[entity]</span> (module) [right of=design, node distance=11em] <span class="nb">{</span>RTLIL::Module<span class="nb">}</span> edge [-latex] node[above] <span class="nb">{</span><span class="k">\tiny</span> 1 <span class="k">\hskip</span>3em N<span class="nb">}</span> (design);

	<span class="k">\node</span><span class="na">[entity]</span> (wire) [fill=blue!10, right of=module, node distance=10em] <span class="nb">{</span>RTLIL::Wire<span class="nb">}</span> (wire.west) edge [-latex] (module);
	<span class="k">\node</span><span class="na">[entity]</span> (cell) [fill=blue!10, above of=wire] <span class="nb">{</span>RTLIL::Cell<span class="nb">}</span> (cell.west) edge [-latex] (module);
<span class="k">\end</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>center<span class="nb">}</span>

<span class="k">\bigskip</span>
Many commands simply choose to only work on this simpler version:
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>]
if (module-&gt;processes.size() != 0 || module-&gt;memories.size() != 0)
    log<span class="nb">_</span>error(&quot;This command does not operate on modules with processes &quot;
              &quot;and/or memories! Run &#39;proc&#39; and &#39;memory&#39; first.<span class="k">\n</span>&quot;);
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
For simplicity we only discuss this version of RTLIL in this presentation.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Using dump and show commands<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> The <span class="nb">{</span><span class="k">\tt</span> dump<span class="nb">}</span> command prints the design (or parts of it) in ILANG format. This is
a text representation of RTLIL.

<span class="k">\bigskip</span>
<span class="k">\item</span> The <span class="nb">{</span><span class="k">\tt</span> show<span class="nb">}</span> command visualizes how the components in the design are connected.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\bigskip</span>
When trying to understand what a command does, create a small test case and
look at the output of <span class="nb">{</span><span class="k">\tt</span> dump<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> show<span class="nb">}</span> before and after the command
has been executed.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>The RTLIL Data Structures<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
The RTLIL data structures are simple structs utilizing C++ <span class="nb">{</span><span class="k">\tt</span> std::<span class="nb">}</span>
containers.

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Most operations are performed directly on the RTLIL structs without
setter or getter functions.

<span class="k">\bigskip</span>
<span class="k">\item</span> In debug builds a consistency checker is run over the in-memory design
between commands to make sure that the RTLIL representation is intact.

<span class="k">\bigskip</span>
<span class="k">\item</span> Most RTLIL structs have helper methods that perform the most common operations.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\bigskip</span>
See <span class="nb">{</span><span class="k">\tt</span> yosys/kernel/rtlil.h<span class="nb">}</span> for details.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>RTLIL::IdString<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsubsecname</span><span class="nb">}{}</span>
<span class="nb">{</span><span class="k">\tt</span> RTLIL::IdString<span class="nb">}</span> is a simple wrapper for <span class="nb">{</span><span class="k">\tt</span> std::string<span class="nb">}</span>. It is used for names of RTLIL objects.

<span class="k">\medskip</span>
The first character of a <span class="nb">{</span><span class="k">\tt</span> RTLIL::IdString<span class="nb">}</span> specifies if the name is <span class="nb">{</span><span class="k">\it</span> public<span class="k">\/</span><span class="nb">}</span> or <span class="nb">{</span><span class="k">\it</span> private<span class="k">\/</span><span class="nb">}</span>:

<span class="k">\medskip</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> RTLIL::IdString[0] == &#39;<span class="k">\textbackslash\textbackslash</span>&#39;<span class="nb">}</span>: <span class="k">\\</span>
This is a public name. Usually this means it is a name that was declared in a Verilog file.

<span class="k">\bigskip</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> RTLIL::IdString[0] == &#39;<span class="k">\$</span>&#39;<span class="nb">}</span>: <span class="k">\\</span>
This is a private name. It was assigned by Yosys.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\bigskip</span>
Use the <span class="nb">{</span><span class="k">\tt</span> NEW<span class="k">\_</span>ID<span class="nb">}</span> macro to create a new unique private name.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>RTLIL::Design and RTLIL::Module<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
The <span class="nb">{</span><span class="k">\tt</span> RTLIL::Design<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> RTLIL::Module<span class="nb">}</span> structs are the top-level RTLIL
data structures.

Yosys always operates on one active design, but can hold many designs in memory.

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
struct RTLIL::Design <span class="nb">{</span>
    std::map&lt;RTLIL::IdString, RTLIL::Module*&gt; modules;
    ...
<span class="nb">}</span>;

struct RTLIL::Module <span class="nb">{</span>
    RTLIL::IdString name;
    std::map&lt;RTLIL::IdString, RTLIL::Wire*&gt; wires;
    std::map&lt;RTLIL::IdString, RTLIL::Cell*&gt; cells;
    std::vector&lt;RTLIL::SigSig&gt; connections;
    ...
<span class="nb">}</span>;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>The RTLIL::Wire Structure<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
Each wire in the design is represented by a <span class="nb">{</span><span class="k">\tt</span> RTLIL::Wire<span class="nb">}</span> struct:

<span class="k">\medskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
struct RTLIL::Wire <span class="nb">{</span>
    RTLIL::IdString name;
    int width, start<span class="nb">_</span>offset, port<span class="nb">_</span>id;
    bool port<span class="nb">_</span>input, port<span class="nb">_</span>output;
    ...
<span class="nb">}</span>;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\medskip</span>
<span class="k">\hfil\begin</span><span class="nb">{</span>tabular<span class="nb">}{</span>p<span class="nb">{</span>3cm<span class="nb">}</span>l<span class="nb">}</span>
<span class="nb">{</span><span class="k">\tt</span> width<span class="nb">}</span> <span class="k">\dotfill</span> <span class="nb">&amp;</span> The total number of bits. E.g. 10 for <span class="nb">{</span><span class="k">\tt</span> [9:0]<span class="nb">}</span>. <span class="k">\\</span>
<span class="nb">{</span><span class="k">\tt</span> start<span class="k">\_</span>offset<span class="nb">}</span> <span class="k">\dotfill</span> <span class="nb">&amp;</span> The lowest bit index. E.g. 3 for <span class="nb">{</span><span class="k">\tt</span> [5:3]<span class="nb">}</span>. <span class="k">\\</span>
<span class="nb">{</span><span class="k">\tt</span> port<span class="k">\_</span>id<span class="nb">}</span> <span class="k">\dotfill</span> <span class="nb">&amp;</span> Zero for non-ports. Positive index for ports. <span class="k">\\</span>
<span class="nb">{</span><span class="k">\tt</span> port<span class="k">\_</span>input<span class="nb">}</span> <span class="k">\dotfill</span> <span class="nb">&amp;</span> True for <span class="nb">{</span><span class="k">\tt</span> input<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> inout<span class="nb">}</span> ports. <span class="k">\\</span>
<span class="nb">{</span><span class="k">\tt</span> port<span class="k">\_</span>output<span class="nb">}</span> <span class="k">\dotfill</span> <span class="nb">&amp;</span> True for <span class="nb">{</span><span class="k">\tt</span> output<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> inout<span class="nb">}</span> ports. <span class="k">\\</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>RTLIL::State and RTLIL::Const<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
The <span class="nb">{</span><span class="k">\tt</span> RTLIL::State<span class="nb">}</span> enum represents a simple 1-bit logic level:

<span class="k">\smallskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
enum RTLIL::State <span class="nb">{</span>
    S0 = 0,
    S1 = 1,
    Sx = 2, // undefined value or conflict
    Sz = 3, // high-impedance / not-connected
    Sa = 4, // don&#39;t care (used only in cases)
    Sm = 5  // marker (used internally by some passes)
<span class="nb">}</span>;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
The <span class="nb">{</span><span class="k">\tt</span> RTLIL::Const<span class="nb">}</span> struct represents a constant multi-bit value:

<span class="k">\smallskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
struct RTLIL::Const <span class="nb">{</span>
    std::vector&lt;RTLIL::State&gt; bits;
    ...
<span class="nb">}</span>;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
Notice that Yosys is not using special <span class="nb">{</span><span class="k">\tt</span> VCC<span class="nb">}</span> or <span class="nb">{</span><span class="k">\tt</span> GND<span class="nb">}</span> driver cells to represent constants. Instead
constants are part of the RTLIL representation itself.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>The RTLIL::SigSpec Structure<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
The <span class="nb">{</span><span class="k">\tt</span> RTLIL::SigSpec<span class="nb">}</span> struct represents a signal vector. Each bit can either be a bit from a wire
or a constant value. Consecutive bits from a wire or consecutive constant bits are consolidated into
a <span class="nb">{</span><span class="k">\tt</span> RTLIL::SigChunk<span class="nb">}</span>:

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
struct RTLIL::SigChunk <span class="nb">{</span>
    RTLIL::Wire *wire;
    RTLIL::Const data; // only used if wire == NULL
    int width, offset;
    ...
<span class="nb">}</span>;

struct RTLIL::SigSpec <span class="nb">{</span>
    std::vector&lt;RTLIL::SigChunk&gt; chunks; // LSB at index 0
    int width;
    ...
<span class="nb">}</span>;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
The <span class="nb">{</span><span class="k">\tt</span> RTLIL::SigSpec<span class="nb">}</span> struct has a ton of additional helper methods to compare, analyze, and
manipulate instances of <span class="nb">{</span><span class="k">\tt</span> RTLIL::SigSpec<span class="nb">}</span>.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>The RTLIL::Cell Structure<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsubsecname</span> (1/2)<span class="nb">}</span>
The <span class="nb">{</span><span class="k">\tt</span> RTLIL::Cell<span class="nb">}</span> struct represents an instance of a module or library cell.

<span class="k">\smallskip</span>
The ports of the cell
are associated with <span class="nb">{</span><span class="k">\tt</span> RTLIL::SigSpec<span class="nb">}</span> instances and the parameters are associated with <span class="nb">{</span><span class="k">\tt</span> RTLIL::Const<span class="nb">}</span>
instances:

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
struct RTLIL::Cell <span class="nb">{</span>
    RTLIL::IdString name, type;
    std::map&lt;RTLIL::IdString, RTLIL::SigSpec&gt; connections;
    std::map&lt;RTLIL::IdString, RTLIL::Const&gt; parameters;
    ...
<span class="nb">}</span>;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
The <span class="nb">{</span><span class="k">\tt</span> type<span class="nb">}</span> may refer to another module in the same design, a cell name from a cell library, or a
cell name from the internal cell library:

<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>6pt<span class="nb">}{</span>7pt<span class="nb">}</span><span class="k">\selectfont</span>]
<span class="s">$</span><span class="nb">not </span><span class="s">$</span>pos <span class="s">$</span><span class="nb">bu</span><span class="m">0</span><span class="nb"> </span><span class="s">$</span>neg <span class="s">$</span><span class="nb">and </span><span class="s">$</span>or <span class="s">$</span><span class="nb">xor </span><span class="s">$</span>xnor <span class="s">$</span><span class="nb">reduce_and </span><span class="s">$</span>reduce<span class="nb">_</span>or <span class="s">$</span><span class="nb">reduce_xor </span><span class="s">$</span>reduce<span class="nb">_</span>xnor
<span class="s">$</span><span class="nb">reduce_bool </span><span class="s">$</span>shl <span class="s">$</span><span class="nb">shr </span><span class="s">$</span>sshl <span class="s">$</span><span class="nb">sshr </span><span class="s">$</span>lt <span class="s">$</span><span class="nb">le </span><span class="s">$</span>eq <span class="s">$</span><span class="nb">ne </span><span class="s">$</span>eqx <span class="s">$</span><span class="nb">nex </span><span class="s">$</span>ge <span class="s">$</span><span class="nb">gt </span><span class="s">$</span>add <span class="s">$</span><span class="nb">sub </span><span class="s">$</span>mul <span class="s">$</span><span class="nb">div </span><span class="s">$</span>mod
<span class="s">$</span><span class="nb">pow </span><span class="s">$</span>logic<span class="nb">_</span>not <span class="s">$</span><span class="nb">logic_and </span><span class="s">$</span>logic<span class="nb">_</span>or <span class="s">$</span><span class="nb">mux </span><span class="s">$</span>pmux <span class="s">$</span><span class="nb">slice </span><span class="s">$</span>concat <span class="s">$</span><span class="nb">lut </span><span class="s">$</span>assert <span class="s">$</span><span class="nb">sr </span><span class="s">$</span>dff
<span class="s">$</span><span class="nb">dffsr </span><span class="s">$</span>adff <span class="s">$</span><span class="nb">dlatch </span><span class="s">$</span>dlatchsr <span class="s">$</span><span class="nb">memrd </span><span class="s">$</span>memwr <span class="s">$</span><span class="nb">mem </span><span class="s">$</span>fsm <span class="s">$</span><span class="nb">_NOT_ </span><span class="s">$</span><span class="nb">_</span>AND<span class="nb">_</span> <span class="s">$</span><span class="nb">_OR_ </span><span class="s">$</span><span class="nb">_</span>XOR<span class="nb">_</span> <span class="s">$</span><span class="nb">_MUX_ </span><span class="s">$</span><span class="nb">_</span>SR<span class="nb">_</span>NN<span class="nb">_</span>
<span class="s">$</span><span class="nb">_SR_NP_ </span><span class="s">$</span><span class="nb">_</span>SR<span class="nb">_</span>PN<span class="nb">_</span> <span class="s">$</span><span class="nb">_SR_PP_ </span><span class="s">$</span><span class="nb">_</span>DFF<span class="nb">_</span>N<span class="nb">_</span> <span class="s">$</span><span class="nb">_DFF_P_ </span><span class="s">$</span><span class="nb">_</span>DFF<span class="nb">_</span>NN0<span class="nb">_</span> <span class="s">$</span><span class="nb">_DFF_NN</span><span class="m">1</span><span class="nb">_ </span><span class="s">$</span><span class="nb">_</span>DFF<span class="nb">_</span>NP0<span class="nb">_</span> <span class="s">$</span><span class="nb">_DFF_NP</span><span class="m">1</span><span class="nb">_ </span><span class="s">$</span><span class="nb">_</span>DFF<span class="nb">_</span>PN0<span class="nb">_</span>
<span class="s">$</span><span class="nb">_DFF_PN</span><span class="m">1</span><span class="nb">_ </span><span class="s">$</span><span class="nb">_</span>DFF<span class="nb">_</span>PP0<span class="nb">_</span> <span class="s">$</span><span class="nb">_DFF_PP</span><span class="m">1</span><span class="nb">_ </span><span class="s">$</span><span class="nb">_</span>DFFSR<span class="nb">_</span>NNN<span class="nb">_</span> <span class="s">$</span><span class="nb">_DFFSR_NNP_ </span><span class="s">$</span><span class="nb">_</span>DFFSR<span class="nb">_</span>NPN<span class="nb">_</span> <span class="s">$</span><span class="nb">_DFFSR_NPP_ </span><span class="s">$</span><span class="nb">_</span>DFFSR<span class="nb">_</span>PNN<span class="nb">_</span>
<span class="s">$</span><span class="nb">_DFFSR_PNP_ </span><span class="s">$</span><span class="nb">_</span>DFFSR<span class="nb">_</span>PPN<span class="nb">_</span> <span class="s">$</span><span class="nb">_DFFSR_PPP_ </span><span class="s">$</span><span class="nb">_</span>DLATCH<span class="nb">_</span>N<span class="nb">_</span> <span class="s">$</span><span class="nb">_DLATCH_P_ </span><span class="s">$</span><span class="nb">_</span>DLATCHSR<span class="nb">_</span>NNN<span class="nb">_</span> <span class="s">$</span><span class="nb">_DLATCHSR_NNP_</span>
<span class="s">$</span><span class="nb">_</span>DLATCHSR<span class="nb">_</span>NPN<span class="nb">_</span> <span class="s">$</span><span class="nb">_DLATCHSR_NPP_ </span><span class="s">$</span><span class="nb">_</span>DLATCHSR<span class="nb">_</span>PNN<span class="nb">_</span> <span class="s">$</span><span class="nb">_DLATCHSR_PNP_ </span><span class="s">$</span><span class="nb">_</span>DLATCHSR<span class="nb">_</span>PPN<span class="nb">_</span> <span class="s">$</span><span class="nb">_DLATCHSR_PPP_</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb"> </span><span class="o">(</span><span class="m">2</span><span class="o">/</span><span class="m">2</span><span class="o">)</span><span class="nb">}</span>
<span class="nb">Simulation models </span><span class="o">(</span><span class="nb">i.e. {</span><span class="nv">\it</span><span class="nb"> documentation</span><span class="nv">\/</span><span class="nb">} :</span><span class="o">-)</span><span class="nb"> for the internal cell library:</span>

<span class="nv">\smallskip</span><span class="nb"></span>
<span class="nv">\hskip</span><span class="m">2</span><span class="nb">em {</span><span class="nv">\tt</span><span class="nb"> yosys</span><span class="o">/</span><span class="nb">techlibs</span><span class="o">/</span><span class="nb">common</span><span class="o">/</span><span class="nb">simlib.v} and </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\hskip</span><span class="m">2</span><span class="nb">em {</span><span class="nv">\tt</span><span class="nb"> yosys</span><span class="o">/</span><span class="nb">techlibs</span><span class="o">/</span><span class="nb">common</span><span class="o">/</span><span class="nb">simcells.v}</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">The lower</span><span class="o">-</span><span class="nb">case cell types </span><span class="o">(</span><span class="nb">such as {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$</span><span class="nb">and}</span><span class="o">)</span><span class="nb"> are parameterized cells of variable</span>
<span class="nb">width. This so</span><span class="o">-</span><span class="nb">called {</span><span class="nv">\it</span><span class="nb"> RTL Cells</span><span class="nv">\/</span><span class="nb">} are the cells described in {</span><span class="nv">\tt</span><span class="nb"> simlib.v}. </span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">The upper</span><span class="o">-</span><span class="nb">case cell types </span><span class="o">(</span><span class="nb">such as {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$\_</span><span class="nb">AND</span><span class="nv">\_</span><span class="nb">}</span><span class="o">)</span><span class="nb"> are single</span><span class="o">-</span><span class="nb">bit cells that are not</span>
<span class="nb">parameterized. This so</span><span class="o">-</span><span class="nb">called {</span><span class="nv">\it</span><span class="nb"> Internal Logic Gates} are the cells described</span>
<span class="nb">in {</span><span class="nv">\tt</span><span class="nb"> simcells.v}.</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">The consistency checker also checks the interfaces to the internal cell library.</span>
<span class="nb">If you want to use private cell types for your own purposes, use the {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$\_\_</span><span class="nb">}</span><span class="o">-</span><span class="nb">prefix</span>
<span class="nb">to avoid name collisions.</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Connecting wires or constant drivers}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nb">Additional connections between wires or between wires and constants are modelled using</span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> RTLIL::Module::connections}:</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">1</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb"></span>
<span class="nb">typedef std::pair&lt;RTLIL::SigSpec, RTLIL::SigSpec&gt; RTLIL::SigSig;</span>

<span class="nb">struct RTLIL::Module {</span>
<span class="nb">    ...</span>
<span class="nb">    std::vector&lt;RTLIL::SigSig&gt; connections;</span>
<span class="nb">    ...</span>
<span class="nb">};</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> RTLIL::SigSig::first} is the driven signal and {</span><span class="nv">\tt</span><span class="nb"> RTLIL::SigSig::second} is the driving signal.</span>
<span class="nb">Example usage </span><span class="o">(</span><span class="nb">setting wire {</span><span class="nv">\tt</span><span class="nb"> foo} to value {</span><span class="nv">\tt</span><span class="nb"> </span><span class="m">42</span><span class="nb">}</span><span class="o">)</span><span class="nb">:</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">1</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb"></span>
<span class="nb">module</span><span class="o">-</span><span class="nb">&gt;connections.push_back</span><span class="o">(</span><span class="nb">RTLIL::SigSig</span><span class="o">(</span><span class="nb">module</span><span class="o">-</span><span class="nb">&gt;wires.at</span><span class="o">(</span><span class="nb">&quot;</span><span class="nv">\\</span><span class="nb">foo&quot;</span><span class="o">)</span><span class="nb">,</span>
<span class="nb">        RTLIL::SigSpec</span><span class="o">(</span><span class="m">42</span><span class="nb">, module</span><span class="o">-</span><span class="nb">&gt;wires.at</span><span class="o">(</span><span class="nb">&quot;</span><span class="nv">\\</span><span class="nb">foo&quot;</span><span class="o">)-</span><span class="nb">&gt;width</span><span class="o">)))</span><span class="nb">;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="nv">\subsection</span><span class="nb">{Creating modules from scratch}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsecname</span><span class="nb">}</span>
<span class="nb">Let&#39;s create the following module using the RTLIL API:</span>

<span class="nv">\smallskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">1</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb"></span>
<span class="nb">module absval</span><span class="o">(</span><span class="nb">input signed </span><span class="o">[</span><span class="m">3</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> a, output </span><span class="o">[</span><span class="m">3</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> y</span><span class="o">)</span><span class="nb">;</span>
<span class="nb">    assign y </span><span class="o">=</span><span class="nb"> a</span><span class="o">[</span><span class="m">3</span><span class="o">]</span><span class="nb"> ? </span><span class="o">-</span><span class="nb">a : a;</span>
<span class="nb">endmodule</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\smallskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">1</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb"></span>
<span class="nb">RTLIL::Module </span><span class="o">*</span><span class="nb">module </span><span class="o">=</span><span class="nb"> new RTLIL::Module;</span>
<span class="nb">module</span><span class="o">-</span><span class="nb">&gt;name </span><span class="o">=</span><span class="nb"> &quot;</span><span class="nv">\\</span><span class="nb">absval&quot;;</span>

<span class="nb">RTLIL::Wire </span><span class="o">*</span><span class="nb">a </span><span class="o">=</span><span class="nb"> module</span><span class="o">-</span><span class="nb">&gt;new_wire</span><span class="o">(</span><span class="m">4</span><span class="nb">, &quot;</span><span class="nv">\\</span><span class="nb">a&quot;</span><span class="o">)</span><span class="nb">;</span>
<span class="nb">a</span><span class="o">-</span><span class="nb">&gt;port_input </span><span class="o">=</span><span class="nb"> true;</span>
<span class="nb">a</span><span class="o">-</span><span class="nb">&gt;port_id </span><span class="o">=</span><span class="nb"> </span><span class="m">1</span><span class="nb">;</span>

<span class="nb">RTLIL::Wire </span><span class="o">*</span><span class="nb">y </span><span class="o">=</span><span class="nb"> module</span><span class="o">-</span><span class="nb">&gt;new_wire</span><span class="o">(</span><span class="m">4</span><span class="nb">, &quot;</span><span class="nv">\\</span><span class="nb">y&quot;</span><span class="o">)</span><span class="nb">;</span>
<span class="nb">y</span><span class="o">-</span><span class="nb">&gt;port_output </span><span class="o">=</span><span class="nb"> true;</span>
<span class="nb">y</span><span class="o">-</span><span class="nb">&gt;port_id </span><span class="o">=</span><span class="nb"> </span><span class="m">2</span><span class="nb">;</span>

<span class="nb">RTLIL::Wire </span><span class="o">*</span><span class="nb">a_inv </span><span class="o">=</span><span class="nb"> module</span><span class="o">-</span><span class="nb">&gt;new_wire</span><span class="o">(</span><span class="m">4</span><span class="nb">, NEW_ID</span><span class="o">)</span><span class="nb">;</span>
<span class="nb">module</span><span class="o">-</span><span class="nb">&gt;addNeg</span><span class="o">(</span><span class="nb">NEW_ID, a, a_inv, true</span><span class="o">)</span><span class="nb">;</span>
<span class="nb">module</span><span class="o">-</span><span class="nb">&gt;addMux</span><span class="o">(</span><span class="nb">NEW_ID, a, a_inv, RTLIL::SigSpec</span><span class="o">(</span><span class="nb">a, </span><span class="m">1</span><span class="nb">, </span><span class="m">3</span><span class="o">)</span><span class="nb">, y</span><span class="o">)</span><span class="nb">;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="nv">\subsection</span><span class="nb">{Modifying modules}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsecname</span><span class="nb">}</span>
<span class="nb">Most commands modify existing modules, not create new ones.</span>

<span class="nb">When modifying existing modules, stick to the following DOs and DON&#39;Ts:</span>

<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Do not remove wires. Simply disconnect them and let a successive {</span><span class="nv">\tt</span><span class="nb"> clean} command worry about removing it.</span>

<span class="nv">\item</span><span class="nb"> Use {</span><span class="nv">\tt</span><span class="nb"> module</span><span class="o">-</span><span class="nb">&gt;fixup</span><span class="nv">\_</span><span class="nb">ports</span><span class="o">()</span><span class="nb">} after changing the {</span><span class="nv">\tt</span><span class="nb"> port</span><span class="nv">\_</span><span class="o">*</span><span class="nb">} properties of wires.</span>

<span class="nv">\item</span><span class="nb"> You can safely remove cells or change the {</span><span class="nv">\tt</span><span class="nb"> connetions} property of a cell, but be careful when</span>
<span class="nb">changing the size of the {</span><span class="nv">\tt</span><span class="nb"> SigSpec} connected to a cell port.</span>

<span class="nv">\item</span><span class="nb"> Use the {</span><span class="nv">\tt</span><span class="nb"> SigMap} helper class </span><span class="o">(</span><span class="nb">see next slide</span><span class="o">)</span><span class="nb"> when you need a unique handle for each signal bit.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="nv">\subsection</span><span class="nb">{Using the SigMap helper class}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsecname</span><span class="nb">}</span>
<span class="nb">Consider the following module:</span>

<span class="nv">\smallskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">1</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb"></span>
<span class="nb">module test</span><span class="o">(</span><span class="nb">input a, output x, y</span><span class="o">)</span><span class="nb">;</span>
<span class="nb">    assign x </span><span class="o">=</span><span class="nb"> a, y </span><span class="o">=</span><span class="nb"> a;</span>
<span class="nb">endmodule</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nb">In this case {</span><span class="nv">\tt</span><span class="nb"> a}, {</span><span class="nv">\tt</span><span class="nb"> x}, and {</span><span class="nv">\tt</span><span class="nb"> y} are all different names for the same signal. However:</span>

<span class="nv">\smallskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">1</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb"></span>
<span class="nb">RTLIL::SigSpec a</span><span class="o">(</span><span class="nb">module</span><span class="o">-</span><span class="nb">&gt;wires.at</span><span class="o">(</span><span class="nb">&quot;</span><span class="nv">\\</span><span class="nb">a&quot;</span><span class="o">))</span><span class="nb">, x</span><span class="o">(</span><span class="nb">module</span><span class="o">-</span><span class="nb">&gt;wires.at</span><span class="o">(</span><span class="nb">&quot;</span><span class="nv">\\</span><span class="nb">x&quot;</span><span class="o">))</span><span class="nb">,</span>
<span class="nb">                                           y</span><span class="o">(</span><span class="nb">module</span><span class="o">-</span><span class="nb">&gt;wires.at</span><span class="o">(</span><span class="nb">&quot;</span><span class="nv">\\</span><span class="nb">y&quot;</span><span class="o">))</span><span class="nb">;</span>
<span class="nb">log</span><span class="o">(</span><span class="nb">&quot;</span><span class="c">%d %d %d\n&quot;, a == x, x == y, y == a); // will print &quot;0 0 0&quot;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nb">The {</span><span class="nv">\tt</span><span class="nb"> SigMap} helper class can be used to map all such aliasing signals to a</span>
<span class="nb">unique signal from the group </span><span class="o">(</span><span class="nb">usually the wire that is directly driven by a cell or port</span><span class="o">)</span><span class="nb">.</span>

<span class="nv">\smallskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">1</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb"></span>
<span class="nb">SigMap sigmap</span><span class="o">(</span><span class="nb">module</span><span class="o">)</span><span class="nb">;</span>
<span class="nb">log</span><span class="o">(</span><span class="nb">&quot;</span><span class="c">%d %d %d\n&quot;, sigmap(a) == sigmap(x), sigmap(x) == sigmap(y),</span>
<span class="nb">                  sigmap</span><span class="o">(</span><span class="nb">y</span><span class="o">)</span><span class="nb"> </span><span class="o">==</span><span class="nb"> sigmap</span><span class="o">(</span><span class="nb">a</span><span class="o">))</span><span class="nb">; </span><span class="o">//</span><span class="nb"> will print &quot;</span><span class="m">1</span><span class="nb"> </span><span class="m">1</span><span class="nb"> </span><span class="m">1</span><span class="nb">&quot;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="nv">\subsection</span><span class="nb">{Printing log messages}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsecname</span><span class="nb">}</span>
<span class="nb">The {</span><span class="nv">\tt</span><span class="nb"> log</span><span class="o">()</span><span class="nb">} function is a {</span><span class="nv">\tt</span><span class="nb"> printf</span><span class="o">()</span><span class="nb">}</span><span class="o">-</span><span class="nb">like function that can be used to create log messages.</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nb">Use {</span><span class="nv">\tt</span><span class="nb"> log</span><span class="nv">\_</span><span class="nb">signal</span><span class="o">()</span><span class="nb">} to create a C</span><span class="o">-</span><span class="nb">string for a SigSpec object</span><span class="nv">\footnote</span><span class="o">[</span><span class="nb">frame</span><span class="o">]</span><span class="nb">{The pointer returned</span>
<span class="nb">by {</span><span class="nv">\tt</span><span class="nb"> log</span><span class="nv">\_</span><span class="nb">signal</span><span class="o">()</span><span class="nb">} is automatically freed by the log framework at a later time.}:</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">1</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb"></span>
<span class="nb">log</span><span class="o">(</span><span class="nb">&quot;Mapped signal x: </span><span class="c">%s\n&quot;, log_signal(sigmap(x)));</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nb">Use {</span><span class="nv">\tt</span><span class="nb"> RTLIL::id</span><span class="m">2</span><span class="nb">cstr</span><span class="o">()</span><span class="nb">} to create a C</span><span class="o">-</span><span class="nb">string for an {</span><span class="nv">\tt</span><span class="nb"> RTLIL::IdString}:</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">1</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb"></span>
<span class="nb">log</span><span class="o">(</span><span class="nb">&quot;Name of this module: </span><span class="c">%s\n&quot;, RTLIL::id2cstr(module-&gt;name));</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nb">Use {</span><span class="nv">\tt</span><span class="nb"> log</span><span class="nv">\_</span><span class="nb">header</span><span class="o">()</span><span class="nb">} and {</span><span class="nv">\tt</span><span class="nb"> log</span><span class="nv">\_</span><span class="nb">push</span><span class="o">()</span><span class="nb">}</span><span class="o">/</span><span class="nb">{</span><span class="nv">\tt</span><span class="nb"> log</span><span class="nv">\_</span><span class="nb">pop</span><span class="o">()</span><span class="nb">} to structure log messages:</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">1</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb"></span>
<span class="nb">log_header</span><span class="o">(</span><span class="nb">&quot;Doing important stuff</span><span class="o">!</span><span class="nv">\n</span><span class="nb">&quot;</span><span class="o">)</span><span class="nb">;</span>
<span class="nb">log_push</span><span class="o">()</span><span class="nb">;</span>
<span class="nb">for </span><span class="o">(</span><span class="nb">int i </span><span class="o">=</span><span class="nb"> </span><span class="m">0</span><span class="nb">; i &lt; </span><span class="m">10</span><span class="nb">; i</span><span class="o">++)</span><span class="nb"></span>
<span class="nb">    log</span><span class="o">(</span><span class="nb">&quot;Log message #</span><span class="c">%d.\n&quot;, i);</span>
<span class="nb">log_pop</span><span class="o">()</span><span class="nb">;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="nv">\subsection</span><span class="nb">{Error handling}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsecname</span><span class="nb">}</span>
<span class="nb">Use {</span><span class="nv">\tt</span><span class="nb"> log</span><span class="nv">\_</span><span class="nb">error</span><span class="o">()</span><span class="nb">} to report a non</span><span class="o">-</span><span class="nb">recoverable error:</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">1</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb"></span>
<span class="nb">if </span><span class="o">(</span><span class="nb">design</span><span class="o">-</span><span class="nb">&gt;modules.count</span><span class="o">(</span><span class="nb">module</span><span class="o">-</span><span class="nb">&gt;name</span><span class="o">)</span><span class="nb"> </span><span class="o">!=</span><span class="nb"> </span><span class="m">0</span><span class="o">)</span><span class="nb"></span>
<span class="nb">    log_error</span><span class="o">(</span><span class="nb">&quot;A module with the name </span><span class="c">%s already exists!\n&quot;,</span>
<span class="nb">            RTLIL::id</span><span class="m">2</span><span class="nb">cstr</span><span class="o">(</span><span class="nb">module</span><span class="o">-</span><span class="nb">&gt;name</span><span class="o">))</span><span class="nb">;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">Use {</span><span class="nv">\tt</span><span class="nb"> log</span><span class="nv">\_</span><span class="nb">cmd</span><span class="nv">\_</span><span class="nb">error</span><span class="o">()</span><span class="nb">} to report a recoverable error:</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">1</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb"></span>
<span class="nb">if </span><span class="o">(</span><span class="nb">design</span><span class="o">-</span><span class="nb">&gt;selection_stack.back</span><span class="o">()</span><span class="nb">.empty</span><span class="o">())</span><span class="nb"></span>
<span class="nb">    log_cmd_error</span><span class="o">(</span><span class="nb">&quot;This command can&#39;t operator on an empty selection</span><span class="o">!</span><span class="nv">\n</span><span class="nb">&quot;</span><span class="o">)</span><span class="nb">;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">Use {</span><span class="nv">\tt</span><span class="nb"> log</span><span class="nv">\_</span><span class="nb">assert</span><span class="o">()</span><span class="nb">} and {</span><span class="nv">\tt</span><span class="nb"> log</span><span class="nv">\_</span><span class="nb">abort</span><span class="o">()</span><span class="nb">} instead of {</span><span class="nv">\tt</span><span class="nb"> assert</span><span class="o">()</span><span class="nb">} and {</span><span class="nv">\tt</span><span class="nb"> abort</span><span class="o">()</span><span class="nb">}.</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="nv">\subsection</span><span class="nb">{Creating a command}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsecname</span><span class="nb">}</span>
<span class="nb">Simply create a global instance of a class derived from {</span><span class="nv">\tt</span><span class="nb"> Pass} to create</span>
<span class="nb">a new yosys command:</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">1</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb"></span>
<span class="nb">#include &quot;kernel</span><span class="o">/</span><span class="nb">rtlil.h&quot;</span>
<span class="nb">#include &quot;kernel</span><span class="o">/</span><span class="nb">register.h&quot;</span>
<span class="nb">#include &quot;kernel</span><span class="o">/</span><span class="nb">log.h&quot;</span>

<span class="nb">struct MyPass : public Pass {</span>
<span class="nb">    MyPass</span><span class="o">()</span><span class="nb"> : Pass</span><span class="o">(</span><span class="nb">&quot;my_cmd&quot;, &quot;just a simple test&quot;</span><span class="o">)</span><span class="nb"> { }</span>
<span class="nb">    virtual void execute</span><span class="o">(</span><span class="nb">std::vector&lt;std::string&gt; args, RTLIL::Design </span><span class="o">*</span><span class="nb">design</span><span class="o">)</span><span class="nb"></span>
<span class="nb">    {</span>
<span class="nb">        log</span><span class="o">(</span><span class="nb">&quot;Arguments to my_cmd:</span><span class="nv">\n</span><span class="nb">&quot;</span><span class="o">)</span><span class="nb">;</span>
<span class="nb">        for </span><span class="o">(</span><span class="nb">auto &amp;arg : args</span><span class="o">)</span><span class="nb"></span>
<span class="nb">            log</span><span class="o">(</span><span class="nb">&quot;  </span><span class="c">%s\n&quot;, arg.c_str());</span>

<span class="nb">        log</span><span class="o">(</span><span class="nb">&quot;Modules in current design:</span><span class="nv">\n</span><span class="nb">&quot;</span><span class="o">)</span><span class="nb">;</span>
<span class="nb">        for </span><span class="o">(</span><span class="nb">auto &amp;mod : design</span><span class="o">-</span><span class="nb">&gt;modules</span><span class="o">)</span><span class="nb"></span>
<span class="nb">            log</span><span class="o">(</span><span class="nb">&quot;  </span><span class="c">%s (%zd wires, %zd cells)\n&quot;, RTLIL::id2cstr(mod.first),</span>
<span class="nb">                    mod.second</span><span class="o">-</span><span class="nb">&gt;wires.size</span><span class="o">()</span><span class="nb">, mod.second</span><span class="o">-</span><span class="nb">&gt;cells.size</span><span class="o">())</span><span class="nb">;</span>
<span class="nb">    }</span>
<span class="nb">} MyPass;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="nv">\subsection</span><span class="nb">{Creating a plugin}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsecname</span><span class="nb">}</span>
<span class="nb">Yosys can be extended by adding additional C</span><span class="o">++</span><span class="nb"> code to the Yosys code base, or</span>
<span class="nb">by loading plugins into Yosys.</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">Use the following command to compile a Yosys plugin:</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">1</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="o">]</span><span class="nb"></span>
<span class="nb">yosys</span><span class="o">-</span><span class="nb">config </span><span class="o">--</span><span class="nb">exec </span><span class="o">--</span><span class="nb">cxx </span><span class="o">--</span><span class="nb">cxxflags </span><span class="o">--</span><span class="nb">ldflags </span><span class="err">\</span><span class="nb"></span>
<span class="nb">             </span><span class="o">-</span><span class="nb">o my_cmd.so </span><span class="o">-</span><span class="nb">shared my_cmd.cc </span><span class="o">--</span><span class="nb">ldlibs</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">Load the plugin using the yosys {</span><span class="nv">\tt</span><span class="nb"> </span><span class="o">-</span><span class="nb">m} option:</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">1</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="o">]</span><span class="nb"></span>
<span class="nb">yosys </span><span class="o">-</span><span class="nb">m .</span><span class="o">/</span><span class="nb">my_cmd.so </span><span class="o">-</span><span class="nb">p &#39;my_cmd foo bar&#39;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="nv">\subsection</span><span class="nb">{Summary}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Writing Yosys extensions is very straight</span><span class="o">-</span><span class="nb">forward.</span>
<span class="nv">\item</span><span class="nb"> </span><span class="nv">\dots</span><span class="nb"> and even simpler if you don&#39;t need RTLIL::Memory or RTLIL::Process objects.</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Writing synthesis software? Consider learning the Yosys API and make your stuff</span>
<span class="nb">part of the Yosys framework.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{center}</span>
<span class="nb">Questions?</span>
<span class="nv">\end</span><span class="nb">{center}</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{center}</span>
<span class="nv">\url</span><span class="nb">{http:</span><span class="o">//</span><span class="nb">www.clifford.at</span><span class="o">/</span><span class="nb">yosys</span><span class="o">/</span><span class="nb">}</span>
<span class="nv">\end</span><span class="nb">{center}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>
</pre></div>
</code></pre></td></tr></table>
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