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<div class='path'>path: <a href='/cgit/iCE40/yosys/log/?id=a2e340de435a6cfeeeb18dc23236cc550be8ca1a&amp;showmsg=1'>root</a>/<a href='/cgit/iCE40/yosys/log/techlibs?id=a2e340de435a6cfeeeb18dc23236cc550be8ca1a&amp;showmsg=1'>techlibs</a>/<a href='/cgit/iCE40/yosys/log/techlibs/ice40?id=a2e340de435a6cfeeeb18dc23236cc550be8ca1a&amp;showmsg=1'>ice40</a></div><div class='content'><table class='list nowrap'><tr class='nohover'><th></th><th class='left'>Commit message (<a href='/cgit/iCE40/yosys/log/techlibs/ice40?id=a2e340de435a6cfeeeb18dc23236cc550be8ca1a'>Collapse</a>)</th><th class='left'>Author</th><th class='left'>Age</th><th class='left'>Files</th><th class='left'>Lines</th></tr>
<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=acd9eeef7c85f1bd72f42d86bb634769556a04c6'>ice40: Fix SPRAM model to keep data stable if chipselect is low</a></td><td>Sylvain Munaut</td><td><span title='2020-03-14 21:01:42 +0100'>2020-03-14</span></td><td>1</td><td><span class='deletions'>-5</span>/<span class='insertions'>+8</span></td></tr>
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According to the official simulation model, and also cross-checked
on real hardware, the data output of the SPRAM when chipselect is
low is kept stable. It doesn't go undefined.

Signed-off-by: Sylvain Munaut &lt;tnt@246tNt.com&gt;


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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=69f155505816e38280a12bc3998d65d03874a404'>ice40: fix specify for ICE40_{LP,U}</a></td><td>Eddie Hung</td><td><span title='2020-03-05 08:11:49 -0800'>2020-03-05</span></td><td>1</td><td><span class='deletions'>-4</span>/<span class='insertions'>+4</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=0930c00f038453685bf4d8f5366db7fe71f54cf8'>ice40: fix implicit signal in specify, also clamp negative times to 0</a></td><td>Eddie Hung</td><td><span title='2020-03-04 15:28:17 -0800'>2020-03-04</span></td><td>1</td><td><span class='deletions'>-22</span>/<span class='insertions'>+22</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>*   </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=0ec971444b0ae226417ac36d408569374269e799'>Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabc</a></td><td>N. Engelhardt</td><td><span title='2020-03-03 19:15:41 +0100'>2020-03-03</span></td><td>1</td><td><span class='deletions'>-4</span>/<span class='insertions'>+22</span></td></tr>
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Add -flowmap option to `synth{,_ice40}`

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<tr class='logheader'><td class='commitgraph'><span class='column2'>|</span> * </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=d7987fec1255c8d4ae8ad0b3e04e2172ac300604'>Add -flowmap to synth and synth_ice40</a></td><td>Dan Ravensloft</td><td><span title='2020-02-28 14:29:57 +0000'>2020-02-28</span></td><td>1</td><td><span class='deletions'>-4</span>/<span class='insertions'>+22</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* <span class='column3'>|</span> </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=6bd95501005523604d4828d1635c49e439472f79'>ice40: add delays to SB_CARRY</a></td><td>Eddie Hung</td><td><span title='2020-02-27 10:17:29 -0800'>2020-02-27</span></td><td>1</td><td><span class='deletions'>-0</span>/<span class='insertions'>+30</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* <span class='column3'>|</span> </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=aa969f87784cda995d4d7650f0a8050ef555ff62'>More +/ice40/cells_sim.v fixes</a></td><td>Eddie Hung</td><td><span title='2020-02-27 10:17:29 -0800'>2020-02-27</span></td><td>1</td><td><span class='deletions'>-27</span>/<span class='insertions'>+27</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* <span class='column3'>|</span> </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=3728ef1765b3b3375481222832d3a17600ae0312'>ice40: fix specify for inverted clocks</a></td><td>Eddie Hung</td><td><span title='2020-02-27 10:17:29 -0800'>2020-02-27</span></td><td>1</td><td><span class='deletions'>-27</span>/<span class='insertions'>+27</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* <span class='column3'>|</span> </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=a76520112d6a7ab894a3e85b7e32def6b4ff5491'>ice40: specify fixes</a></td><td>Eddie Hung</td><td><span title='2020-02-27 10:17:29 -0800'>2020-02-27</span></td><td>3</td><td><span class='deletions'>-66</span>/<span class='insertions'>+66</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* <span class='column3'>|</span> </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=fb60d82971a9de5312467c4c192148ab546504dc'>ice40: move over to specify blocks for -abc9</a></td><td>Eddie Hung</td><td><span title='2020-02-27 10:17:29 -0800'>2020-02-27</span></td><td>10</td><td><span class='deletions'>-164</span>/<span class='insertions'>+1344</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=0b0148399c81dc8c0297d8eac3b2638ed272ba58'>synth_*: call 'opt -fast' after 'techmap'</a></td><td>Eddie Hung</td><td><span title='2020-02-05 18:39:01 -0800'>2020-02-05</span></td><td>1</td><td><span class='deletions'>-0</span>/<span class='insertions'>+1</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=e18aeda7ed3b3dbf4700e25c2bc745c93541b3b8'>Fix $lut input ordering -- SigSpec(std::initializer_list&lt;&gt;) is backwards</a></td><td>Eddie Hung</td><td><span title='2020-01-27 14:02:13 -0800'>2020-01-27</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+1</span></td></tr>
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Just like Verilog...


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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=cfb0366a18b0f3cab254636fdf534a3de76af8d5'>Import tests from #1628</a></td><td>Eddie Hung</td><td><span title='2020-01-27 13:56:16 -0800'>2020-01-27</span></td><td>1</td><td><span class='deletions'>-2</span>/<span class='insertions'>+2</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=ce6a690d27f3ce3b637f1d9be42b1efd744500d2'>xilinx/ice40/ecp5: undo permuting LUT masks in lut_map</a></td><td>Eddie Hung</td><td><span title='2020-01-27 13:30:27 -0800'>2020-01-27</span></td><td>1</td><td><span class='deletions'>-7</span>/<span class='insertions'>+6</span></td></tr>
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Now done in read_aiger


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<tr class='logheader'><td class='commitgraph'>*   </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=af8281d2f5e3945a8bb93dd7c7400aafb29af3b8'>Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warnings</a></td><td>Eddie Hung</td><td><span title='2020-01-27 09:54:04 -0800'>2020-01-27</span></td><td>4</td><td><span class='deletions'>-6</span>/<span class='insertions'>+10</span></td></tr>
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ice40: reduce ABC9 internal fanout warnings with a param for CI-&gt;I3

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<tr class='logheader'><td class='commitgraph'><span class='column4'>|</span> * </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=b1787615514f84c83c27d08011427e90c9bd0f4a'>ice40: reduce ABC9 internal fanout warnings with a param for CI-&gt;I3</a></td><td>Eddie Hung</td><td><span title='2020-01-24 11:59:48 -0800'>2020-01-24</span></td><td>4</td><td><span class='deletions'>-6</span>/<span class='insertions'>+10</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* <span class='column5'>|</span> </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=81e6b040a4e9a6c8def9c4d68851e2a1f9328ed8'>ice40: add SB_SPRAM256KA arrival time</a></td><td>Eddie Hung</td><td><span title='2020-01-24 12:17:09 -0800'>2020-01-24</span></td><td>1</td><td><span class='deletions'>-0</span>/<span class='insertions'>+1</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>*   </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=a4cfd1237ff92764cea121f7025fc9f9dd07462f'>Merge pull request #1602 from niklasnisbeth/ice40-init-vals-warning</a></td><td>David Shah</td><td><span title='2020-01-18 09:47:17 +0000'>2020-01-18</span></td><td>1</td><td><span class='deletions'>-2</span>/<span class='insertions'>+8</span></td></tr>
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ice40: Demote conflicting FF init values to a warning

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<tr class='logheader'><td class='commitgraph'><span class='column6'>|</span> * </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=379dcda1398ea7a1325f82340148359ffe2bf548'>ice40: Demote conflicting FF init values to a warning</a></td><td>Niklas Nisbeth</td><td><span title='2019-12-31 02:38:10 +0100'>2019-12-31</span></td><td>1</td><td><span class='deletions'>-2</span>/<span class='insertions'>+8</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* <span class='column1'>|</span> </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=78ffd5d193a72a024204cae09ff4ab05238ed311'>synth_ice40: call wreduce before mul2dsp</a></td><td>Eddie Hung</td><td><span title='2020-01-17 15:41:55 -0800'>2020-01-17</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+2</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* <span class='column1'>|</span> </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=c0b55deb0bb189d1b6343b5d209f7fc4ac251596'>synth_ice40: -abc2 to always use `abc` even if `-abc9`</a></td><td>Eddie Hung</td><td><span title='2020-01-12 11:26:05 -0800'>2020-01-12</span></td><td>1</td><td><span class='deletions'>-10</span>/<span class='insertions'>+10</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* <span class='column1'>|</span>   </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=19541640eece245c344dbadd87a150151546789b'>Merge remote-tracking branch 'origin/master' into xaig_dff</a></td><td>Eddie Hung</td><td><span title='2020-01-06 09:31:28 -0800'>2020-01-06</span></td><td>1</td><td><span class='deletions'>-0</span>/<span class='insertions'>+2</span></td></tr>
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<tr class='logheader'><td class='commitgraph'><span class='column2'>|</span> * <span class='column1'>|</span> </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=c5d28f5d6b20a42e6f3a4b1a4e3be341a352e5e3'>Valid to have attribute starting with SB_CARRY.</a></td><td>Miodrag Milanovic</td><td><span title='2020-01-04 19:00:44 +0100'>2020-01-04</span></td><td>1</td><td><span class='deletions'>-0</span>/<span class='insertions'>+2</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* <span class='column3'>|</span> <span class='column1'>|</span> </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=b454735bea6727f346fdbbc28f261b40d91c61ba'>Merge remote-tracking branch 'origin/master' into xaig_dff</a></td><td>Eddie Hung</td><td><span title='2020-01-02 12:44:06 -0800'>2020-01-02</span></td><td>1</td><td><span class='deletions'>-2</span>/<span class='insertions'>+2</span></td></tr>
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<tr class='logheader'><td class='commitgraph'><span class='column4'>|</span> * <span class='column1'>|</span> </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=79448f9be035c88589b4e9c0de6b2bdc5acbd4df'>Update doc that "-retime" calls abc with "-dff -D 1"</a></td><td>Eddie Hung</td><td><span title='2019-12-30 13:28:29 -0800'>2019-12-30</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+1</span></td></tr>
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</td></tr>
<tr class='logheader'><td class='commitgraph'><span class='column4'>|</span> * <span class='column1'>|</span> </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=aa6d06c1b5b0083096ad547b0ad2600fcdc854f4'>Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""</a></td><td>Eddie Hung</td><td><span title='2019-12-30 13:28:29 -0800'>2019-12-30</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+1</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column4'>|</span> <span class='column1'>|</span><span class='column1'>/</span>  
<span class='column4'>|</span> <span class='column1'>|</span>   
<span class='column4'>|</span> <span class='column1'>|</span>   
<span class='column4'>|</span> <span class='column1'>|</span>   </td>
<td colspan='5' class='logmsg'>
This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745.


</td></tr>
<tr class='logheader'><td class='commitgraph'><span class='column4'>|</span> * </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=10e82e103f7b95d5a50d2ac85bc8e07e4461e388'>Revert "Optimise write_xaiger"</a></td><td>Eddie Hung</td><td><span title='2019-12-20 12:05:45 -0800'>2019-12-20</span></td><td>1</td><td><span class='deletions'>-5</span>/<span class='insertions'>+0</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column4'>|</span> <span class='column5'>|</span> </td>
<td colspan='5' class='logmsg'>
</td></tr>
<tr class='logheader'><td class='commitgraph'><span class='column4'>|</span> *   </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=df626ee7abca3446225dac9179d7e7f380774b2c'>Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup</a></td><td>Eddie Hung</td><td><span title='2019-12-19 12:24:03 -0500'>2019-12-19</span></td><td>1</td><td><span class='deletions'>-0</span>/<span class='insertions'>+5</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column4'>|</span> <span class='column6'>|</span><span class='column1'>\</span>  
<span class='column4'>|</span> <span class='column6'>|</span> <span class='column1'>|</span> 
<span class='column4'>|</span> <span class='column6'>|</span> <span class='column1'>|</span> </td>
<td colspan='5' class='logmsg'>
Optimise write_xaiger

</td></tr>
<tr class='logheader'><td class='commitgraph'><span class='column4'>|</span> <span class='column6'>|</span> * </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=98c9ea605b5cb2eb540ae5b804a18f8921f0bc46'>techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger</a></td><td>Eddie Hung</td><td><span title='2019-12-06 17:05:02 -0800'>2019-12-06</span></td><td>1</td><td><span class='deletions'>-0</span>/<span class='insertions'>+5</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column4'>|</span> <span class='column6'>|</span> <span class='column1'>|</span> </td>
<td colspan='5' class='logmsg'>
</td></tr>
<tr class='logheader'><td class='commitgraph'>* <span class='column6'>|</span> <span class='column1'>|</span> </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=2358320f5168edd691882bba0f759d82308291d6'>Cleanup ice40 boxes</a></td><td>Eddie Hung</td><td><span title='2019-12-31 18:29:37 -0800'>2019-12-31</span></td><td>3</td><td><span class='deletions'>-30</span>/<span class='insertions'>+43</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column6'>|</span><span class='column6'>/</span> <span class='column1'>/</span>  </td>
<td colspan='5' class='logmsg'>
</td></tr>
<tr class='logheader'><td class='commitgraph'>* <span class='column1'>|</span> </td><td class='logsubject'><a href='/cgit/iCE40/yosys/commit/techlibs/ice40?id=fb203d2a2c02c3df1a2c6a92ec196e57<style>pre { line-height: 125%; margin: 0; }
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.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */</style><div class="highlight"><pre><span></span><span class="k">\section</span><span class="nb">{</span>Writing Yosys extensions in C++<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>
<span class="k">\sectionpage</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Program Components and Data Formats<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>[scale=0.6, every node/.style=<span class="nb">{</span>transform shape<span class="nb">}</span>]
	<span class="k">\tikzstyle</span><span class="nb">{</span>process<span class="nb">}</span> = [draw, fill=green!10, rectangle, minimum height=3em, minimum width=10em, node distance=15em]
	<span class="k">\tikzstyle</span><span class="nb">{</span>data<span class="nb">}</span> = [draw, fill=blue!10, ellipse, minimum height=3em, minimum width=7em, node distance=15em]
	<span class="k">\node</span><span class="na">[process]</span> (vlog) <span class="nb">{</span>Verilog Frontend<span class="nb">}</span>;
	<span class="k">\node</span><span class="na">[process, dashed, fill=green!5]</span> (vhdl) [right of=vlog] <span class="nb">{</span>VHDL Frontend<span class="nb">}</span>;
	<span class="k">\node</span><span class="na">[process]</span> (ilang) [right of=vhdl] <span class="nb">{</span>Other Frontends<span class="nb">}</span>;
	<span class="k">\node</span><span class="na">[data]</span> (ast) [below of=vlog, node distance=5em, xshift=7.5em] <span class="nb">{</span>AST<span class="nb">}</span>;
	<span class="k">\node</span><span class="na">[process]</span> (astfe) [below of=ast, node distance=5em] <span class="nb">{</span>AST Frontend<span class="nb">}</span>;
	<span class="k">\node</span><span class="na">[data]</span> (rtlil) [below of=astfe, node distance=5em, xshift=7.5em] <span class="nb">{</span>RTLIL<span class="nb">}</span>;
	<span class="k">\node</span><span class="na">[process]</span> (pass) [right of=rtlil, node distance=5em, xshift=7.5em] <span class="nb">{</span>Passes<span class="nb">}</span>;
	<span class="k">\node</span><span class="na">[process]</span> (vlbe) [below of=rtlil, node distance=7em, xshift=-13em] <span class="nb">{</span>Verilog Backend<span class="nb">}</span>;
	<span class="k">\node</span><span class="na">[process]</span> (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] <span class="nb">{</span>ILANG Backend<span class="nb">}</span>;
	<span class="k">\node</span><span class="na">[process, fill=green!5]</span> (otherbe) [below of=rtlil, node distance=7em, xshift=+13em] <span class="nb">{</span>Other Backends<span class="nb">}</span>;

	<span class="k">\draw</span><span class="na">[-latex]</span> (vlog) -- (ast);
	<span class="k">\draw</span><span class="na">[-latex]</span> (vhdl) -- (ast);
	<span class="k">\draw</span><span class="na">[-latex]</span> (ast) -- (astfe);
	<span class="k">\draw</span><span class="na">[-latex]</span> (astfe) -- (rtlil);
	<span class="k">\draw</span><span class="na">[-latex]</span> (ilang) -- (rtlil);
	<span class="k">\draw</span><span class="na">[latex-latex]</span> (rtlil) -- (pass);
	<span class="k">\draw</span><span class="na">[-latex]</span> (rtlil) -- (vlbe);
	<span class="k">\draw</span><span class="na">[-latex]</span> (rtlil) -- (ilangbe);
	<span class="k">\draw</span><span class="na">[-latex]</span> (rtlil) -- (otherbe);
<span class="k">\end</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Simplified RTLIL Entity-Relationship Diagram<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
Between passses and frontends/backends the design is stored in Yosys&#39; internal
RTLIL (RTL Intermediate Language) format. For writing Yosys extensions it is
key to understand this format.

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>[scale=0.6, every node/.style=<span class="nb">{</span>transform shape<span class="nb">}</span>]
	<span class="k">\tikzstyle</span><span class="nb">{</span>entity<span class="nb">}</span> = [draw, fill=gray!10, rectangle, minimum height=3em, minimum width=7em, node distance=5em, font=<span class="nb">{</span><span class="k">\ttfamily</span><span class="nb">}</span>]
	<span class="k">\node</span><span class="na">[entity]</span> (design) <span class="nb">{</span>RTLIL::Design<span class="nb">}</span>;
	<span class="k">\node</span><span class="na">[entity]</span> (module) [right of=design, node distance=11em] <span class="nb">{</span>RTLIL::Module<span class="nb">}</span> edge [-latex] node[above] <span class="nb">{</span><span class="k">\tiny</span> 1 <span class="k">\hskip</span>3em N<span class="nb">}</span> (design);

	<span class="k">\node</span><span class="na">[entity]</span> (process) [fill=green!10, right of=module, node distance=10em] <span class="nb">{</span>RTLIL::Process<span class="nb">}</span> (process.west) edge [-latex] (module);
	<span class="k">\node</span><span class="na">[entity]</span> (memory) [fill=red!10, below of=process] <span class="nb">{</span>RTLIL::Memory<span class="nb">}</span> edge [-latex] (module);
	<span class="k">\node</span><span class="na">[entity]</span> (wire) [fill=blue!10, above of=process] <span class="nb">{</span>RTLIL::Wire<span class="nb">}</span> (wire.west) edge [-latex] (module);
	<span class="k">\node</span><span class="na">[entity]</span> (cell) [fill=blue!10, above of=wire] <span class="nb">{</span>RTLIL::Cell<span class="nb">}</span> (cell.west) edge [-latex] (module);

	<span class="k">\node</span><span class="na">[entity]</span> (case) [fill=green!10, right of=process, node distance=10em] <span class="nb">{</span>RTLIL::CaseRule<span class="nb">}</span> edge [latex-latex] (process);
	<span class="k">\node</span><span class="na">[entity]</span> (sync) [fill=green!10, above of=case] <span class="nb">{</span>RTLIL::SyncRule<span class="nb">}</span> edge [-latex] (process);
	<span class="k">\node</span><span class="na">[entity]</span> (switch) [fill=green!10, below of=case] <span class="nb">{</span>RTLIL::SwitchRule<span class="nb">}</span> edge [-latex] (case);
	<span class="k">\draw</span><span class="na">[latex-]</span> (switch.east) -- ++(1em,0) |- (case.east);
<span class="k">\end</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>RTLIL without memories and processes<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">}</span>
After the commands <span class="nb">{</span><span class="k">\tt</span> proc<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> memory<span class="nb">}</span> (or <span class="nb">{</span><span class="k">\tt</span> memory -nomap<span class="nb">}</span>), we are
left with a much simpler version of RTLIL:

<span class="k">\begin</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>[scale=0.6, every node/.style=<span class="nb">{</span>transform shape<span class="nb">}</span>]
	<span class="k">\tikzstyle</span><span class="nb">{</span>entity<span class="nb">}</span> = [draw, fill=gray!10, rectangle, minimum height=3em, minimum width=7em, node distance=5em, font=<span class="nb">{</span><span class="k">\ttfamily</span><span class="nb">}</span>]
	<span class="k">\node</span><span class="na">[entity]</span> (design) <span class="nb">{</span>RTLIL::Design<span class="nb">}</span>;
	<span class="k">\node</span><span class="na">[entity]</span> (module) [right of=design, node distance=11em] <span class="nb">{</span>RTLIL::Module<span class="nb">}</span> edge [-latex] node[above] <span class="nb">{</span><span class="k">\tiny</span> 1 <span class="k">\hskip</span>3em N<span class="nb">}</span> (design);

	<span class="k">\node</span><span class="na">[entity]</span> (wire) [fill=blue!10, right of=module, node distance=10em] <span class="nb">{</span>RTLIL::Wire<span class="nb">}</span> (wire.west) edge [-latex] (module);
	<span class="k">\node</span><span class="na">[entity]</span> (cell) [fill=blue!10, above of=wire] <span class="nb">{</span>RTLIL::Cell<span class="nb">}</span> (cell.west) edge [-latex] (module);
<span class="k">\end</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>center<span class="nb">}</span>

<span class="k">\bigskip</span>
Many commands simply choose to only work on this simpler version:
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>]
for (RTLIL::Module *module : design-&gt;selected<span class="nb">_</span>modules() <span class="nb">{</span>
    if (module-&gt;has<span class="nb">_</span>memories<span class="nb">_</span>warn() || module-&gt;has<span class="nb">_</span>processes<span class="nb">_</span>warn())
        continue;
    ....
<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

For simplicity we only discuss this version of RTLIL in this presentation.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Using dump and show commands<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> The <span class="nb">{</span><span class="k">\tt</span> dump<span class="nb">}</span> command prints the design (or parts of it) in ILANG format. This is
a text representation of RTLIL.

<span class="k">\bigskip</span>
<span class="k">\item</span> The <span class="nb">{</span><span class="k">\tt</span> show<span class="nb">}</span> command visualizes how the components in the design are connected.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\bigskip</span>
When trying to understand what a command does, create a small test case and
look at the output of <span class="nb">{</span><span class="k">\tt</span> dump<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> show<span class="nb">}</span> before and after the command
has been executed.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>The RTLIL Data Structures<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
The RTLIL data structures are simple structs utilizing <span class="nb">{</span><span class="k">\tt</span> pool&lt;&gt;<span class="nb">}</span> and
<span class="nb">{</span><span class="k">\tt</span> dict&lt;&gt;<span class="nb">}</span> containers (drop-in replacements for <span class="nb">{</span><span class="k">\tt</span>
std::unordered<span class="k">\_</span>set&lt;&gt;<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> std::unordered<span class="k">\_</span>map&lt;&gt;<span class="nb">}</span>).

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Most operations are performed directly on the RTLIL structs without
setter or getter functions.

<span class="k">\bigskip</span>
<span class="k">\item</span> In debug builds a consistency checker is run over the in-memory design
between commands to make sure that the RTLIL representation is intact.

<span class="k">\bigskip</span>
<span class="k">\item</span> Most RTLIL structs have helper methods that perform the most common operations.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\bigskip</span>
See <span class="nb">{</span><span class="k">\tt</span> yosys/kernel/rtlil.h<span class="nb">}</span> for details.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>RTLIL::IdString<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsubsecname</span><span class="nb">}{}</span>
<span class="nb">{</span><span class="k">\tt</span> RTLIL::IdString<span class="nb">}</span> in many ways behave like a <span class="nb">{</span><span class="k">\tt</span> std::string<span class="nb">}</span>. It is used
for names of RTLIL objects. Internally a RTLIL::IdString object is only a
single integer.

<span class="k">\medskip</span>
The first character of a <span class="nb">{</span><span class="k">\tt</span> RTLIL::IdString<span class="nb">}</span> specifies if the name is <span class="nb">{</span><span class="k">\it</span> public<span class="k">\/</span><span class="nb">}</span> or <span class="nb">{</span><span class="k">\it</span> private<span class="k">\/</span><span class="nb">}</span>:

<span class="k">\medskip</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> RTLIL::IdString[0] == &#39;<span class="k">\textbackslash\textbackslash</span>&#39;<span class="nb">}</span>: <span class="k">\\</span>
This is a public name. Usually this means it is a name that was declared in a Verilog file.

<span class="k">\bigskip</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> RTLIL::IdString[0] == &#39;<span class="k">\$</span>&#39;<span class="nb">}</span>: <span class="k">\\</span>
This is a private name. It was assigned by Yosys.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\bigskip</span>
Use the <span class="nb">{</span><span class="k">\tt</span> NEW<span class="k">\_</span>ID<span class="nb">}</span> macro to create a new unique private name.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>RTLIL::Design and RTLIL::Module<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
The <span class="nb">{</span><span class="k">\tt</span> RTLIL::Design<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> RTLIL::Module<span class="nb">}</span> structs are the top-level RTLIL
data structures. Yosys always operates on one active design, but can hold many designs in memory.

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
struct RTLIL::Design <span class="nb">{</span>
    dict&lt;RTLIL::IdString, RTLIL::Module*&gt; modules<span class="nb">_</span>;
    ...
<span class="nb">}</span>;

struct RTLIL::Module <span class="nb">{</span>
    RTLIL::IdString name;
    dict&lt;RTLIL::IdString, RTLIL::Wire*&gt; wires<span class="nb">_</span>;
    dict&lt;RTLIL::IdString, RTLIL::Cell*&gt; cells<span class="nb">_</span>;
    std::vector&lt;RTLIL::SigSig&gt; connections<span class="nb">_</span>;
    ...
<span class="nb">}</span>;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

(Use the various accessor functions instead of directly working with the <span class="nb">{</span><span class="k">\tt</span> *<span class="k">\_</span><span class="nb">}</span> members.)
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>The RTLIL::Wire Structure<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
Each wire in the design is represented by a <span class="nb">{</span><span class="k">\tt</span> RTLIL::Wire<span class="nb">}</span> struct:

<span class="k">\medskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
struct RTLIL::Wire <span class="nb">{</span>
    RTLIL::IdString name;
    int width, start<span class="nb">_</span>offset, port<span class="nb">_</span>id;
    bool port<span class="nb">_</span>input, port<span class="nb">_</span>output;
    ...
<span class="nb">}</span>;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\medskip</span>
<span class="k">\hfil\begin</span><span class="nb">{</span>tabular<span class="nb">}{</span>p<span class="nb">{</span>3cm<span class="nb">}</span>l<span class="nb">}</span>
<span class="nb">{</span><span class="k">\tt</span> width<span class="nb">}</span> <span class="k">\dotfill</span> <span class="nb">&amp;</span> The total number of bits. E.g. 10 for <span class="nb">{</span><span class="k">\tt</span> [9:0]<span class="nb">}</span>. <span class="k">\\</span>
<span class="nb">{</span><span class="k">\tt</span> start<span class="k">\_</span>offset<span class="nb">}</span> <span class="k">\dotfill</span> <span class="nb">&amp;</span> The lowest bit index. E.g. 3 for <span class="nb">{</span><span class="k">\tt</span> [5:3]<span class="nb">}</span>. <span class="k">\\</span>
<span class="nb">{</span><span class="k">\tt</span> port<span class="k">\_</span>id<span class="nb">}</span> <span class="k">\dotfill</span> <span class="nb">&amp;</span> Zero for non-ports. Positive index for ports. <span class="k">\\</span>
<span class="nb">{</span><span class="k">\tt</span> port<span class="k">\_</span>input<span class="nb">}</span> <span class="k">\dotfill</span> <span class="nb">&amp;</span> True for <span class="nb">{</span><span class="k">\tt</span> input<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> inout<span class="nb">}</span> ports. <span class="k">\\</span>
<span class="nb">{</span><span class="k">\tt</span> port<span class="k">\_</span>output<span class="nb">}</span> <span class="k">\dotfill</span> <span class="nb">&amp;</span> True for <span class="nb">{</span><span class="k">\tt</span> output<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> inout<span class="nb">}</span> ports. <span class="k">\\</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>RTLIL::State and RTLIL::Const<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
The <span class="nb">{</span><span class="k">\tt</span> RTLIL::State<span class="nb">}</span> enum represents a simple 1-bit logic level:

<span class="k">\smallskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
enum RTLIL::State <span class="nb">{</span>
    S0 = 0,
    S1 = 1,
    Sx = 2, // undefined value or conflict
    Sz = 3, // high-impedance / not-connected
    Sa = 4, // don&#39;t care (used only in cases)
    Sm = 5  // marker (used internally by some passes)
<span class="nb">}</span>;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
The <span class="nb">{</span><span class="k">\tt</span> RTLIL::Const<span class="nb">}</span> struct represents a constant multi-bit value:

<span class="k">\smallskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
struct RTLIL::Const <span class="nb">{</span>
    std::vector&lt;RTLIL::State&gt; bits;
    ...
<span class="nb">}</span>;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
Notice that Yosys is not using special <span class="nb">{</span><span class="k">\tt</span> VCC<span class="nb">}</span> or <span class="nb">{</span><span class="k">\tt</span> GND<span class="nb">}</span> driver cells to represent constants. Instead
constants are part of the RTLIL representation itself.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>The RTLIL::SigSpec Structure<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
The <span class="nb">{</span><span class="k">\tt</span> RTLIL::SigSpec<span class="nb">}</span> struct represents a signal vector. Each bit can either be a bit from a wire
or a constant value.

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
struct RTLIL::SigBit
<span class="nb">{</span>
    RTLIL::Wire *wire;
    union <span class="nb">{</span>
        RTLIL::State data; // used if wire == NULL
        int offset;        // used if wire != NULL
    <span class="nb">}</span>;
    ...
<span class="nb">}</span>;

struct RTLIL::SigSpec <span class="nb">{</span>
    std::vector&lt;RTLIL::SigBit&gt; bits<span class="nb">_</span>; // LSB at index 0
    ...
<span class="nb">}</span>;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
The <span class="nb">{</span><span class="k">\tt</span> RTLIL::SigSpec<span class="nb">}</span> struct has a ton of additional helper methods to compare, analyze, and
manipulate instances of <span class="nb">{</span><span class="k">\tt</span> RTLIL::SigSpec<span class="nb">}</span>.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>The RTLIL::Cell Structure<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsubsecname</span> (1/2)<span class="nb">}</span>
The <span class="nb">{</span><span class="k">\tt</span> RTLIL::Cell<span class="nb">}</span> struct represents an instance of a module or library cell.

<span class="k">\smallskip</span>
The ports of the cell
are associated with <span class="nb">{</span><span class="k">\tt</span> RTLIL::SigSpec<span class="nb">}</span> instances and the parameters are associated with <span class="nb">{</span><span class="k">\tt</span> RTLIL::Const<span class="nb">}</span>
instances:

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
struct RTLIL::Cell <span class="nb">{</span>
    RTLIL::IdString name, type;
    dict&lt;RTLIL::IdString, RTLIL::SigSpec&gt; connections<span class="nb">_</span>;
    dict&lt;RTLIL::IdString, RTLIL::Const&gt; parameters;
    ...
<span class="nb">}</span>;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
The <span class="nb">{</span><span class="k">\tt</span> type<span class="nb">}</span> may refer to another module in the same design, a cell name from a cell library, or a
cell name from the internal cell library:

<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>6pt<span class="nb">}{</span>7pt<span class="nb">}</span><span class="k">\selectfont</span>]
<span class="s">$</span><span class="nb">not </span><span class="s">$</span>pos <span class="s">$</span><span class="nb">neg </span><span class="s">$</span>and <span class="s">$</span><span class="nb">or </span><span class="s">$</span>xor <span class="s">$</span><span class="nb">xnor </span><span class="s">$</span>reduce<span class="nb">_</span>and <span class="s">$</span><span class="nb">reduce_or </span><span class="s">$</span>reduce<span class="nb">_</span>xor <span class="s">$</span><span class="nb">reduce_xnor</span>
<span class="s">$</span>reduce<span class="nb">_</span>bool <span class="s">$</span><span class="nb">shl </span><span class="s">$</span>shr <span class="s">$</span><span class="nb">sshl </span><span class="s">$</span>sshr <span class="s">$</span><span class="nb">lt </span><span class="s">$</span>le <span class="s">$</span><span class="nb">eq </span><span class="s">$</span>ne <span class="s">$</span><span class="nb">eqx </span><span class="s">$</span>nex <span class="s">$</span><span class="nb">ge </span><span class="s">$</span>gt <span class="s">$</span><span class="nb">add </span><span class="s">$</span>sub <span class="s">$</span><span class="nb">mul </span><span class="s">$</span>div <span class="s">$</span><span class="nb">mod</span>
<span class="s">$</span>pow <span class="s">$</span><span class="nb">logic_not </span><span class="s">$</span>logic<span class="nb">_</span>and <span class="s">$</span><span class="nb">logic_or </span><span class="s">$</span>mux <span class="s">$</span><span class="nb">pmux </span><span class="s">$</span>slice <span class="s">$</span><span class="nb">concat </span><span class="s">$</span>lut <span class="s">$</span><span class="nb">assert </span><span class="s">$</span>sr <span class="s">$</span><span class="nb">dff</span>
<span class="s">$</span>dffsr <span class="s">$</span><span class="nb">adff </span><span class="s">$</span>dlatch <span class="s">$</span><span class="nb">dlatchsr </span><span class="s">$</span>memrd <span class="s">$</span><span class="nb">memwr </span><span class="s">$</span>mem <span class="s">$</span><span class="nb">fsm </span><span class="s">$</span><span class="nb">_</span>NOT<span class="nb">_</span> <span class="s">$</span><span class="nb">_AND_ </span><span class="s">$</span><span class="nb">_</span>OR<span class="nb">_</span> <span class="s">$</span><span class="nb">_XOR_ </span><span class="s">$</span><span class="nb">_</span>MUX<span class="nb">_</span> <span class="s">$</span><span class="nb">_SR_NN_</span>
<span class="s">$</span><span class="nb">_</span>SR<span class="nb">_</span>NP<span class="nb">_</span> <span class="s">$</span><span class="nb">_SR_PN_ </span><span class="s">$</span><span class="nb">_</span>SR<span class="nb">_</span>PP<span class="nb">_</span> <span class="s">$</span><span class="nb">_DFF_N_ </span><span class="s">$</span><span class="nb">_</span>DFF<span class="nb">_</span>P<span class="nb">_</span> <span class="s">$</span><span class="nb">_DFF_NN</span><span class="m">0</span><span class="nb">_ </span><span class="s">$</span><span class="nb">_</span>DFF<span class="nb">_</span>NN1<span class="nb">_</span> <span class="s">$</span><span class="nb">_DFF_NP</span><span class="m">0</span><span class="nb">_ </span><span class="s">$</span><span class="nb">_</span>DFF<span class="nb">_</span>NP1<span class="nb">_</span> <span class="s">$</span><span class="nb">_DFF_PN</span><span class="m">0</span><span class="nb">_</span>
<span class="s">$</span><span class="nb">_</span>DFF<span class="nb">_</span>PN1<span class="nb">_</span> <span class="s">$</span><span class="nb">_DFF_PP</span><span class="m">0</span><span class="nb">_ </span><span class="s">$</span><span class="nb">_</span>DFF<span class="nb">_</span>PP1<span class="nb">_</span> <span class="s">$</span><span class="nb">_DFFSR_NNN_ </span><span class="s">$</span><span class="nb">_</span>DFFSR<span class="nb">_</span>NNP<span class="nb">_</span> <span class="s">$</span><span class="nb">_DFFSR_NPN_ </span><span class="s">$</span><span class="nb">_</span>DFFSR<span class="nb">_</span>NPP<span class="nb">_</span> <span class="s">$</span><span class="nb">_DFFSR_PNN_</span>
<span class="s">$</span><span class="nb">_</span>DFFSR<span class="nb">_</span>PNP<span class="nb">_</span> <span class="s">$</span><span class="nb">_DFFSR_PPN_ </span><span class="s">$</span><span class="nb">_</span>DFFSR<span class="nb">_</span>PPP<span class="nb">_</span> <span class="s">$</span><span class="nb">_DLATCH_N_ </span><span class="s">$</span><span class="nb">_</span>DLATCH<span class="nb">_</span>P<span class="nb">_</span> <span class="s">$</span><span class="nb">_DLATCHSR_NNN_ </span><span class="s">$</span><span class="nb">_</span>DLATCHSR<span class="nb">_</span>NNP<span class="nb">_</span>
<span class="s">$</span><span class="nb">_DLATCHSR_NPN_ </span><span class="s">$</span><span class="nb">_</span>DLATCHSR<span class="nb">_</span>NPP<span class="nb">_</span> <span class="s">$</span><span class="nb">_DLATCHSR_PNN_ </span><span class="s">$</span><span class="nb">_</span>DLATCHSR<span class="nb">_</span>PNP<span class="nb">_</span> <span class="s">$</span><span class="nb">_DLATCHSR_PPN_ </span><span class="s">$</span><span class="nb">_</span>DLATCHSR<span class="nb">_</span>PPP<span class="nb">_</span>
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsubsecname</span> (2/2)<span class="nb">}</span>
Simulation models (i.e. <span class="nb">{</span><span class="k">\it</span> documentation<span class="k">\/</span><span class="nb">}</span> :-) for the internal cell library:

<span class="k">\smallskip</span>
<span class="k">\hskip</span>2em <span class="nb">{</span><span class="k">\tt</span> yosys/techlibs/common/simlib.v<span class="nb">}</span> and <span class="k">\\</span>
<span class="k">\hskip</span>2em <span class="nb">{</span><span class="k">\tt</span> yosys/techlibs/common/simcells.v<span class="nb">}</span>

<span class="k">\bigskip</span>
The lower-case cell types (such as <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>and<span class="nb">}</span>) are parameterized cells of variable
width. This so-called <span class="nb">{</span><span class="k">\it</span> RTL Cells<span class="k">\/</span><span class="nb">}</span> are the cells described in <span class="nb">{</span><span class="k">\tt</span> simlib.v<span class="nb">}</span>.

<span class="k">\bigskip</span>
The upper-case cell types (such as <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>AND<span class="k">\_</span><span class="nb">}</span>) are single-bit cells that are not
parameterized. This so-called <span class="nb">{</span><span class="k">\it</span> Internal Logic Gates<span class="nb">}</span> are the cells described
in <span class="nb">{</span><span class="k">\tt</span> simcells.v<span class="nb">}</span>.

<span class="k">\bigskip</span>
The consistency checker also checks the interfaces to the internal cell library.
If you want to use private cell types for your own purposes, use the <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_\_</span><span class="nb">}</span>-prefix
to avoid name collisions.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>Connecting wires or constant drivers<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
Additional connections between wires or between wires and constants are modelled using
<span class="nb">{</span><span class="k">\tt</span> RTLIL::Module::connections<span class="nb">}</span>:

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
typedef std::pair&lt;RTLIL::SigSpec, RTLIL::SigSpec&gt; RTLIL::SigSig;

struct RTLIL::Module <span class="nb">{</span>
    ...
    std::vector&lt;RTLIL::SigSig&gt; connections<span class="nb">_</span>;
    ...
<span class="nb">}</span>;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="nb">{</span><span class="k">\tt</span> RTLIL::SigSig::first<span class="nb">}</span> is the driven signal and <span class="nb">{</span><span class="k">\tt</span> RTLIL::SigSig::second<span class="nb">}</span> is the driving signal.
Example usage (setting wire <span class="nb">{</span><span class="k">\tt</span> foo<span class="nb">}</span> to value <span class="nb">{</span><span class="k">\tt</span> 42<span class="nb">}</span>):
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
module-&gt;connect(module-&gt;wire(&quot;<span class="k">\\</span>foo&quot;),
                RTLIL::SigSpec(42, module-&gt;wire(&quot;<span class="k">\\</span>foo&quot;)-&gt;width));
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Creating modules from scratch<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">}</span>
Let&#39;s create the following module using the RTLIL API:

<span class="k">\smallskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=Verilog]
module absval(input signed [3:0] a, output [3:0] y);
    assign y = a[3] ? -a : a;
endmodule
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\smallskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
RTLIL::Module *module = new RTLIL::Module;
module-&gt;name = &quot;<span class="k">\\</span>absval&quot;;

RTLIL::Wire *a = module-&gt;addWire(&quot;<span class="k">\\</span>a&quot;, 4);
a-&gt;port<span class="nb">_</span>input = true;
a-&gt;port<span class="nb">_</span>id = 1;

RTLIL::Wire *y = module-&gt;addWire(&quot;<span class="k">\\</span>y&quot;, 4);
y-&gt;port<span class="nb">_</span>output = true;
y-&gt;port<span class="nb">_</span>id = 2;

RTLIL::Wire *a<span class="nb">_</span>inv = module-&gt;addWire(NEW<span class="nb">_</span>ID, 4);
module-&gt;addNeg(NEW<span class="nb">_</span>ID, a, a<span class="nb">_</span>inv, true);
module-&gt;addMux(NEW<span class="nb">_</span>ID, a, a<span class="nb">_</span>inv, RTLIL::SigSpec(a, 1, 3), y);

module-&gt;fixup<span class="nb">_</span>ports();
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Modifying modules<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
Most commands modify existing modules, not create new ones.

When modifying existing modules, stick to the following DOs and DON&#39;Ts:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Do not remove wires. Simply disconnect them and let a successive <span class="nb">{</span><span class="k">\tt</span> clean<span class="nb">}</span> command worry about removing it.

<span class="k">\item</span> Use <span class="nb">{</span><span class="k">\tt</span> module-&gt;fixup<span class="k">\_</span>ports()<span class="nb">}</span> after changing the <span class="nb">{</span><span class="k">\tt</span> port<span class="k">\_*</span><span class="nb">}</span> properties of wires.

<span class="k">\item</span> You can safely remove cells or change the <span class="nb">{</span><span class="k">\tt</span> connections<span class="nb">}</span> property of a cell, but be careful when
changing the size of the <span class="nb">{</span><span class="k">\tt</span> SigSpec<span class="nb">}</span> connected to a cell port.

<span class="k">\item</span> Use the <span class="nb">{</span><span class="k">\tt</span> SigMap<span class="nb">}</span> helper class (see next slide) when you need a unique handle for each signal bit.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Using the SigMap helper class<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">}</span>
Consider the following module:

<span class="k">\smallskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=Verilog]
module test(input a, output x, y);
    assign x = a, y = a;
endmodule
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

In this case <span class="nb">{</span><span class="k">\tt</span> a<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> x<span class="nb">}</span>, and <span class="nb">{</span><span class="k">\tt</span> y<span class="nb">}</span> are all different names for the same signal. However:

<span class="k">\smallskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
RTLIL::SigSpec a(module-&gt;wire(&quot;<span class="k">\\</span>a&quot;)), x(module-&gt;wire(&quot;<span class="k">\\</span>x&quot;)),
                                       y(module-&gt;wire(&quot;<span class="k">\\</span>y&quot;));
log(&quot;<span class="c">%d %d %d\n&quot;, a == x, x == y, y == a); // will print &quot;0 0 0&quot;</span>
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

The <span class="nb">{</span><span class="k">\tt</span> SigMap<span class="nb">}</span> helper class can be used to map all such aliasing signals to a
unique signal from the group (usually the wire that is directly driven by a cell or port).

<span class="k">\smallskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
SigMap sigmap(module);
log(&quot;<span class="c">%d %d %d\n&quot;, sigmap(a) == sigmap(x), sigmap(x) == sigmap(y),</span>
                  sigmap(y) == sigmap(a)); // will print &quot;1 1 1&quot;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Printing log messages<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">}</span>
The <span class="nb">{</span><span class="k">\tt</span> log()<span class="nb">}</span> function is a <span class="nb">{</span><span class="k">\tt</span> printf()<span class="nb">}</span>-like function that can be used to create log messages.

<span class="k">\medskip</span>
Use <span class="nb">{</span><span class="k">\tt</span> log<span class="k">\_</span>signal()<span class="nb">}</span> to create a C-string for a SigSpec object<span class="k">\footnote</span><span class="na">[frame]</span><span class="nb">{</span>The pointer returned
by <span class="nb">{</span><span class="k">\tt</span> log<span class="k">\_</span>signal()<span class="nb">}</span> is automatically freed by the log framework at a later time.<span class="nb">}</span>:
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
log(&quot;Mapped signal x: <span class="c">%s\n&quot;, log_signal(sigmap(x)));</span>
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\medskip</span>
Use <span class="nb">{</span><span class="k">\tt</span> log<span class="k">\_</span>id()<span class="nb">}</span> to create a C-string for an <span class="nb">{</span><span class="k">\tt</span> RTLIL::IdString<span class="nb">}</span>:
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
log(&quot;Name of this module: <span class="c">%s\n&quot;, log_id(module-&gt;name));</span>
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\medskip</span>
Use <span class="nb">{</span><span class="k">\tt</span> log<span class="k">\_</span>header()<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> log<span class="k">\_</span>push()<span class="nb">}</span>/<span class="nb">{</span><span class="k">\tt</span> log<span class="k">\_</span>pop()<span class="nb">}</span> to structure log messages:
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
log<span class="nb">_</span>header(design, &quot;Doing important stuff!<span class="k">\n</span>&quot;);
log<span class="nb">_</span>push();
for (int i = 0; i &lt; 10; i++)
    log(&quot;Log message #<span class="c">%d.\n&quot;, i);</span>
log<span class="nb">_</span>pop();
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Error handling<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">}</span>
Use <span class="nb">{</span><span class="k">\tt</span> log<span class="k">\_</span>error()<span class="nb">}</span> to report a non-recoverable error:

<span class="k">\medskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
if (design-&gt;modules.count(module-&gt;name) != 0)
    log<span class="nb">_</span>error(&quot;A module with the name <span class="c">%s already exists!\n&quot;,</span>
            RTLIL::id2cstr(module-&gt;name));
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
Use <span class="nb">{</span><span class="k">\tt</span> log<span class="k">\_</span>cmd<span class="k">\_</span>error()<span class="nb">}</span> to report a recoverable error:
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
if (design-&gt;selection<span class="nb">_</span>stack.back().empty())
    log<span class="nb">_</span>cmd<span class="nb">_</span>error(&quot;This command can&#39;t operator on an empty selection!<span class="k">\n</span>&quot;);
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
Use <span class="nb">{</span><span class="k">\tt</span> log<span class="k">\_</span>assert()<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> log<span class="k">\_</span>abort()<span class="nb">}</span> instead of <span class="nb">{</span><span class="k">\tt</span> assert()<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> abort()<span class="nb">}</span>.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Creating a command<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">}</span>
Simply create a global instance of a class derived from <span class="nb">{</span><span class="k">\tt</span> Pass<span class="nb">}</span> to create
a new yosys command:

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=C++]
#include &quot;kernel/yosys.h&quot;
USING<span class="nb">_</span>YOSYS<span class="nb">_</span>NAMESPACE

struct MyPass : public Pass <span class="nb">{</span>
    MyPass() : Pass(&quot;my<span class="nb">_</span>cmd&quot;, &quot;just a simple test&quot;) <span class="nb">{</span> <span class="nb">}</span>
    virtual void execute(std::vector&lt;std::string&gt; args, RTLIL::Design *design)
    <span class="nb">{</span>
        log(&quot;Arguments to my<span class="nb">_</span>cmd:<span class="k">\n</span>&quot;);
        for (auto <span class="nb">&amp;</span>arg : args)
            log(&quot;  <span class="c">%s\n&quot;, arg.c_str());</span>

        log(&quot;Modules in current design:<span class="k">\n</span>&quot;);
        for (auto mod : design-&gt;modules())
            log(&quot;  <span class="c">%s (%d wires, %d cells)\n&quot;, log_id(mod),</span>
                    GetSize(mod-&gt;wires()), GetSize(mod-&gt;cells()));
    <span class="nb">}</span>
<span class="nb">}</span> MyPass;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Creating a plugin<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">}</span>
Yosys can be extended by adding additional C++ code to the Yosys code base, or
by loading plugins into Yosys.

<span class="k">\bigskip</span>
Use the following command to compile a Yosys plugin:
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>]
yosys-config --exec --cxx --cxxflags --ldflags <span class="k">\</span>
             -o my<span class="nb">_</span>cmd.so -shared my<span class="nb">_</span>cmd.cc --ldlibs
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
Or shorter:
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>]
yosys-config --build my<span class="nb">_</span>cmd.so my<span class="nb">_</span>cmd.cc
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
Load the plugin using the yosys <span class="nb">{</span><span class="k">\tt</span> -m<span class="nb">}</span> option:
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>]
yosys -m ./my<span class="nb">_</span>cmd.so -p &#39;my<span class="nb">_</span>cmd foo bar&#39;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Summary<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Writing Yosys extensions is very straight-forward.
<span class="k">\item</span> <span class="k">\dots</span> and even simpler if you don&#39;t need RTLIL::Memory or RTLIL::Process objects.

<span class="k">\bigskip</span>
<span class="k">\item</span> Writing synthesis software? Consider learning the Yosys API and make your work
part of the Yosys framework.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>center<span class="nb">}</span>
Questions?
<span class="k">\end</span><span class="nb">{</span>center<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\url</span><span class="nb">{</span>http://www.clifford.at/yosys/<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>
</pre></div>
</code></pre></td></tr></table>
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