Content-Security-Policy: default-src 'none'
Content-Type: text/plain; charset=UTF-8
Content-Length: 38854
Content-Disposition: inline; filename="setup.c"
Last-Modified: Sat, 13 Dec 2025 05:24:09 GMT
Expires: Tue, 11 Dec 2035 05:24:09 GMT
ETag: "89994066424d45a3a905e4ad509d7e3982cf8b51"

#include <xen/config.h>
#include <xen/init.h>
#include <xen/lib.h>
#include <xen/sched.h>
#include <xen/sched-if.h>
#include <xen/domain.h>
#include <xen/serial.h>
#include <xen/softirq.h>
#include <xen/acpi.h>
#include <xen/console.h>
#include <xen/serial.h>
#include <xen/trace.h>
#include <xen/multiboot.h>
#include <xen/domain_page.h>
#include <xen/version.h>
#include <xen/gdbstub.h>
#include <xen/percpu.h>
#include <xen/hypercall.h>
#include <xen/keyhandler.h>
#include <xen/numa.h>
#include <xen/rcupdate.h>
#include <xen/vga.h>
#include <xen/dmi.h>
#include <xen/nodemask.h>
#include <public/version.h>
#ifdef CONFIG_COMPAT
#include <compat/platform.h>
#include <compat/xen.h>
#endif
#include <asm/bitops.h>
#include <asm/smp.h>
#include <asm/processor.h>
#include <asm/mpspec.h>
#include <asm/apic.h>
#include <asm/desc.h>
#include <asm/paging.h>
#include <asm/e820.h>
#include <xsm/acm/acm_hooks.h>
#include <xen/kexec.h>
#include <asm/edd.h>
#include <xsm/xsm.h>
#include <asm/tboot.h>
#include <asm/bzimage.h> /* for bzimage_headroom */
#include <asm/mach-generic/mach_apic.h> /* for generic_apic_probe */
#include <asm/setup.h>
#include <xen/cpu.h>

#if defined(CONFIG_X86_64)
#define BOOTSTRAP_DIRECTMAP_END (1UL << 32) /* 4GB */
#define maddr_to_bootstrap_virt(m) maddr_to_virt(m)
#else
#define BOOTSTRAP_DIRECTMAP_END (1UL << 30) /* 1GB */
#define maddr_to_bootstrap_virt(m) ((void *)(long)(m))
#endif

extern u16 boot_edid_caps;
extern u8 boot_edid_info[128];
extern struct boot_video_info boot_vid_info;

/* opt_nosmp: If true, secondary processors are ignored. */
static int __initdata opt_nosmp = 0;
boolean_param("nosmp", opt_nosmp);

/* maxcpus: maximum number of CPUs to activate. */
static unsigned int __initdata max_cpus = NR_CPUS;
integer_param("maxcpus", max_cpus);

/* opt_watchdog: If true, run a watchdog NMI on each processor. */
static int __initdata opt_watchdog = 0;
boolean_param("watchdog", opt_watchdog);

/* opt_tsc_unstable: Override all tests; assume TSC is unreliable. */
static int opt_tsc_unstable;
boolean_param("tsc_unstable", opt_tsc_unstable);

/* **** Linux config option: propagated to domain0. */
/* "acpi=off":    Sisables both ACPI table parsing and interpreter. */
/* "acpi=force":  Override the disable blacklist.                   */
/* "acpi=strict": Disables out-of-spec workarounds.                 */
/* "acpi=ht":     Limit ACPI just to boot-time to enable HT.        */
/* "acpi=noirq":  Disables ACPI interrupt routing.                  */
static void parse_acpi_param(char *s);
custom_param("acpi", parse_acpi_param);

/* **** Linux config option: propagated to domain0. */
/* acpi_skip_timer_override: Skip IRQ0 overrides. */
boolean_param("acpi_skip_timer_override", acpi_skip_timer_override);

/* **** Linux config option: propagated to domain0. */
/* noapic: Disable IOAPIC setup. */
boolean_param("noapic", skip_ioapic_setup);

/* **** Linux config option: propagated to domain0. */
/* xen_cpuidle: xen control cstate. */
/*static*/ int xen_cpuidle = -1;
boolean_param("cpuidle", xen_cpuidle);

int early_boot = 1;

cpumask_t __read_mostly cpu_present_map;

unsigned long __read_mostly xen_phys_start;

#ifdef CONFIG_X86_32
/* Limits of Xen heap, used to initialise the allocator. */
unsigned long __initdata xenheap_initial_phys_start;
unsigned long __read_mostly xenheap_phys_end;
#endif

DEFINE_PER_CPU(struct tss_struct, init_tss);

char __attribute__ ((__section__(".bss.stack_aligned"))) cpu0_stack[STACK_SIZE];

struct cpuinfo_x86 __read_mostly boot_cpu_data = { 0, 0, 0, 0, -1 };

unsigned long __read_mostly mmu_cr4_features = X86_CR4_PSE | X86_CR4_PGE | X86_CR4_PAE;

int __read_mostly acpi_disabled;

int __read_mostly acpi_force;
static char __initdata acpi_param[10] = "";
static void __init parse_acpi_param(char *s)
{
    /* Save the parameter so it can be propagated to domain0. */
    safe_strcpy(acpi_param, s);

    /* Interpret the parameter for use within Xen. */
    if ( !strcmp(s, "off") )
    {
        disable_acpi();
    }
    else if ( !strcmp(s, "force") )
    {
        acpi_force = 1;
        acpi_ht = 1;
        acpi_disabled = 0;
    }
    else if ( !strcmp(s, "strict") )
    {
        acpi_strict = 1;
    }
    else if ( !strcmp(s, "ht") )
    {
        if ( !acpi_force )
            disable_acpi();
        acpi_ht = 1;
    }
    else if ( !strcmp(s, "noirq") )
    {
        acpi_noirq_set();
    }
}

#define EARLY_FAIL(f, a...) do {                \
    printk( f , ## a );                         \
    for ( ; ; ) halt();                         \
} while (0)

static unsigned long __initdata initial_images_base;
static unsigned long __initdata initial_images_start;
static unsigned long __initdata initial_images_end;

unsigned long __init initial_images_nrpages(void)
{
    ASSERT(!(initial_images_base & ~PAGE_MASK));
    ASSERT(!(initial_images_end   & ~PAGE_MASK));
    return ((initial_images_end >> PAGE_SHIFT) -
            (initial_images_base >> PAGE_SHIFT));
}

void __init discard_initial_images(void)
{
    init_domheap_pages(initial_images_base, initial_images_end);
}

static void free_xen_data(char *s, char *e)
{
#ifndef MEMORY_GUARD
    init_xenheap_pages(__pa(s), __pa(e));
#endif
    memguard_guard_range(s, e-s);
#if defined(CONFIG_X86_64)
    /* Also zap the mapping in the 1:1 area. */
    memguard_guard_range(__va(__pa(s)), e-s);
#endif
}

extern char __init_begin[], __init_end[], __bss_start[];

static void __init init_idle_domain(void)
{
    struct domain *idle_domain;

    /* Domain creation requires that scheduler structures are initialised. */
    scheduler_init();

    idle_domain = domain_create(IDLE_DOMAIN_ID, 0, 0);
    if ( idle_domain == NULL )
        BUG();
    idle_domain->vcpu = idle_vcpu;
    idle_domain->max_vcpus = NR_CPUS;
    if ( alloc_vcpu(idle_domain, 0, 0) == NULL )
        BUG();

    set_current(idle_vcpu[0]);
    this_cpu(curr_vcpu) = current;

    setup_idle_pagetable();
}

void __devinit srat_detect_node(int cpu)
{
    unsigned node;
    u32 apicid = x86_cpu_to_apicid[cpu];

    node = apicid_to_node[apicid];
    if ( node == NUMA_NO_NODE || !node_online(node) )
        node = 0;
    numa_set_node(cpu, node);

    if ( opt_cpu_info && acpi_numa > 0 )
        printk("CPU %d APIC %d -> Node %d\n", cpu, apicid, node);
}

/*
 * Ensure a given physical memory range is present in the bootstrap mappings.
 * Use superpage mappings to ensure that pagetable memory needn't be allocated.
 */
static void __init bootstrap_map(unsigned long start, unsigned long end)
{
    unsigned long mask = (1UL << L2_PAGETABLE_SHIFT) - 1;
    start = max_t(unsigned long, start & ~mask, 16UL << 20);
    end   = (end + mask) & ~mask;
    if ( start >= end )
        return;
    if ( end > BOOTSTRAP_DIRECTMAP_END )
        panic("Cannot access memory beyond end of "
              "bootstrap direct-map area\n");
    map_pages_to_xen(
        (unsigned long)maddr_to_bootstrap_virt(start),
        start >> PAGE_SHIFT, (end-start) >> PAGE_SHIFT, PAGE_HYPERVISOR);
}

static void __init move_memory(
    unsigned long dst, unsigned long src_start, unsigned long src_end)
{
    bootstrap_map(src_start, src_end);
    bootstrap_map(dst, dst + src_end - src_start);
    memmove(maddr_to_bootstrap_virt(dst),
            maddr_to_bootstrap_virt(src_start),
            src_end - src_start);
}

static void __init setup_max_pdx(void)
{
#ifdef __x86_64__
    max_pdx = pfn_to_pdx(max_page - 1) + 1;

    if ( max_pdx > (DIRECTMAP_SIZE >> PAGE_SHIFT) )
        max_pdx = DIRECTMAP_SIZE >> PAGE_SHIFT;

    if ( max_pdx > FRAMETABLE_SIZE / sizeof(*frame_table) )
        max_pdx = FRAMETABLE_SIZE / sizeof(*frame_table);

    max_page = pdx_to_pfn(max_pdx - 1) + 1;
#endif
}

void set_pdx_range(unsigned long smfn, unsigned long emfn)
{
    unsigned long idx, eidx;

    idx = pfn_to_pdx(smfn) / PDX_GROUP_COUNT;
    eidx = (pfn_to_pdx(emfn - 1) + PDX_GROUP_COUNT) / PDX_GROUP_COUNT;
    for ( ; idx < eidx; ++idx )
        __set_bit(idx, pdx_group_valid);
}

/* A temporary copy of the e820 map that we can mess with during bootstrap. */
static struct e820map __initdata boot_e820;

struct boot_video_info {
    u8  orig_x;             /* 0x00 */
    u8  orig_y;             /* 0x01 */
    u8  orig_video_mode;    /* 0x02 */
    u8  orig_video_cols;    /* 0x03 */
    u8  orig_video_lines;   /* 0x04 */
    u8  orig_video_isVGA;   /* 0x05 */
    u16 orig_video_points;  /* 0x06 */

    /* VESA graphic mode -- linear frame buffer */
    u32 capabilities;       /* 0x08 */
    u16 lfb_linelength;     /* 0x0c */
    u16 lfb_width;          /* 0x0e */
    u16 lfb_height;         /* 0x10 */
    u16 lfb_depth;          /* 0x12 */
    u32 lfb_base;           /* 0x14 */
    u32 lfb_size;           /* 0x18 */
    u8  red_size;           /* 0x1c */
    u8  red_pos;            /* 0x1d */
    u8  green_size;         /* 0x1e */
    u8  green_pos;          /* 0x1f */
    u8  blue_size;          /* 0x20 */
    u8  blue_pos;           /* 0x21 */
    u8  rsvd_size;          /* 0x22 */
    u8  rsvd_pos;           /* 0x23 */
    u16 vesapm_seg;         /* 0x24 */
    u16 vesapm_off;         /* 0x26 */
    u16 vesa_attrib;        /* 0x28 */
};

static void __init parse_video_info(void)
{
    struct boot_video_info *bvi = &bootsym(boot_vid_info);

    if ( (bvi->orig_video_isVGA == 1) && (bvi->orig_video_mode == 3) )
    {
        vga_console_info.video_type = XEN_VGATYPE_TEXT_MODE_3;
        vga_console_info.u.text_mode_3.font_height = bvi->orig_video_points;
        vga_console_info.u.text_mode_3.cursor_x = bvi->orig_x;
        vga_console_info.u.text_mode_3.cursor_y = bvi->orig_y;
        vga_console_info.u.text_mode_3.rows = bvi->orig_video_lines;
        vga_console_info.u.text_mode_3.columns = bvi->orig_video_cols;
    }
    else if ( bvi->orig_video_isVGA == 0x23 )
    {
        vga_console_info.video_type = XEN_VGATYPE_VESA_LFB;
        vga_console_info.u.vesa_lfb.width = bvi->lfb_width;
        vga_console_info.u.vesa_lfb.height = bvi->lfb_height;
        vga_console_info.u.vesa_lfb.bytes_per_line = bvi->lfb_linelength;
        vga_console_info.u.vesa_lfb.bits_per_pixel = bvi->lfb_depth;
        vga_console_info.u.vesa_lfb.lfb_base = bvi->lfb_base;
        vga_console_info.u.vesa_lfb.lfb_size = bvi->lfb_size;
        vga_console_info.u.vesa_lfb.red_pos = bvi->red_pos;
        vga_console_info.u.vesa_lfb.red_size = bvi->red_size;
        vga_console_info.u.vesa_lfb.green_pos = bvi->green_pos;
        vga_console_info.u.vesa_lfb.green_size = bvi->green_size;
        vga_console_info.u.vesa_lfb.blue_pos = bvi->blue_pos;
        vga_console_info.u.vesa_lfb.blue_size = bvi->blue_size;
        vga_console_info.u.vesa_lfb.rsvd_pos = bvi->rsvd_pos;
        vga_console_info.u.vesa_lfb.rsvd_size = bvi->rsvd_size;
        vga_console_info.u.vesa_lfb.gbl_caps = bvi->capabilities;
        vga_console_info.u.vesa_lfb.mode_attrs = bvi->vesa_attrib;
    }
}

static void __init kexec_reserve_area(struct e820map *e820)
{
    unsigned long kdump_start = kexec_crash_area.start;
    unsigned long kdump_size  = kexec_crash_area.size;
    static int is_reserved = 0;

    kdump_size = (kdump_size + PAGE_SIZE - 1) & PAGE_MASK;

    if ( (kdump_start == 0) || (kdump_size == 0) || is_reserved )
        return;

    is_reserved = 1;

    if ( !reserve_e820_ram(e820, kdump_start, kdump_start + kdump_size) )
    {
        printk("Kdump: DISABLED (failed to reserve %luMB (%lukB) at 0x%lx)"
               "\n", kdump_size >> 20, kdump_size >> 10, kdump_start);
        kexec_crash_area.start = kexec_crash_area.size = 0;
    }
    else
    {
        printk("Kdump: %luMB (%lukB) at 0x%lx\n",
               kdump_size >> 20, kdump_size >> 10, kdump_start);
    }
}

void init_done(void)
{
    /* Free (or page-protect) the init areas. */
    memset(__init_begin, 0xcc, __init_end - __init_begin); /* int3 poison */
    free_xen_data(__init_begin, __init_end);
    printk("Freed %ldkB init memory.\n", (long)(__init_end-__init_begin)>>10);

    startup_cpu_idle_loop();
}

static char * __init cmdline_cook(char *p)
{
    p = p ? : "";
    while ( *p == ' ' )
        p++;
    while ( (*p != ' ') && (*p != '\0') )
        p++;
    while ( *p == ' ' )
        p++;
    return p;
}

void __init __start_xen(unsigned long mbi_p)
{
    char *memmap_type = NULL;
    char *cmdline, *kextra;
    unsigned long _initrd_start = 0, _initrd_len = 0;
    unsigned int initrdidx = 1;
    multiboot_info_t *mbi = __va(mbi_p);
    module_t *mod = (module_t *)__va(mbi->mods_addr);
    unsigned long nr_pages, modules_length, modules_headroom;
    int i, j, e820_warn = 0, bytes = 0;
    bool_t acpi_boot_table_init_done = 0;
    struct ns16550_defaults ns16550 = {
        .data_bits = 8,
        .parity    = 'n',
        .stop_bits = 1
    };

    percpu_init_areas();

    set_intr_gate(TRAP_page_fault, &early_page_fault);

    /* Parse the command-line options. */
    cmdline = cmdline_cook((mbi->flags & MBI_CMDLINE) ?
                           __va(mbi->cmdline) : NULL);
    if ( (kextra = strstr(cmdline, " -- ")) != NULL )
    {
        /*
         * Options after ' -- ' separator belong to dom0.
         *  1. Orphan dom0's options from Xen's command line.
         *  2. Skip all but final leading space from dom0's options.
         */
        *kextra = '\0';
        kextra += 3;
        while ( kextra[1] == ' ' ) kextra++;
    }
    cmdline_parse(cmdline);

    /* If TSC is marked as unstable, clear all enhanced TSC features. */
    if ( opt_tsc_unstable )
    {
        setup_clear_cpu_cap(X86_FEATURE_CONSTANT_TSC);
        setup_clear_cpu_cap(X86_FEATURE_NONSTOP_TSC);
        setup_clear_cpu_cap(X86_FEATURE_TSC_RELIABLE);
    }

    parse_video_info();

    set_current((struct vcpu *)0xfffff000); /* debug sanity */
    idle_vcpu[0] = current;
    set_processor_id(0); /* needed early, for smp_processor_id() */
    if ( cpu_has_efer )
        rdmsrl(MSR_EFER, this_cpu(efer));
    asm volatile ( "mov %%cr4,%0" : "=r" (this_cpu(cr4)) );

    smp_prepare_boot_cpu();

    /* We initialise the serial devices very early so we can get debugging. */
    ns16550.io_base = 0x3f8;
    ns16550.irq     = 4;
    ns16550_init(0, &ns16550);
    ns16550.io_base = 0x2f8;
    ns16550.irq     = 3;
    ns16550_init(1, &ns16550);
    console_init_preirq();

    printk("Command line: %s\n", cmdline);

    printk("Video information:\n");

    /* Print VGA display mode information. */
    switch ( vga_console_info.video_type )
    {
    case XEN_VGATYPE_TEXT_MODE_3:
        printk(" VGA is text mode %dx%d, font 8x%d\n",
               vga_console_info.u.text_mode_3.columns,
               vga_console_info.u.text_mode_3.rows,
               vga_console_info.u.text_mode_3.font_height);
        break;
    case XEN_VGATYPE_VESA_LFB:
        printk(" VGA is graphics mode %dx%d, %d bpp\n",
               vga_console_info.u.vesa_lfb.width,
               vga_console_info.u.vesa_lfb.height,
               vga_console_info.u.vesa_lfb.bits_per_pixel);
        break;
    default:
        printk(" No VGA detected\n");
        break;
    }

    /* Print VBE/DDC EDID information. */
    if ( bootsym(boot_edid_caps) != 0x1313 )
    {
        u16 caps = bootsym(boot_edid_caps);
        printk(" VBE/DDC methods:%s%s%s; ",
               (caps & 1) ? " V1" : "",
               (caps & 2) ? " V2" : "",
               !(caps & 3) ? " none" : "");
        printk("EDID transfer time: %d seconds\n", caps >> 8);
        if ( *(u32 *)bootsym(boot_edid_info) == 0x13131313 )
        {
            printk(" EDID info not retrieved because ");
            if ( !(caps & 3) )
                printk("no DDC retrieval method detected\n");
            else if ( (caps >> 8) > 5 )
                printk("takes longer than 5 seconds\n");
            else
                printk("of reasons unknown\n");
        }
    }

    printk("Disc information:\n");
    printk(" Found %d MBR signatures\n",
           bootsym(boot_mbr_signature_nr));
    printk(" Found %d EDD information structures\n",
           bootsym(boot_edd_info_nr));

    /* Check that we have at least one Multiboot module. */
    if ( !(mbi->flags & MBI_MODULES) || (mbi->mods_count == 0) )
        EARLY_FAIL("dom0 kernel not specified. "
                   "Check bootloader configuration.\n");

    if ( ((unsigned long)cpu0_stack & (STACK_SIZE-1)) != 0 )
        EARLY_FAIL("Misaligned CPU0 stack.\n");

    if ( e820_raw_nr != 0 )
    {
        memmap_type = "Xen-e820";
    }
    else if ( bootsym(lowmem_kb) )
    {
        memmap_type = "Xen-e801";
        e820_raw[0].addr = 0;
        e820_raw[0].size = bootsym(lowmem_kb) << 10;
        e820_raw[0].type = E820_RAM;
        e820_raw[1].addr = 0x100000;
        e820_raw[1].size = bootsym(highmem_kb) << 10;
        e820_raw[1].type = E820_RAM;
        e820_raw_nr = 2;
    }
    else if ( mbi->flags & MBI_MEMMAP )
    {
        memmap_type = "Multiboot-e820";
        while ( (bytes < mbi->mmap_length) && (e820_raw_nr < E820MAX) )
        {
            memory_map_t *map = __va(mbi->mmap_addr + bytes);

            /*
             * This is a gross workaround for a BIOS bug. Some bootloaders do
             * not write e820 map entries into pre-zeroed memory. This is
             * okay if the BIOS fills in all fields of the map entry, but
             * some broken BIOSes do not bother to write the high word of
             * the length field if the length is smaller than 4GB. We
             * detect and fix this by flagging sections below 4GB that
             * appear to be larger than 4GB in size.
             */
            if ( (map->base_addr_high == 0) && (map->length_high != 0) )
            {
                if ( !e820_warn )
                {
                    printk("WARNING: Buggy e820 map detected and fixed "
                           "(truncated length fields).\n");
                    e820_warn = 1;
                }
                map->length_high = 0;
            }

            e820_raw[e820_raw_nr].addr = 
                ((u64)map->base_addr_high << 32) | (u64)map->base_addr_low;
            e820_raw[e820_raw_nr].size = 
                ((u64)map->length_high << 32) | (u64)map->length_low;
            e820_raw[e820_raw_nr].type = map->type;
            e820_raw_nr++;

            bytes += map->size + 4;
        }
    }
    else if ( mbi->flags & MBI_MEMLIMITS )
    {
        memmap_type = "Multiboot-e801";
        e820_raw[0].addr = 0;
        e820_raw[0].size = mbi->mem_lower << 10;
        e820_raw[0].type = E820_RAM;
        e820_raw[1].addr = 0x100000;
        e820_raw[1].size = mbi->mem_upper << 10;
        e820_raw[1].type = E820_RAM;
        e820_raw_nr = 2;
    }
    else
    {
        EARLY_FAIL("Bootloader provided no memory information.\n");
    }

    /* Sanitise the raw E820 map to produce a final clean version. */
    max_page = init_e820(memmap_type, e820_raw, &e820_raw_nr);

    /* Create a temporary copy of the E820 map. */
    memcpy(&boot_e820, &e820, sizeof(e820));

    /* Early kexec reservation (explicit static start address). */
    nr_pages = 0;
    for ( i = 0; i < e820.nr_map; i++ )
        if ( e820.map[i].type == E820_RAM )
            nr_pages += e820.map[i].size >> PAGE_SHIFT;
    set_kexec_crash_area_size((u64)nr_pages << PAGE_SHIFT);
    kexec_reserve_area(&boot_e820);

    /*
     * Iterate backwards over all superpage-aligned RAM regions.
     * 
     * We require superpage alignment because the boot allocator is not yet
     * initialised. Hence we can only map superpages in the address range
     * 0 to BOOTSTRAP_DIRECTMAP_END, as this is guaranteed not to require
     * dynamic allocation of pagetables.
     * 
     * As well as mapping superpages in that range, in preparation for
     * initialising the boot allocator, we also look for a region to which
     * we can relocate the dom0 kernel and other multiboot modules. Also, on
     * x86/64, we relocate Xen to higher memory.
     */
    modules_length = 0;
    for ( i = 0; i < mbi->mods_count; i++ )
        modules_length += mod[i].mod_end - mod[i].mod_start;

    /* ensure mod[0] is mapped before parsing */
    bootstrap_map(mod[0].mod_start, mod[0].mod_end);
    modules_headroom = bzimage_headroom(
                      (char *)(unsigned long)mod[0].mod_start,
                      (unsigned long)(mod[0].mod_end - mod[0].mod_start));

    for ( i = boot_e820.nr_map-1; i >= 0; i-- )
    {
        uint64_t s, e, mask = (1UL << L2_PAGETABLE_SHIFT) - 1;

        /* Superpage-aligned chunks from 16MB to BOOTSTRAP_DIRECTMAP_END. */
        s = (boot_e820.map[i].addr + mask) & ~mask;
        e = (boot_e820.map[i].addr + boot_e820.map[i].size) & ~mask;
        s = max_t(uint64_t, s, 16 << 20);
        e = min_t(uint64_t, e, BOOTSTRAP_DIRECTMAP_END);
        if ( (boot_e820.map[i].type != E820_RAM) || (s >= e) )
            continue;

        set_pdx_range(s >> PAGE_SHIFT, e >> PAGE_SHIFT);

        /* Map the chunk. No memory will need to be allocated to do this. */
        map_pages_to_xen(
            (unsigned long)maddr_to_bootstrap_virt(s),
            s >> PAGE_SHIFT, (e-s) >> PAGE_SHIFT, PAGE_HYPERVISOR);

#if defined(CONFIG_X86_64)
#define reloc_size ((__pa(&_end) + mask) & ~mask)
        /* Is the region suitable for relocating Xen? */
        if ( !xen_phys_start && ((e-s) >= reloc_size) )
        {
            extern l2_pgentry_t l2_xenmap[];
            l4_pgentry_t *pl4e;
            l3_pgentry_t *pl3e;
            l2_pgentry_t *pl2e;
            int i, j, k;

            /* Select relocation address. */
            e -= reloc_size;
            xen_phys_start = e;
            bootsym(trampoline_xen_phys_start) = e;

            /*
             * Perform relocation to new physical address.
             * Before doing so we must sync static/global data with main memory
             * with a barrier(). After this we must *not* modify static/global
             * data until after we have switched to the relocated pagetables!
             */
            barrier();
            move_memory(e, 0, __pa(&_end) - xen_phys_start);

            /* Poison low 1MB to detect stray pointers to physical 0-1MB. */
            memset(maddr_to_bootstrap_virt(e), 0x55, 1U<<20);

            /* Walk initial pagetables, relocating page directory entries. */
            pl4e = __va(__pa(idle_pg_table));
            for ( i = 0 ; i < L4_PAGETABLE_ENTRIES; i++, pl4e++ )
            {
                if ( !(l4e_get_flags(*pl4e) & _PAGE_PRESENT) )
                    continue;
                *pl4e = l4e_from_intpte(l4e_get_intpte(*pl4e) +
                                        xen_phys_start);
                pl3e = l4e_to_l3e(*pl4e);
                for ( j = 0; j < L3_PAGETABLE_ENTRIES; j++, pl3e++ )
                {
                    /* Not present, 1GB mapping, or already relocated? */
                    if ( !(l3e_get_flags(*pl3e) & _PAGE_PRESENT) ||
                         (l3e_get_flags(*pl3e) & _PAGE_PSE) ||
                         (l3e_get_pfn(*pl3e) > 0x1000) )
                        continue;
                    *pl3e = l3e_from_intpte(l3e_get_intpte(*pl3e) +
                                            xen_phys_start);
                    pl2e = l3e_to_l2e(*pl3e);
                    for ( k = 0; k < L2_PAGETABLE_ENTRIES; k++, pl2e++ )
                    {
                        /* Not present, PSE, or already relocated? */
                        if ( !(l2e_get_flags(*pl2e) & _PAGE_PRESENT) ||
                             (l2e_get_flags(*pl2e) & _PAGE_PSE) ||
                             (l2e_get_pfn(*pl2e) > 0x1000) )
                            continue;
                        *pl2e = l2e_from_intpte(l2e_get_intpte(*pl2e) +
                                                xen_phys_start);
                    }
                }
            }

            /* The only data mappings to be relocated are in the Xen area. */
            pl2e = __va(__pa(l2_xenmap));
            *pl2e++ = l2e_from_pfn(xen_phys_start >> PAGE_SHIFT,
                                   PAGE_HYPERVISOR | _PAGE_PSE);
            for ( i = 1; i < L2_PAGETABLE_ENTRIES; i++, pl2e++ )
            {
                if ( !(l2e_get_flags(*pl2e) & _PAGE_PRESENT) )
                    continue;
                *pl2e = l2e_from_intpte(l2e_get_intpte(*pl2e) +
                                        xen_phys_start);
            }

            /* Re-sync the stack and then switch to relocated pagetables. */
            asm volatile (
                "rep movsb        ; " /* re-sync the stack */
                "movq %%cr4,%%rsi ; "
                "andb $0x7f,%%sil ; "
                "movq %%rsi,%%cr4 ; " /* CR4.PGE == 0 */
                "movq %0,%%cr3    ; " /* CR3 == new pagetables */
                "orb $0x80,%%sil  ; "
                "movq %%rsi,%%cr4   " /* CR4.PGE == 1 */
                : : "r" (__pa(idle_pg_table)), "S" (cpu0_stack),
                "D" (__va(__pa(cpu0_stack))), "c" (STACK_SIZE) : "memory" );
        }
#endif

        /* Is the region suitable for relocating the multiboot modules? */
        if ( !initial_images_start && (s < e) &&
             ((e-s) >= (modules_length+modules_headroom)) )
        {
            initial_images_end = e;
            initial_images_start = initial_images_end - modules_length;
            initial_images_base = initial_images_start - modules_headroom;
            initial_images_base &= PAGE_MASK;
            for ( j = mbi->mods_count-1; j >= 0; j-- )
            {
                e -= mod[j].mod_end - mod[j].mod_start;
                move_memory(e, mod[j].mod_start, mod[j].mod_end);
                mod[j].mod_end += e - mod[j].mod_start;
                mod[j].mod_start = e;
            }
            e = initial_images_base;
        }

        if ( !kexec_crash_area.start && (s < e) &&
             ((e-s) >= kexec_crash_area.size) )
        {
            e = (e - kexec_crash_area.size) & PAGE_MASK;
            kexec_crash_area.start = e;
        }
    }

    if ( !initial_images_start )
        EARLY_FAIL("Not enough memory to relocate the dom0 kernel image.\n");
    reserve_e820_ram(&boot_e820, initial_images_base, initial_images_end);

#if defined(CONFIG_X86_32)
    xenheap_initial_phys_start = (PFN_UP(__pa(&_end)) + 1) << PAGE_SHIFT;
    /* Must pass a single mapped page for populating bootmem_region_list. */
    init_boot_pages(__pa(&_end), xenheap_initial_phys_start);
    xenheap_phys_end = DIRECTMAP_MBYTES << 20;
#else
    if ( !xen_phys_start )
        EARLY_FAIL("Not enough memory to relocate Xen.\n");
    reserve_e820_ram(&boot_e820, __pa(&_start), __pa(&_end));
#endif

    /* Late kexec reservation (dynamic start address). */
    kexec_reserve_area(&boot_e820);

    setup_max_pdx();

    /*
     * Walk every RAM region and map it in its entirety (on x86/64, at least)
     * and notify it to the boot allocator.
     */
    for ( i = 0; i < boot_e820.nr_map; i++ )
    {
        uint64_t s, e, map_s, map_e, mask = PAGE_SIZE - 1;

        /* Only page alignment required now. */
        s = (boot_e820.map[i].addr + mask) & ~mask;
        e = (boot_e820.map[i].addr + boot_e820.map[i].size) & ~mask;
#if defined(CONFIG_X86_32)
        s = max_t(uint64_t, s, xenheap_phys_end);
#else
        s = max_t(uint64_t, s, 1<<20);
#endif
        if ( (boot_e820.map[i].type != E820_RAM) || (s >= e) )
            continue;

#ifdef __x86_64__
        if ( !acpi_boot_table_init_done &&
             s >= BOOTSTRAP_DIRECTMAP_END &&
             !acpi_boot_table_init() )
        {
            acpi_boot_table_init_done = 1;
            srat_parse_regions(s);
            setup_max_pdx();
        }

        if ( pfn_to_pdx((e - 1) >> PAGE_SHIFT) >= max_pdx )
        {
            if ( pfn_to_pdx(s >> PAGE_SHIFT) >= max_pdx )
            {
                for ( j = i - 1; ; --j )
                {
                    if ( boot_e820.map[j].type == E820_RAM )
                        break;
                    ASSERT(j);
                }
                map_e = boot_e820.map[j].addr + boot_e820.map[j].size;
                if ( (map_e >> PAGE_SHIFT) < max_page )
                {
                    max_page = map_e >> PAGE_SHIFT;
                    max_pdx = pfn_to_pdx(max_page - 1) + 1;
                }
                printk(XENLOG_WARNING "Ignoring inaccessible memory range"
                                      " %013"PRIx64"-%013"PRIx64"\n",
                       s, e);
                continue;
            }
            map_e = e;
            e = (pdx_to_pfn(max_pdx - 1) + 1ULL) << PAGE_SHIFT;
            printk(XENLOG_WARNING "Ignoring inaccessible memory range"
                                  " %013"PRIx64"-%013"PRIx64"\n",
                   e, map_e);
        }
#endif

        set_pdx_range(s >> PAGE_SHIFT, e >> PAGE_SHIFT);

        /* Need to create mappings above 16MB. */
        map_s = max_t(uint64_t, s, 16<<20);
        map_e = e;
#if defined(CONFIG_X86_32) /* mappings are truncated on x86_32 */
        map_e = min_t(uint64_t, map_e, BOOTSTRAP_DIRECTMAP_END);
#endif

        /* Pass mapped memory to allocator /before/ creating new mappings. */
        init_boot_pages(s, min_t(uint64_t, map_s, e));

        /* Create new mappings /before/ passing memory to the allocator. */
        if ( map_s < map_e )
            map_pages_to_xen(
                (unsigned long)maddr_to_bootstrap_virt(map_s),
                map_s >> PAGE_SHIFT, (map_e-map_s) >> PAGE_SHIFT,
                PAGE_HYPERVISOR);

        /* Pass remainder of this memory chunk to the allocator. */
        init_boot_pages(map_s, e);
    }

    memguard_init();

    nr_pages = 0;
    for ( i = 0; i < e820.nr_map; i++ )
        if ( e820.map[i].type == E820_RAM )
            nr_pages += e820.map[i].size >> PAGE_SHIFT;
    printk("System RAM: %luMB (%lukB)\n",
           nr_pages >> (20 - PAGE_SHIFT),
           nr_pages << (PAGE_SHIFT - 10));
    total_pages = nr_pages;

    /* Sanity check for unwanted bloat of certain hypercall structures. */
    BUILD_BUG_ON(sizeof(((struct xen_platform_op *)0)->u) !=
                 sizeof(((struct xen_platform_op *)0)->u.pad));
    BUILD_BUG_ON(sizeof(((struct xen_domctl *)0)->u) !=
                 sizeof(((struct xen_domctl *)0)->u.pad));
    BUILD_BUG_ON(sizeof(((struct xen_sysctl *)0)->u) !=
                 sizeof(((struct xen_sysctl *)0)->u.pad));

    BUILD_BUG_ON(sizeof(start_info_t) > PAGE_SIZE);
    BUILD_BUG_ON(sizeof(shared_info_t) > PAGE_SIZE);
    BUILD_BUG_ON(sizeof(struct vcpu_info) != 64);

#ifdef CONFIG_COMPAT
    BUILD_BUG_ON(sizeof(((struct compat_platform_op *)0)->u) !=
                 sizeof(((struct compat_platform_op *)0)->u.pad));
    BUILD_BUG_ON(sizeof(start_info_compat_t) > PAGE_SIZE);
    BUILD_BUG_ON(sizeof(struct compat_vcpu_info) != 64);
#endif

    /* Check definitions in public headers match internal defs. */
    BUILD_BUG_ON(__HYPERVISOR_VIRT_START != HYPERVISOR_VIRT_START);
#ifdef HYPERVISOR_VIRT_END
    BUILD_BUG_ON(__HYPERVISOR_VIRT_END   != HYPERVISOR_VIRT_END);
#endif
    BUILD_BUG_ON(MACH2PHYS_VIRT_START != RO_MPT_VIRT_START);
    BUILD_BUG_ON(MACH2PHYS_VIRT_END   != RO_MPT_VIRT_END);

    init_frametable();

    if ( !acpi_boot_table_init_done )
        acpi_boot_table_init();

    acpi_numa_init();

    numa_initmem_init(0, max_page);

#if defined(CONFIG_X86_32)
    /* Initialise the Xen heap. */
    for ( nr_pages = i = 0; i < boot_e820.nr_map; i++ )
    {
        uint64_t s = boot_e820.map[i].addr;
        uint64_t e = s + boot_e820.map[i].size;
        s = max_t(uint64_t, s, xenheap_initial_phys_start);
        e = min_t(uint64_t, e, xenheap_phys_end);
        if ( (boot_e820.map[i].type != E820_RAM) || (s >= e) )
            continue;
        init_xenheap_pages(s, e);
        nr_pages += (e - s) >> PAGE_SHIFT;
    }
    printk("Xen heap: %luMB (%lukB)\n", 
           nr_pages >> (20 - PAGE_SHIFT),
           nr_pages << (PAGE_SHIFT - 10));
#endif

    end_boot_allocator();
    early_boot = 0;

#if defined(CONFIG_X86_64)
    vesa_init();
#endif

    softirq_init();
    tasklet_subsys_init();

    early_cpu_init();

    paging_init();

    tboot_probe();

    /* Unmap the first page of CPU0's stack. */
    memguard_guard_stack(cpu0_stack);

    open_softirq(NEW_TLBFLUSH_CLOCK_PERIOD_SOFTIRQ, new_tlbflush_clock_period);

    if ( opt_watchdog ) 
        nmi_watchdog = NMI_LOCAL_APIC;

    sort_exception_tables();

    find_smp_config();

    dmi_scan_machine();

    generic_apic_probe();

    acpi_boot_init();

    if ( x2apic_is_available() )
        enable_x2apic();

    init_cpu_to_node();

    if ( smp_found_config )
        get_smp_config();

#ifdef CONFIG_X86_64
    /* Low mappings were only needed for some BIOS table parsing. */
    zap_low_mappings();
#endif

    init_apic_mappings();

    init_IRQ();

    xsm_init(&initrdidx, mbi, initial_images_start);

    timer_init();

    init_idle_domain();

    trap_init();

    rcu_init();
    
    early_time_init();

    arch_init_memory();

    identify_cpu(&boot_cpu_data);
    if ( cpu_has_fxsr )
        set_in_cr4(X86_CR4_OSFXSR);
    if ( cpu_has_xmm )
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.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */</style><div class="highlight"><pre><span></span><span class="k">\section</span><span class="nb">{</span>Yosys by example -- Advanced Synthesis<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>
<span class="k">\sectionpage</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span>Overview<span class="nb">}</span>
This section contains 4 subsections:
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Using selections
<span class="k">\item</span> Advanced uses of techmap
<span class="k">\item</span> Coarse-grain synthesis
<span class="k">\item</span> Automatic design changes
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Using selections<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>
<span class="k">\subsectionpage</span>
<span class="k">\subsectionpagesuffix</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>Simple selections<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
Most Yosys commands make use of the ``selection framework&#39;&#39; of Yosys. It can be used
to apply commands only to part of the design. For example:

<span class="k">\medskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
delete                # will delete the whole design, but

delete foobar         # will only delete the module foobar.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
The <span class="nb">{</span><span class="k">\tt</span> select<span class="nb">}</span> command can be used to create a selection for subsequent
commands. For example:

<span class="k">\medskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
select foobar         # select the module foobar
delete                # delete selected objects
select -clear         # reset selection (select whole design)
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>Selection by object name<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
The easiest way to select objects is by object name. This is usually only done
in synthesis scripts that are hand-tailored for a specific design.

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
select foobar         # select module foobar
select foo*           # select all modules whose names start with foo
select foo*/bar*      # select all objects matching bar* from modules matching foo*
select */clk          # select objects named clk from all modules
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>Module and design context<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
Commands can be executed in <span class="nb">{</span><span class="k">\it</span> module<span class="k">\/</span><span class="nb">}</span> or <span class="nb">{</span><span class="k">\it</span> design<span class="k">\/</span><span class="nb">}</span> context. Until now all
commands have been executed in design context. The <span class="nb">{</span><span class="k">\tt</span> cd<span class="nb">}</span> command can be used
to switch to module context.

<span class="k">\bigskip</span>
In module context all commands only effect the active module. Objects in the module
are selected without the <span class="nb">{</span><span class="k">\tt</span> &lt;module<span class="k">\_</span>name&gt;/<span class="nb">}</span> prefix. For example:

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
cd foo                # switch to module foo
delete bar            # delete object foo/bar

cd mycpu              # switch to module mycpu
dump reg<span class="nb">_</span>*            # print details on all objects whose names start with reg<span class="nb">_</span>

cd ..                 # switch back to design
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
Note: Most synthesis scripts never switch to module context. But it is a very powerful
tool for interactive design investigation.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>Selecting by object property or type<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
Special patterns can be used to select by object property or type. For example:

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
select w:reg<span class="nb">_</span>*        # select all wires whose names start with reg<span class="nb">_</span>
select a:foobar       # select all objects with the attribute foobar set
select a:foobar=42    # select all objects with the attribute foobar set to 42
select A:blabla       # select all modules with the attribute blabla set
select foo/t:<span class="s">$</span><span class="nb">add     # select all </span><span class="s">$</span>add cells from the module foo
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
A complete list of this pattern expressions can be found in the command
reference to the <span class="nb">{</span><span class="k">\tt</span> select<span class="nb">}</span> command.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>Combining selection<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
When more than one selection expression is used in one statement, then they are
pushed on a stack. The final elements on the stack are combined into a union:

<span class="k">\medskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
select t:<span class="s">$</span><span class="nb">dff r:WIDTH&gt;</span><span class="m">1</span><span class="nb">     # all cells of type </span><span class="s">$</span>dff and/or with a parameter WIDTH &gt; 1
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
Special <span class="k">\%</span>-commands can be used to combine the elements on the stack:

<span class="k">\medskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
select t:<span class="s">$</span><span class="nb">dff r:WIDTH&gt;</span><span class="m">1</span><span class="nb"> </span><span class="c">%i  # all cells of type $dff *AND* with a parameter WIDTH &gt; 1</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{block}{Examples for {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">}</span><span class="o">-</span><span class="nb">codes </span><span class="o">(</span><span class="nb">see {</span><span class="nv">\tt</span><span class="nb"> help select} for full list</span><span class="o">)</span><span class="nb">}</span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">u} </span><span class="nv">\dotfill</span><span class="nb"> union of top two elements on stack </span><span class="o">--</span><span class="nb"> pop </span><span class="m">2</span><span class="nb">, push </span><span class="m">1</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">d} </span><span class="nv">\dotfill</span><span class="nb"> difference of top two elements on stack </span><span class="o">--</span><span class="nb"> pop </span><span class="m">2</span><span class="nb">, push </span><span class="m">1</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">i} </span><span class="nv">\dotfill</span><span class="nb"> intersection of top two elements on stack </span><span class="o">--</span><span class="nb"> pop </span><span class="m">2</span><span class="nb">, push </span><span class="m">1</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">n} </span><span class="nv">\dotfill</span><span class="nb"> inverse of top element on stack </span><span class="o">--</span><span class="nb"> pop </span><span class="m">1</span><span class="nb">, push </span><span class="m">1</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{block}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Expanding selections}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nb">Selections of cells and wires can be expanded along connections using {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">}</span><span class="o">-</span><span class="nb">codes</span>
<span class="nb">for selecting input cones </span><span class="o">(</span><span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">ci}</span><span class="o">)</span><span class="nb">, output cones </span><span class="o">(</span><span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">co}</span><span class="o">)</span><span class="nb">, or both </span><span class="o">(</span><span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">x}</span><span class="o">)</span><span class="nb">.</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb"># select all wires that are inputs to </span><span class="s">$</span>add cells
select t:<span class="s">$</span><span class="nb">add </span><span class="c">%ci w:* %i</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">Additional constraints such as port names can be specified.</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb"># select all wires that connect a &quot;Q&quot; output with a &quot;D&quot; input</span>
<span class="nb">select c:</span><span class="o">*</span><span class="nb"> </span><span class="c">%co:+[Q] w:* %i c:* %ci:+[D] w:* %i %i</span>

<span class="nb"># select the multiplexer tree that drives the signal &#39;state&#39;</span>
<span class="nb">select state </span><span class="c">%ci*:+$mux,$pmux[A,B,Y]</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">See {</span><span class="nv">\tt</span><span class="nb"> help select} for full documentation of this expressions.</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Incremental selection}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nb">Sometimes a selection can most easily be described by a series of add</span><span class="o">/</span><span class="nb">delete operations.</span>
<span class="nb">The commands {</span><span class="nv">\tt</span><span class="nb"> select </span><span class="o">-</span><span class="nb">add} and {</span><span class="nv">\tt</span><span class="nb"> select </span><span class="o">-</span><span class="nb">del} respectively add or remove objects</span>
<span class="nb">from the current selection instead of overwriting it.</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">select </span><span class="o">-</span><span class="nb">none            # start with an empty selection</span>
<span class="nb">select </span><span class="o">-</span><span class="nb">add reg_</span><span class="o">*</span><span class="nb">       # select a bunch of objects</span>
<span class="nb">select </span><span class="o">-</span><span class="nb">del reg_</span><span class="m">42</span><span class="nb">      # but not this one</span>
<span class="nb">select </span><span class="o">-</span><span class="nb">add state </span><span class="c">%ci   # and add mor stuff</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">Within a select expression the token {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">} can be used to push the previous selection</span>
<span class="nb">on the stack.</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">select t:</span><span class="s">$</span>add t:<span class="s">$</span><span class="nb">sub    # select all </span><span class="s">$</span>add and <span class="s">$</span><span class="nb">sub cells</span>
<span class="nb">select </span><span class="c">% %ci % %d       # select only the input wires to those cells</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Creating selection variables}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nb">Selections can be stored under a name with the {</span><span class="nv">\tt</span><span class="nb"> select </span><span class="o">-</span><span class="nb">set &lt;name&gt;}</span>
<span class="nb">command. The stored selections can be used in later select expressions</span>
<span class="nb">using the syntax {</span><span class="nv">\tt</span><span class="nb"> @&lt;name&gt;}.</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">select </span><span class="o">-</span><span class="nb">set cone_a state_a </span><span class="c">%ci*:-$dff  # set @cone_a to the input cone of state_a</span>
<span class="nb">select </span><span class="o">-</span><span class="nb">set cone_b state_b </span><span class="c">%ci*:-$dff  # set @cone_b to the input cone of state_b</span>
<span class="nb">select @cone_a @cone_b </span><span class="c">%i              # select the objects that are in both cones</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">Remember that select expressions can also be used directly as arguments to most</span>
<span class="nb">commands. Some commands also except a single select argument to some options.</span>
<span class="nb">In those cases selection variables must be used to capture more complex selections.</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">dump @cone_a @cone_b</span>

<span class="nb">select </span><span class="o">-</span><span class="nb">set cone_ab @cone_a @cone_b </span><span class="c">%i</span>
<span class="nb">show </span><span class="o">-</span><span class="nb">color red @cone_ab </span><span class="o">-</span><span class="nb">color magenta @cone_a </span><span class="o">-</span><span class="nb">color blue @cone_b</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example}</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">4</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">6</span><span class="nb">pt}{</span><span class="m">7</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">select.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">7</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys, frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">select.ys}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\hfil\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="nv">\linewidth</span><span class="nb">,trim</span><span class="o">=</span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm </span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">select.pdf}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="nv">\subsection</span><span class="nb">{Advanced uses of techmap}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span>
<span class="nv">\subsectionpage</span><span class="nb"></span>
<span class="nv">\subsectionpagesuffix</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Introduction to techmap}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"></span>
<span class="nb">The {</span><span class="nv">\tt</span><span class="nb"> techmap} command replaces cells in the design with implementations given</span>
<span class="nb">as Verilog code </span><span class="o">(</span><span class="nb">called ``map files&#39;&#39;</span><span class="o">)</span><span class="nb">. It can replace Yosys&#39; internal cell</span>
<span class="nb">types </span><span class="o">(</span><span class="nb">such as {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$</span><span class="nb">or}</span><span class="o">)</span><span class="nb"> as well as user</span><span class="o">-</span><span class="nb">defined cell types.</span>
<span class="nv">\medskip\item</span><span class="nb"></span>
<span class="nb">Verilog parameters are used extensively to customize the internal cell types.</span>
<span class="nv">\medskip\item</span><span class="nb"></span>
<span class="nb">Additional special parameters are used by techmap to communicate meta</span><span class="o">-</span><span class="nb">data to the</span>
<span class="nb">map files.</span>
<span class="nv">\medskip\item</span><span class="nb"></span>
<span class="nb">Special wires are used to instruct techmap how to handle a module in the map file.</span>
<span class="nv">\medskip\item</span><span class="nb"></span>
<span class="nb">Generate blocks and recursion are powerful tools for writing map files.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example </span><span class="m">1</span><span class="o">/</span><span class="m">2</span><span class="nb">}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span>
<span class="nb">To map the Verilog OR</span><span class="o">-</span><span class="nb">reduction operator to </span><span class="m">3</span><span class="o">-</span><span class="nb">input OR gates:</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">0</span><span class="nb">.</span><span class="m">35</span><span class="nv">\linewidth</span><span class="nb">}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, lastline</span><span class="o">=</span><span class="m">24</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">red_or</span><span class="m">3</span><span class="nb">x</span><span class="m">1</span><span class="nb">_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">0</span><span class="nb">.</span><span class="m">65</span><span class="nv">\linewidth</span><span class="nb">}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">25</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">red_or</span><span class="m">3</span><span class="nb">x</span><span class="m">1</span><span class="nb">_map.v}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example </span><span class="m">2</span><span class="o">/</span><span class="m">2</span><span class="nb">}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\hfil\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">10</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm </span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">red_or</span><span class="m">3</span><span class="nb">x</span><span class="m">1</span><span class="nb">.pdf}</span>
<span class="nv">\vss</span><span class="nb"></span>
<span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">4</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys, firstline</span><span class="o">=</span><span class="m">4</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">4</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">red_or</span><span class="m">3</span><span class="nb">x</span><span class="m">1</span><span class="nb">_test.ys}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">red_or</span><span class="m">3</span><span class="nb">x</span><span class="m">1</span><span class="nb">_test.v}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Conditional techmap}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> In some cases only cells with certain properties should be substituted.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> The special wire {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">FAIL</span><span class="nv">\_</span><span class="nb">} can be used to disable a module</span>
<span class="nb">in the map file for a certain set of parameters.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> The wire {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">FAIL</span><span class="nv">\_</span><span class="nb">} must be set to a constant value. If it</span>
<span class="nb">is non</span><span class="o">-</span><span class="nb">zero then the module is disabled for this set of parameters.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Example use</span><span class="o">-</span><span class="nb">cases:</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> coarse</span><span class="o">-</span><span class="nb">grain cell types that only operate on certain bit widths</span>
<span class="nv">\item</span><span class="nb"> memory resources for different memory geometries </span><span class="o">(</span><span class="nb">width, depth, ports, etc.</span><span class="o">)</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span>
<span class="nv">\hfill\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">6</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm </span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">sym_mul.pdf}</span>
<span class="nv">\vss</span><span class="nb"></span>
<span class="nb">}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">sym_mul_map.v}</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">sym_mul_test.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">4</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">ys, lastline</span><span class="o">=</span><span class="m">4</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">sym_mul_test.ys}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Scripting in map modules}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> The special wires {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">DO</span><span class="nv">\_</span><span class="o">*</span><span class="nb">} can be used to run Yosys scripts</span>
<span class="nb">in the context of the replacement module.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> The wire that comes first in alphabetical oder is interpreted as string </span><span class="o">(</span><span class="nb">must</span>
<span class="nb">be connected to constants</span><span class="o">)</span><span class="nb"> that is executed as script. Then the wire is removed. Repeat.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> You can even call techmap recursively</span><span class="o">!</span><span class="nb"></span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Example use</span><span class="o">-</span><span class="nb">cases:</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Using always blocks in map module: call {</span><span class="nv">\tt</span><span class="nb"> proc}</span>
<span class="nv">\item</span><span class="nb"> Perform expensive optimizations </span><span class="o">(</span><span class="nb">such as {</span><span class="nv">\tt</span><span class="nb"> freduce}</span><span class="o">)</span><span class="nb"> on cells where</span>
<span class="nb">this is known to work well.</span>
<span class="nv">\item</span><span class="nb"> Interacting with custom commands.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>

<span class="nv">\scriptsize</span><span class="nb"></span>
<span class="nb">PROTIP: Commands such as {</span><span class="nv">\tt</span><span class="nb"> shell}, {</span><span class="nv">\tt</span><span class="nb"> show </span><span class="o">-</span><span class="nb">pause}, and {</span><span class="nv">\tt</span><span class="nb"> dump} can be use</span>
<span class="nb">in the {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">DO</span><span class="nv">\_</span><span class="o">*</span><span class="nb">} scripts for debugging map modules.</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\vskip</span><span class="m">4</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\hskip</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">10</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm </span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mymul.pdf}</span>
<span class="nv">\vss</span><span class="nb"></span>
<span class="nb">}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mymul_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">4</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mymul_test.v}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">ys, lastline</span><span class="o">=</span><span class="m">5</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mymul_test.ys}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">ys, firstline</span><span class="o">=</span><span class="m">7</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">12</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mymul_test.ys}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Handling constant inputs}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> The special parameters {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">CONSTMSK</span><span class="nv">\_\it</span><span class="nb"> &lt;port</span><span class="o">-</span><span class="nb">name&gt;</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">} and</span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">CONSTVAL</span><span class="nv">\_\it</span><span class="nb"> &lt;port</span><span class="o">-</span><span class="nb">name&gt;</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">} can be used to handle constant</span>
<span class="nb">input values to cells.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> The former contains </span><span class="m">1</span><span class="o">-</span><span class="nb">bits for all constant input bits on the port.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> The latter contains the constant bits or undef </span><span class="o">(</span><span class="nb">x</span><span class="o">)</span><span class="nb"> for non</span><span class="o">-</span><span class="nb">constant bits.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Example use</span><span class="o">-</span><span class="nb">cases:</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Converting arithmetic </span><span class="o">(</span><span class="nb">for example multiply to shift</span><span class="o">)</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Identify constant addresses or enable bits in memory interfaces.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\vskip</span><span class="m">5</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\hskip</span><span class="m">6</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm </span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mulshift.pdf}</span>
<span class="nv">\vss</span><span class="nb"></span>
<span class="nb">}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">4</span><span class="nb">cm</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mulshift_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">4</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mulshift_test.v}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">ys, lastline</span><span class="o">=</span><span class="m">5</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mulshift_test.ys}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Handling shorted inputs}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> The special parameters {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">BITS</span><span class="nv">\_</span><span class="nb">CONNMAP</span><span class="nv">\_</span><span class="nb">} and</span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">CONNMAP</span><span class="nv">\_\it</span><span class="nb"> &lt;port</span><span class="o">-</span><span class="nb">name&gt;</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">} can be used to handle shorted inputs.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Each bit of the port correlates to an {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">BITS</span><span class="nv">\_</span><span class="nb">CONNMAP</span><span class="nv">\_</span><span class="nb">} bits wide</span>
<span class="nb">number in {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">CONNMAP</span><span class="nv">\_\it</span><span class="nb"> &lt;port</span><span class="o">-</span><span class="nb">name&gt;</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">}.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Each unique signal bit is assigned its own number. Identical fields in the {</span><span class="nv">\tt</span><span class="nb"></span>
<span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">CONNMAP</span><span class="nv">\_\it</span><span class="nb"> &lt;port</span><span class="o">-</span><span class="nb">name&gt;</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">} parameters mean shorted signal bits.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> The numbers </span><span class="m">0</span><span class="o">-</span><span class="m">3</span><span class="nb"> are reserved for {</span><span class="nv">\tt</span><span class="nb"> </span><span class="m">0</span><span class="nb">}, {</span><span class="nv">\tt</span><span class="nb"> </span><span class="m">1</span><span class="nb">}, {</span><span class="nv">\tt</span><span class="nb"> x}, and {</span><span class="nv">\tt</span><span class="nb"> z} respectively.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Example use</span><span class="o">-</span><span class="nb">cases:</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Detecting shared clock or control signals in memory interfaces.</span>
<span class="nv">\item</span><span class="nb"> In some cases this can be used for for optimization.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\vskip</span><span class="m">4</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span>
<span class="nv">\hskip</span><span class="m">6</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm </span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">addshift.pdf}</span>
<span class="nv">\vss</span><span class="nb"></span>
<span class="nb">}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">4</span><span class="nb">cm</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">addshift_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">4</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">addshift_test.v}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">ys, lastline</span><span class="o">=</span><span class="m">5</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">addshift_test.ys}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Notes on using techmap}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Don&#39;t use positional cell parameters in map modules.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Don&#39;t try to implement basic logic optimization with techmap. </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">{</span><span class="nv">\small</span><span class="nb"> </span><span class="o">(</span><span class="nb">So the OR</span><span class="o">-</span><span class="nb">reduce using OR</span><span class="m">3</span><span class="nb">X</span><span class="m">1</span><span class="nb"> cells map was actually a bad example.</span><span class="o">)</span><span class="nb">}</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> You can use the {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$\_\,\_</span><span class="nb">}</span><span class="o">-</span><span class="nb">prefix for internal cell types to avoid</span>
<span class="nb">collisions with the user</span><span class="o">-</span><span class="nb">namespace. But always use two underscores or the</span>
<span class="nb">internal consistency checker will trigger on this cells.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Techmap has two major use cases:</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Creating good logic</span><span class="o">-</span><span class="nb">level representation of arithmetic functions. </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">This also means using dedicated hardware resources such as half</span><span class="o">-</span><span class="nb"> and full</span><span class="o">-</span><span class="nb">adder</span>
<span class="nb">cells in ASICS or dedicated carry logic in FPGAs.</span>
<span class="nv">\smallskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Mapping of coarse</span><span class="o">-</span><span class="nb">grain resources such as block memory or DSP cells.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="nv">\subsection</span><span class="nb">{Coarse</span><span class="o">-</span><span class="nb">grain synthesis}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span>
<span class="nv">\subsectionpage</span><span class="nb"></span>
<span class="nv">\subsectionpagesuffix</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Intro to coarse</span><span class="o">-</span><span class="nb">grain synthesis}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nb">In coarse</span><span class="o">-</span><span class="nb">grain synthesis the target architecture has cells of the same</span>
<span class="nb">complexity or larger complexity than the internal RTL representation.</span>

<span class="nb">For example:</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb"></span>
<span class="nb">	wire </span><span class="o">[</span><span class="m">15</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> a, b;</span>
<span class="nb">	wire </span><span class="o">[</span><span class="m">31</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> c, y;</span>
<span class="nb">	assign y </span><span class="o">=</span><span class="nb"> a </span><span class="o">*</span><span class="nb"> b </span><span class="o">+</span><span class="nb"> c;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nb">This circuit contains two cells in the RTL representation: one multiplier and</span>
<span class="nb">one adder. In some architectures this circuit can be implemented using</span>
<span class="nb">a single circuit element, for example an FPGA DSP core. Coarse grain synthesis</span>
<span class="nb">is this mapping of groups of circuit elements to larger components.</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">Fine</span><span class="o">-</span><span class="nb">grain synthesis would be matching the circuit elements to smaller</span>
<span class="nb">components, such as LUTs, gates, or half</span><span class="o">-</span><span class="nb"> and full</span><span class="o">-</span><span class="nb">adders.</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{The extract pass}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Like the {</span><span class="nv">\tt</span><span class="nb"> techmap} pass, the {</span><span class="nv">\tt</span><span class="nb"> extract} pass is called with</span>
<span class="nb">a map file. It compares the circuits inside the modules of the map file</span>
<span class="nb">with the design and looks for sub</span><span class="o">-</span><span class="nb">circuits in the design that match any</span>
<span class="nb">of the modules in the map file.</span>
<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> If a match is found, the {</span><span class="nv">\tt</span><span class="nb"> extract} pass will replace the matching</span>
<span class="nb">subcircuit with an instance of the module from the map file.</span>
<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> In a way the {</span><span class="nv">\tt</span><span class="nb"> extract} pass is the inverse of the techmap pass.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example </span><span class="m">1</span><span class="o">/</span><span class="m">2</span><span class="nb">}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\vskip</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{tikzpicture}</span>
<span class="nb">    </span><span class="nv">\node</span><span class="nb"> at </span><span class="o">(</span><span class="m">0</span><span class="nb">,</span><span class="m">0</span><span class="o">)</span><span class="nb"> {</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">00</span><span class="nb">a.pdf}};</span>
<span class="nb">    </span><span class="nv">\node</span><span class="nb"> at </span><span class="o">(</span><span class="m">3</span><span class="nb">,</span><span class="o">-</span><span class="m">3</span><span class="o">)</span><span class="nb"> {</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">8</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">00</span><span class="nb">b.pdf}};</span>
<span class="nb">    </span><span class="nv">\draw</span><span class="o">[</span><span class="nb">yshift</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm,thick,</span><span class="o">-</span><span class="nb">latex</span><span class="o">]</span><span class="nb"> </span><span class="o">(</span><span class="m">1</span><span class="nb">,</span><span class="o">-</span><span class="m">1</span><span class="o">)</span><span class="nb"> </span><span class="o">--</span><span class="nb"> </span><span class="o">(</span><span class="m">2</span><span class="nb">,</span><span class="o">-</span><span class="m">2</span><span class="o">)</span><span class="nb">;</span>
<span class="nv">\end</span><span class="nb">{tikzpicture}</span>
<span class="nv">\vss</span><span class="nb">}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">1</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_xmap.v}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">read_verilog macc_simple_test.v</span>
<span class="nb">hierarchy </span><span class="o">-</span><span class="nb">check </span><span class="o">-</span><span class="nb">top test</span>

<span class="nb">extract </span><span class="o">-</span><span class="nb">map macc_simple_xmap.v;;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example </span><span class="m">2</span><span class="o">/</span><span class="m">2</span><span class="nb">}</span>
<span class="nv">\hfil\begin</span><span class="nb">{tabular}{cc}</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\hbox</span><span class="nb"> to </span><span class="m">5</span><span class="nb">cm {</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">01</span><span class="nb">.v}}} &amp;</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\hbox</span><span class="nb"> to </span><span class="m">5</span><span class="nb">cm {</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">02</span><span class="nb">.v}}} </span><span class="nv">\\</span><span class="nb"></span>
<span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> &amp; </span><span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">01</span><span class="nb">a.pdf}} &amp;</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">02</span><span class="nb">a.pdf}} </span><span class="nv">\\</span><span class="nb"></span>
<span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> &amp; </span><span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">01</span><span class="nb">b.pdf}} &amp;</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">02</span><span class="nb">b.pdf}} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{tabular}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{The wrap</span><span class="o">-</span><span class="nb">extract</span><span class="o">-</span><span class="nb">unwrap method}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\scriptsize</span><span class="nb"></span>
<span class="nb">Often a coarse</span><span class="o">-</span><span class="nb">grain element has a constant bit</span><span class="o">-</span><span class="nb">width, but can be used to</span>
<span class="nb">implement operations with a smaller bit</span><span class="o">-</span><span class="nb">width. For example, a </span><span class="m">18</span><span class="nb">x</span><span class="m">25</span><span class="o">-</span><span class="nb">bit multiplier</span>
<span class="nb">can also be used to implement </span><span class="m">16</span><span class="nb">x</span><span class="m">20</span><span class="o">-</span><span class="nb">bit multiplication.</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">A way of mapping such elements in coarse grain synthesis is the wrap</span><span class="o">-</span><span class="nb">extract</span><span class="o">-</span><span class="nb">unwrap method:</span>

<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> {</span><span class="nv">\bf</span><span class="nb"> wrap} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">Identify candidate</span><span class="o">-</span><span class="nb">cells in the circuit and wrap them in a cell with a constant</span>
<span class="nb">wider bit</span><span class="o">-</span><span class="nb">width using {</span><span class="nv">\tt</span><span class="nb"> techmap}. The wrappers use the same parameters as the original cell, so</span>
<span class="nb">the information about the original width of the ports is preserved. </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">Then use the {</span><span class="nv">\tt</span><span class="nb"> connwrappers} command to connect up the bit</span><span class="o">-</span><span class="nb">extended in</span><span class="o">-</span><span class="nb"> and</span>
<span class="nb">outputs of the wrapper cells.</span>
<span class="nv">\item</span><span class="nb"> {</span><span class="nv">\bf</span><span class="nb"> extract} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">Now all operations are encoded using the same bit</span><span class="o">-</span><span class="nb">width as the coarse grain element. The {</span><span class="nv">\tt</span><span class="nb"></span>
<span class="nb">extract} command can be used to replace circuits with cells of the target architecture.</span>
<span class="nv">\item</span><span class="nb"> {</span><span class="nv">\bf</span><span class="nb"> unwrap} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">The remaining wrapper cell can be unwrapped using {</span><span class="nv">\tt</span><span class="nb"> techmap}.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">The following sides detail an example that shows how to map MACC operations of</span>
<span class="nb">arbitrary size to MACC cells with a </span><span class="m">18</span><span class="nb">x</span><span class="m">25</span><span class="o">-</span><span class="nb">bit multiplier and a </span><span class="m">48</span><span class="o">-</span><span class="nb">bit adder </span><span class="o">(</span><span class="nb">such as</span>
<span class="nb">the Xilinx DSP</span><span class="m">48</span><span class="nb"> cells</span><span class="o">)</span><span class="nb">.</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Example: DSP</span><span class="m">48</span><span class="nv">\_</span><span class="nb">MACC}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">1</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Preconditioning: {</span><span class="nv">\tt</span><span class="nb"> macc</span><span class="nv">\_</span><span class="nb">xilinx</span><span class="nv">\_</span><span class="nb">swap</span><span class="nv">\_</span><span class="nb">map.v} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">Make sure {</span><span class="nv">\tt</span><span class="nb"> A} is the smaller port on all multipliers</span>

<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, lastline</span><span class="o">=</span><span class="m">15</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_swap_map.v}</span>
<span class="nv">\column</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">16</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_swap_map.v}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">2</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Wrapping multipliers: {</span><span class="nv">\tt</span><span class="nb"> macc</span><span class="nv">\_</span><span class="nb">xilinx</span><span class="nv">\_</span><span class="nb">wrap</span><span class="nv">\_</span><span class="nb">map.v}</span>

<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, lastline</span><span class="o">=</span><span class="m">23</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_wrap_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">24</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">46</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_wrap_map.v}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">3</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Wrapping adders: {</span><span class="nv">\tt</span><span class="nb"> macc</span><span class="nv">\_</span><span class="nb">xilinx</span><span class="nv">\_</span><span class="nb">wrap</span><span class="nv">\_</span><span class="nb">map.v}</span>

<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">48</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">67</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_wrap_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">68</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">89</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_wrap_map.v}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">4</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Extract: {</span><span class="nv">\tt</span><span class="nb"> macc</span><span class="nv">\_</span><span class="nb">xilinx</span><span class="nv">\_</span><span class="nb">xmap.v}</span>

<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">1</span><span class="nb">,  lastline</span><span class="o">=</span><span class="m">17</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_xmap.v}</span>

<span class="nb">.. simply use the same wrapping commands on this module as on the design to create a template for the {</span><span class="nv">\tt</span><span class="nb"> extract} command.</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">5</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Unwrapping multipliers: {</span><span class="nv">\tt</span><span class="nb"> macc</span><span class="nv">\_</span><span class="nb">xilinx</span><span class="nv">\_</span><span class="nb">unwrap</span><span class="nv">\_</span><span class="nb">map.v}</span>

<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">1</span><span class="nb">,  lastline</span><span class="o">=</span><span class="m">17</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_unwrap_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">18</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">30</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_unwrap_map.v}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">6</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Unwrapping adders: {</span><span class="nv">\tt</span><span class="nb"> macc</span><span class="nv">\_</span><span class="nb">xilinx</span><span class="nv">\_</span><span class="nb">unwrap</span><span class="nv">\_</span><span class="nb">map.v}</span>

<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">32</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">48</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_unwrap_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">49</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">61</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_unwrap_map.v}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">7</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nv">\hfil\begin</span><span class="nb">{tabular}{cc}</span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">1</span><span class="nb">} &amp; {</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">2</span><span class="nb">} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\hbox</span><span class="nb"> to </span><span class="m">5</span><span class="nb">cm {</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, firstline</span><span class="o">=</span><span class="m">1</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">6</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test.v}}} &amp;</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\hbox</span><span class="nb"> to </span><span class="m">5</span><span class="nb">cm {</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, firstline</span><span class="o">=</span><span class="m">8</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">13</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test.v}}} </span><span class="nv">\\</span><span class="nb"></span>
<span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> &amp; </span><span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{tabular}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">                            read_verilog macc_xilinx_test.v</span>
<span class="nb">                            hierarchy </span><span class="o">-</span><span class="nb">check</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span>
<span class="nv">\hfil\begin</span><span class="nb">{tabular}{cc}</span>
<span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> &amp; </span><span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">1</span><span class="nb">a.pdf}} &amp;</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">a.pdf}} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{tabular}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">8</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nv">\hfil\begin</span><span class="nb">{tabular}{cc}</span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">1</span><span class="nb">} &amp; {</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">2</span><span class="nb">} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">1</span><span class="nb">a.pdf}} &amp;</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">a.pdf}} </span><span class="nv">\\</span><span class="nb"></span>
<span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> &amp; </span><span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{tabular}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">                         techmap </span><span class="o">-</span><span class="nb">map macc_xilinx_swap_map.v ;;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\hfil\begin</span><span class="nb">{tabular}{cc}</span>
<span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> &amp; </span><span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">1</span><span class="nb">b.pdf}} &amp;</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">b.pdf}} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{tabular}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">9</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Wrapping in {</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">1</span><span class="nb">}:</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span><span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">4</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">1</span><span class="nb">b.pdf}}</span><span class="nv">\vss</span><span class="nb">}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">techmap </span><span class="o">-</span><span class="nb">map macc_xilinx_wrap_map.v</span>

<span class="nb">connwrappers </span><span class="o">-</span><span class="nb">unsigned </span><span class="s">$</span><span class="nb">__</span>mul<span class="nb">_</span>wrapper <span class="k">\</span>
                            Y Y<span class="nb">_</span>WIDTH <span class="k">\</span>
             -unsigned <span class="s">$</span><span class="nb">__add_wrapper </span><span class="err">\</span><span class="nb"></span>
<span class="nb">                            Y Y_WIDTH ;;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>

<span class="nv">\vskip</span><span class="m">1</span><span class="nb">cm</span>
<span class="nv">\hfil\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="nv">\linewidth</span><span class="nb">,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">1</span><span class="nb">c.pdf}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">10</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Wrapping in {</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">2</span><span class="nb">}:</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span><span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">4</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">b.pdf}}</span><span class="nv">\vss</span><span class="nb">}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">techmap </span><span class="o">-</span><span class="nb">map macc_xilinx_wrap_map.v</span>

<span class="nb">connwrappers </span><span class="o">-</span><span class="nb">unsigned </span><span class="s">$</span><span class="nb">__</span>mul<span class="nb">_</span>wrapper <span class="k">\</span>
                            Y Y<span class="nb">_</span>WIDTH <span class="k">\</span>
             -unsigned <span class="s">$</span><span class="nb">__add_wrapper </span><span class="err">\</span><span class="nb"></span>
<span class="nb">                            Y Y_WIDTH ;;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>

<span class="nv">\vskip</span><span class="m">1</span><span class="nb">cm</span>
<span class="nv">\hfil\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="nv">\linewidth</span><span class="nb">,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">c.pdf}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">11</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Extract in {</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">1</span><span class="nb">}:</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">4</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">design </span><span class="o">-</span><span class="nb">push</span>
<span class="nb">read_verilog macc_xilinx_xmap.v</span>
<span class="nb">techmap </span><span class="o">-</span><span class="nb">map macc_xilinx_swap_map.v</span>
<span class="nb">techmap </span><span class="o">-</span><span class="nb">map macc_xilinx_wrap_map.v;;</span>
<span class="nb">design </span><span class="o">-</span><span class="nb">save __macc_xilinx_xmap</span>
<span class="nb">design </span><span class="o">-</span><span class="nb">pop</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\vss</span><span class="nb">}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">1</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">extract </span><span class="o">-</span><span class="nb">constports </span><span class="o">-</span><span class="nb">ignore_parameters </span><span class="err">\</span><span class="nb"></span>
<span class="nb">        </span><span class="o">-</span><span class="nb">map </span><span class="c">%__macc_xilinx_xmap       \</span>
<span class="nb">        </span><span class="o">-</span><span class="nb">swap </span><span class="s">$</span><span class="nb">__</span>add<span class="nb">_</span>wrapper A,B ;;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\vbox</span> to 0cm<span class="nb">{</span><span class="k">\fbox</span><span class="nb">{</span><span class="k">\includegraphics</span><span class="na">[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExAdv/macc<span class="nb">_</span>xilinx<span class="nb">_</span>test1c.pdf<span class="nb">}}</span><span class="k">\vss</span><span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>columns<span class="nb">}</span>

<span class="k">\vskip</span>2cm
<span class="k">\hfil\includegraphics</span><span class="na">[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExAdv/macc<span class="nb">_</span>xilinx<span class="nb">_</span>test1d.pdf<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">{}</span> -- 12/13<span class="nb">}</span>
Extract in <span class="nb">{</span><span class="k">\tt</span> test2<span class="nb">}</span>:
<span class="k">\begin</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>4.5cm<span class="nb">}</span>
<span class="k">\vbox</span> to 0cm<span class="nb">{</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[linewidth=5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
design -push
read<span class="nb">_</span>verilog macc<span class="nb">_</span>xilinx<span class="nb">_</span>xmap.v
techmap -map macc<span class="nb">_</span>xilinx<span class="nb">_</span>swap<span class="nb">_</span>map.v
techmap -map macc<span class="nb">_</span>xilinx<span class="nb">_</span>wrap<span class="nb">_</span>map.v;;
design -save <span class="nb">__</span>macc<span class="nb">_</span>xilinx<span class="nb">_</span>xmap
design -pop
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\vss</span><span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5.5cm<span class="nb">}</span>
<span class="k">\vskip</span>-1cm
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[linewidth=5.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
extract -constports -ignore<span class="nb">_</span>parameters <span class="k">\</span>
        -map <span class="c">%__macc_xilinx_xmap       \</span>
        -swap <span class="s">$</span><span class="nb">__add_wrapper A,B ;;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span><span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">4</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">c.pdf}}</span><span class="nv">\vss</span><span class="nb">}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>

<span class="nv">\vskip</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\hfil\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">11</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">d.pdf}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">13</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Unwrap in {</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">2</span><span class="nb">}:</span>

<span class="nv">\hfil\begin</span><span class="nb">{tikzpicture}</span>
<span class="nv">\node</span><span class="nb"> at </span><span class="o">(</span><span class="m">0</span><span class="nb">,</span><span class="m">0</span><span class="o">)</span><span class="nb"> {</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">11</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">d.pdf}};</span>
<span class="nv">\node</span><span class="nb"> at </span><span class="o">(</span><span class="m">0</span><span class="nb">,</span><span class="o">-</span><span class="m">4</span><span class="o">)</span><span class="nb"> {</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">8</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">e.pdf}};</span>
<span class="nv">\node</span><span class="nb"> at </span><span class="o">(</span><span class="m">1</span><span class="nb">,</span><span class="o">-</span><span class="m">1</span><span class="nb">.</span><span class="m">7</span><span class="o">)</span><span class="nb"> {</span><span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, frame</span><span class="o">=</span><span class="nb">single, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">techmap </span><span class="o">-</span><span class="nb">map macc_xilinx_unwrap_map.v ;;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}};</span>
<span class="nv">\draw</span><span class="o">[-</span><span class="nb">latex</span><span class="o">]</span><span class="nb"> </span><span class="o">(</span><span class="m">4</span><span class="nb">,</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">7</span><span class="o">)</span><span class="nb"> .. controls </span><span class="o">(</span><span class="m">5</span><span class="nb">,</span><span class="o">-</span><span class="m">1</span><span class="nb">.</span><span class="m">7</span><span class="o">)</span><span class="nb"> .. </span><span class="o">(</span><span class="m">4</span><span class="nb">,</span><span class="o">-</span><span class="m">2</span><span class="nb">.</span><span class="m">7</span><span class="o">)</span><span class="nb">;</span>
<span class="nv">\end</span><span class="nb">{tikzpicture}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>


<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="nv">\subsection</span><span class="nb">{Automatic design changes}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span>
<span class="nv">\subsectionpage</span><span class="nb"></span>
<span class="nv">\subsectionpagesuffix</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Changing the design from Yosys}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nb">Yosys commands can be used to change the design in memory. Examples of this are:</span>

<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> {</span><span class="nv">\bf</span><span class="nb"> Changes in design hierarchy} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">Commands such as {</span><span class="nv">\tt</span><span class="nb"> flatten} and {</span><span class="nv">\tt</span><span class="nb"> submod} can be used to change the design hierarchy, i.e.</span>
<span class="nb">flatten the hierarchy or moving parts of a module to a submodule. This has applications in synthesis</span>
<span class="nb">scripts as well as in reverse engineering and analysis.</span>

<span class="nv">\item</span><span class="nb"> {</span><span class="nv">\bf</span><span class="nb"> Behavioral changes} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">Commands such as {</span><span class="nv">\tt</span><span class="nb"> techmap} can be used to make behavioral changes to the design, for example</span>
<span class="nb">changing asynchronous resets to synchronous resets. This has applications in design space exploration</span>
<span class="o">(</span><span class="nb">evaluation of various architectures for one circuit</span><span class="o">)</span><span class="nb">.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Example: Async reset to sync reset}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nb">The following techmap map file replaces all positive</span><span class="o">-</span><span class="nb">edge async reset flip</span><span class="o">-</span><span class="nb">flops with</span>
<span class="nb">positive</span><span class="o">-</span><span class="nb">edge sync reset flip</span><span class="o">-</span><span class="nb">flops. The code is taken from the example Yosys script</span>
<span class="nb">for ASIC synthesis of the Amber ARMv</span><span class="m">2</span><span class="nb"> CPU.</span>

<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb"></span>
<span class="o">(*</span><span class="nb"> techmap_celltype </span><span class="o">=</span><span class="nb"> &quot;</span><span class="s">$</span>adff&quot; *)
module adff2dff (CLK, ARST, D, Q);

    parameter WIDTH = 1;
    parameter CLK<span class="nb">_</span>POLARITY = 1;
    parameter ARST<span class="nb">_</span>POLARITY = 1;
    parameter ARST<span class="nb">_</span>VALUE = 0;

    input CLK, ARST;
    input [WIDTH-1:0] D;
    output reg [WIDTH-1:0] Q;

    wire [1023:0] <span class="nb">_</span>TECHMAP<span class="nb">_</span>DO<span class="nb">_</span> = &quot;proc&quot;;

    wire <span class="nb">_</span>TECHMAP<span class="nb">_</span>FAIL<span class="nb">_</span> = !CLK<span class="nb">_</span>POLARITY || !ARST<span class="nb">_</span>POLARITY;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\vss</span><span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>4cm<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=Verilog]
// ..continued..


    always @(posedge CLK)
        if (ARST)
            Q &lt;= ARST<span class="nb">_</span>VALUE;
        else
             &lt;= D;

endmodule
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>columns<span class="nb">}</span>

<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Summary<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> A lot can be achieved in Yosys just with the standard set of commands.
<span class="k">\item</span> The commands <span class="nb">{</span><span class="k">\tt</span> techmap<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> extract<span class="nb">}</span> can be used to prototype many complex synthesis tasks.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>center<span class="nb">}</span>
Questions?
<span class="k">\end</span><span class="nb">{</span>center<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\url</span><span class="nb">{</span>http://www.clifford.at/yosys/<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>
</pre></div>
</code></pre></td></tr></table>
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