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<div class='markdown-body'><p><a href="https://waffle.io/open-keychain/open-keychain"><img src="https://badge.waffle.io/open-keychain/open-keychain.png?label=ready&amp;title=Ready" alt="Stories in Ready" title="" /></a></p>

<h1>OpenKeychain (for Android)</h1>

<p>OpenKeychain is an OpenPGP implementation for Android. <br />
For a more detailed description and installation instructions go to https://www.openkeychain.org .</p>

<h3>Branches</h3>

<ul>
<li>The development of OpenKeychain happens in the "master" branch.</li>
<li>For every release a new branch, e.g., "3.2-fixes" is created to backport fixes from "master"</li>
</ul>

<h3>Travis CI Build Status of master branch</h3>

<p><a href="https://travis-ci.org/open-keychain/open-keychain"><img src="https://travis-ci.org/open-keychain/open-keychain.svg?branch=master" alt="Build Status" title="" /></a></p>

<h2>How to help the project?</h2>

<h3>Translate the application</h3>

<p>Translations are managed at Transifex, please contribute there at https://www.transifex.com/projects/p/open-keychain/</p>

<h3>Contribute Code</h3>

<ol>
<li>Lookout for interesting issues on Github. We have tagged issues were we explicitly like to see contributions: https://github.com/open-keychain/open-keychain/labels/help-wanted</li>
<li>Read this README, especially the notes about coding style</li>
<li>Fork OpenKeychain and contribute code (the best part :sunglasses: )</li>
<li>Open a pull request on Github. We will help with occuring problems and merge your changes back into the main project.</li>
<li>PROFIT</li>
</ol>

<h3>For bigger changes</h3>

<ol>
<li>Join the development mailinglist at https://lists.riseup.net/www/subscribe/openkeychain</li>
<li>Propose bigger changes and discuss the consequences</li>
</ol>

<p>I am happy about every code contribution and appreciate your effort to help us developing OpenKeychain!</p>

<h2>Development</h2>

<p>Development mailinglist at https://lists.riseup.net/www/subscribe/openkeychain</p>

<h3>Build with Gradle</h3>

<ol>
<li>Clone the project from GitHub</li>
<li>Get all external submodules with <code>git submodule update --init --recursive</code></li>
<li>Have Android SDK "tools", "platform-tools", and "build-tools" directories in your PATH (http://developer.android.com/sdk/index.html)</li>
<li>Open the Android SDK Manager (shell command: <code>android</code>).
Expand the Tools directory and select "Android SDK Build-tools (Version 23.0.1)".
Expand the Extras directory and install "Android Support Library", as well as "Local Maven repository for Support Libraries"
Select SDK Platform for API levels 21, 22, and 23.</li>
<li>Export ANDROID_HOME pointing to your Android SDK</li>
<li>Execute <code>./gradlew assembleFdroidDebug</code></li>
<li>You can install the app with <code>adb install -r OpenKeychain/build/outputs/apk/OpenKeychain-fdroid-debug.apk</code></li>
</ol>

<h3>Run Tests</h3>

<ol>
<li>Use OpenJDK instead of Oracle JDK</li>
<li>Execute <code>./gradlew clean testFdroidDebug --continue</code></li>
</ol>

<h3>Run Jacoco Test Coverage</h3>

<ol>
<li>Use OpenJDK instead of Oracle JDK</li>
<li>Execute <code>./gradlew clean testFdroidDebug jacocoTestReport</code></li>
<li>Report is here: OpenKeychain/build/reports/jacoco/jacocoTestReport/html/index.html</li>
</ol>

<h3>Development with Android Studio</h3>

<p>We are using the newest <a href="http://developer.android.com/sdk/installing/studio.html">Android Studio</a> for development. Development with Eclipse is currently not possible because we are using the new <a href="http://developer.android.com/sdk/installing/studio-tips.html">project structure</a>.</p>

<ol>
<li>Clone the project from Github</li>
<li>Get all external submodules with <code>git submodule update --init --recursive</code></li>
<li>From Android Studio: File -> Import Project ->  Select the cloned top folder</li>
</ol>

<h2>Libraries</h2>

<h3>Bouncy Castle</h3>

<p>OpenKeychain uses a forked version with some small changes. These changes will been sent to Bouncy Castle.</p>

<p>see
* Fork: https://github.com/open-keychain/bouncycastle</p>

<h4>Bouncy Castle resources</h4>

<ul>
<li>Repository: https://github.com/bcgit/bc-java</li>
<li>Issue tracker: http://www.bouncycastle.org/jira/browse/BJA</li>
</ul>

<h4>Documentation</h4>

<ul>
<li>Documentation project at http://www.cryptoworkshop.com/guide/</li>
<li>Tests in https://github.com/bcgit/bc-java/tree/master/pg/src/test/java/org/bouncycastle/openpgp/test</li>
<li>Examples in https://github.com/bcgit/bc-java/tree/master/pg/src/main/java/org/bouncycastle/openpgp/examples</li>
<li>Mailinglist Archive at http://bouncy-castle.1462172.n4.nabble.com/Bouncy-Castle-Dev-f1462173.html</li>
<li>Commit changelog of pg subpackage: https://github.com/bcgit/bc-java/commits/master/pg</li>
</ul>

<h2>Build System</h2>

<p>We try to make our builds as <a href="https://blog.torproject.org/blog/deterministic-builds-part-one-cyberwar-and-global-compromise">reproducible/deterministic</a> as possible.  </p>

<h4>Update Gradle version</h4>

<ul>
<li>Always use a fixed Android Gradle plugin version not a dynamic one, e.g. <code>0.7.3</code> instead of <code>0.7.+</code> (allows offline builds without lookups for new versions, also some minor Android plugin versions had serious issues, i.e. <a href="http://tools.android.com/tech-docs/new-build-system">0.7.2 and 0.8.1</a>)</li>
<li>Update every build.gradle file with the new gradle version and/or gradle plugin version
<ul>
<li>build.gradle</li>
<li>OpenKeychain/build.gradle</li>
</ul></li>
<li>run ./gradlew wrapper twice to update gradle and download the new gradle jar file</li>
<li>commit the corresponding <a href="http://www.gradle.org/docs/current/userguide/gradle_wrapper.html">Gradle wrapper</a> to the repository (allows easy building for new contributors without the need to install the required Gradle version using a package manager)</li>
</ul>

<h4>Update SDK and Build Tools</h4>

<ul>
<li>Open build.gradle and change:
<code>
ext {
compileSdkVersion = 21
buildToolsVersion = '21.1.2'
}
</code></li>
<li>Change SDK and Build Tools in git submodules "openkeychain-api-lib" and "openpgp-api-lib" manually. They should also build on their own without the ext variables.</li>
</ul>

<h4>Update library</h4>

<ul>
<li>You can check for library updates with ``./gradlew dependencyUpdates -Drevision=release</li>
</ul>

<h4>Add new library</h4>

<ul>
<li>You can add the library as a Maven dependency or as a git submodule (if patches are required) in the "extern" folder.</li>
<li>You can get all transitive dependencies with <code>./gradlew -q dependencies OpenKeychain:dependencies</code></li>
<li>If added as a Maven dependency, pin the library using <a href="https://github.com/WhisperSystems/gradle-witness">Gradle Witness</a> (Do <code>./gradlew -q calculateChecksums</code> for Trust on First Use)</li>
<li>If added as a git submodule, change the <code>compileSdkVersion</code> and <code>buildToolsVersion</code> in build.gradle to use the variables from the root project:
<code>
android {
compileSdkVersion rootProject.ext.compileSdkVersion
buildToolsVersion rootProject.ext.buildToolsVersion
}
</code></li>
<li>You can check for wrong <code>compileSdkVersion</code> by <code>find -name build.gradle | xargs grep compileSdkVersion</code></li>
</ul>

<h4>Slow Gradle?</h4>

<ul>
<li>https://www.timroes.de/2013/09/12/speed-up-gradle/</li>
<li>Disable Lint checking if it is enabled in build.gradle</li>
</ul>

<h4>Error:Configuration with name 'default' not found.</h4>

<p>Gradle project dependencies are missing. Do a <code>git submodule init &amp;&amp; git submodule update</code></p>

<h4>Build on Mac OS X fails?</h4>

<p>Try exporting JAVA<em>TOOL</em>OPTIONS="-Dfile.encoding=UTF8"</p>

<h2>Translations</h2>

<p>Translations are hosted on Transifex, which is configured by ".tx/config".</p>

<ol>
<li>To pull newest translations install transifex client (e.g. <code>apt-get install transifex-client</code>)</li>
<li>Config Transifex client with "~/.transifexrc"</li>
<li>Go into root folder of git repo</li>
<li>execute <code>tx pull -af --skip</code></li>
</ol>

<p>see http://help.transifex.net/features/client/index.html#user-client</p>

<h2>Coding Style</h2>

<h3>Code</h3>

<ul>
<li>Indentation: 4 spaces, no tabs.</li>
<li>Maximum line width for code and comments: 100.</li>
<li>Opening braces don't go on their own line.</li>
<li>Field names: Non-public, non-static fields start with m.</li>
<li>Acronyms are words: Treat acronyms as words in names, yielding !XmlHttpRequest, getUrl(), etc.</li>
<li>Fully Qualify Imports: Do <em>not</em> use wildcard-imports such as <code>import foo.*;</code></li>
<li>Android Studio warnings should be fixed, or suppressed if they are incorrect.</li>
</ul>

<p>The full coding style can be found at http://source.android.com/source/code-style.html</p>

<h3>Automated syntax check with CheckStyle</h3>

<h4>Linux</h4>

<ol>
<li>Paste the <code>tools/checkstyle.xml</code> file to <code>~/.AndroidStudioPreview/config/codestyles/</code></li>
<li>Go to Settings > Code Style > Java, select OpenPgpChecker, as well as Code Style > XML and select OpenPgpChecker again.</li>
<li>Start code inspection and see the results by selecting Analyze > Inspect Code from Android-Studio or you can directly run checkstyle via cli with <code>.tools/checkstyle</code>. Make sure it's executable first.</li>
</ol>

<h4>Mac OSX</h4>

<ol>
<li>Paste the <code>tools/checkstyle.xml</code> file to <code>~/Library/Preferences/AndroidStudioPreview/codestyles</code></li>
<li>Go to Preferences > Code Style > Java, select OpenPgpChecker, as well as Code Style > XML and select OpenPgpChecker again.</li>
<li>Start code inspection and see the results by selecting Analyze > Inspect Code from Android-Studio or you can directly run checkstyle via cli with <code>.tools/checkstyle</code>. Make sure it's executable first.</li>
</ol>

<h4>Windows</h4>

<ol>
<li>Paste the <code>tools/checkstyle.xml</code> file to <code>C:\Users\&lt;UserName&gt;\.AndroidStudioPreview\config\codestyles</code></li>
<li>Go to File > Settings > Code Style > Java, select OpenPgpChecker, as well as Code Style > XML and select OpenPgpChecker again.</li>
<li>Start code inspection and see the results by selecting Analyze > Inspect Code from Android-Studio.</li>
</ol>

<h2>Licenses</h2>

<p>OpenKechain is licensed under GPLv3+.
The full license text can be found in the <a href="https://github.com/open-keychain/open-keychain/blob/HEAD/LICENSE">LICENSE file</a>.
Some parts and some libraries are Apache License v2, MIT X11 License (see below).</p>

<blockquote>
  <p>This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.</p>

<p>This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.</p>

<p>You should have received a copy of the GNU General Public License
along with this program.  If not, see <a href="http://www.gnu.org/licenses/">http://www.gnu.org/licenses/</a>.</p>
</blockquote>

<h3>Libraries</h3>

<p>See <a href="https://github.com/open-keychain/open-keychain/blob/HEAD/OpenKeychain/src/main/res/raw/help_about.md">In-app about screen</a></p>

<h3>Images</h3>

<ul>
<li><p>Actionbar icons <br />
http://developer.android.com/design/downloads/index.html#action-bar-icon-pack</p></li>
<li><p>QR Code Actionbar icon <br />
https://github.com/openintents/openintents/blob/master/extensions/qrcode<em>ext/icons/ic</em>menu<em>qr</em>code/ic<em>menu</em>qr<em>code</em>holo<em>light/ic</em>menu<em>qr</em>code.svg</p></li>
<li><p>Key status icons by the ModernPGP working group <br />
https://github.com/ModernPGP</p></li>
</ul>
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<a id='n862' href='#n862'>862</a>
<a id='n863' href='#n863'>863</a>
<a id='n864' href='#n864'>864</a>
<a id='n865' href='#n865'>865</a>
<a id='n866' href='#n866'>866</a>
<a id='n867' href='#n867'>867</a>
<a id='n868' href='#n868'>868</a>
<a id='n869' href='#n869'>869</a>
<a id='n870' href='#n870'>870</a>
<a id='n871' href='#n871'>871</a>
<a id='n872' href='#n872'>872</a>
<a id='n873' href='#n873'>873</a>
<a id='n874' href='#n874'>874</a>
<a id='n875' href='#n875'>875</a>
<a id='n876' href='#n876'>876</a>
<a id='n877' href='#n877'>877</a>
<a id='n878' href='#n878'>878</a>
<a id='n879' href='#n879'>879</a>
<a id='n880' href='#n880'>880</a>
<a id='n881' href='#n881'>881</a>
<a id='n882' href='#n882'>882</a>
<a id='n883' href='#n883'>883</a>
<a id='n884' href='#n884'>884</a>
<a id='n885' href='#n885'>885</a>
<a id='n886' href='#n886'>886</a>
<a id='n887' href='#n887'>887</a>
<a id='n888' href='#n888'>888</a>
<a id='n889' href='#n889'>889</a>
<a id='n890' href='#n890'>890</a>
<a id='n891' href='#n891'>891</a>
<a id='n892' href='#n892'>892</a>
<a id='n893' href='#n893'>893</a>
<a id='n894' href='#n894'>894</a>
<a id='n895' href='#n895'>895</a>
<a id='n896' href='#n896'>896</a>
</pre></td>
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.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */</style><div class="highlight"><pre><span></span><span class="k">\section</span><span class="nb">{</span>Yosys by example -- Advanced Synthesis<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>
<span class="k">\sectionpage</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span>Overview<span class="nb">}</span>
This section contains 4 subsections:
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Using selections
<span class="k">\item</span> Advanced uses of techmap
<span class="k">\item</span> Coarse-grain synthesis
<span class="k">\item</span> Automatic design changes
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Using selections<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>
<span class="k">\subsectionpage</span>
<span class="k">\subsectionpagesuffix</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>Simple selections<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
Most Yosys commands make use of the ``selection framework&#39;&#39; of Yosys. It can be used
to apply commands only to part of the design. For example:

<span class="k">\medskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
delete                # will delete the whole design, but

delete foobar         # will only delete the module foobar.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
The <span class="nb">{</span><span class="k">\tt</span> select<span class="nb">}</span> command can be used to create a selection for subsequent
commands. For example:

<span class="k">\medskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
select foobar         # select the module foobar
delete                # delete selected objects
select -clear         # reset selection (select whole design)
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>Selection by object name<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
The easiest way to select objects is by object name. This is usually only done
in synthesis scripts that are hand-tailored for a specific design.

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
select foobar         # select module foobar
select foo*           # select all modules whose names start with foo
select foo*/bar*      # select all objects matching bar* from modules matching foo*
select */clk          # select objects named clk from all modules
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>Module and design context<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
Commands can be executed in <span class="nb">{</span><span class="k">\it</span> module<span class="k">\/</span><span class="nb">}</span> or <span class="nb">{</span><span class="k">\it</span> design<span class="k">\/</span><span class="nb">}</span> context. Until now all
commands have been executed in design context. The <span class="nb">{</span><span class="k">\tt</span> cd<span class="nb">}</span> command can be used
to switch to module context.

<span class="k">\bigskip</span>
In module context all commands only effect the active module. Objects in the module
are selected without the <span class="nb">{</span><span class="k">\tt</span> &lt;module<span class="k">\_</span>name&gt;/<span class="nb">}</span> prefix. For example:

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
cd foo                # switch to module foo
delete bar            # delete object foo/bar

cd mycpu              # switch to module mycpu
dump reg<span class="nb">_</span>*            # print details on all objects whose names start with reg<span class="nb">_</span>

cd ..                 # switch back to design
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
Note: Most synthesis scripts never switch to module context. But it is a very powerful
tool for interactive design investigation.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>Selecting by object property or type<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
Special patterns can be used to select by object property or type. For example:

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
select w:reg<span class="nb">_</span>*        # select all wires whose names start with reg<span class="nb">_</span>
select a:foobar       # select all objects with the attribute foobar set
select a:foobar=42    # select all objects with the attribute foobar set to 42
select A:blabla       # select all modules with the attribute blabla set
select foo/t:<span class="s">$</span><span class="nb">add     # select all </span><span class="s">$</span>add cells from the module foo
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
A complete list of this pattern expressions can be found in the command
reference to the <span class="nb">{</span><span class="k">\tt</span> select<span class="nb">}</span> command.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>Combining selection<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
When more than one selection expression is used in one statement, then they are
pushed on a stack. The final elements on the stack are combined into a union:

<span class="k">\medskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
select t:<span class="s">$</span><span class="nb">dff r:WIDTH&gt;</span><span class="m">1</span><span class="nb">     # all cells of type </span><span class="s">$</span>dff and/or with a parameter WIDTH &gt; 1
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
Special <span class="k">\%</span>-commands can be used to combine the elements on the stack:

<span class="k">\medskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
select t:<span class="s">$</span><span class="nb">dff r:WIDTH&gt;</span><span class="m">1</span><span class="nb"> </span><span class="c">%i  # all cells of type $dff *AND* with a parameter WIDTH &gt; 1</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{block}{Examples for {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">}</span><span class="o">-</span><span class="nb">codes </span><span class="o">(</span><span class="nb">see {</span><span class="nv">\tt</span><span class="nb"> help select} for full list</span><span class="o">)</span><span class="nb">}</span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">u} </span><span class="nv">\dotfill</span><span class="nb"> union of top two elements on stack </span><span class="o">--</span><span class="nb"> pop </span><span class="m">2</span><span class="nb">, push </span><span class="m">1</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">d} </span><span class="nv">\dotfill</span><span class="nb"> difference of top two elements on stack </span><span class="o">--</span><span class="nb"> pop </span><span class="m">2</span><span class="nb">, push </span><span class="m">1</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">i} </span><span class="nv">\dotfill</span><span class="nb"> intersection of top two elements on stack </span><span class="o">--</span><span class="nb"> pop </span><span class="m">2</span><span class="nb">, push </span><span class="m">1</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">n} </span><span class="nv">\dotfill</span><span class="nb"> inverse of top element on stack </span><span class="o">--</span><span class="nb"> pop </span><span class="m">1</span><span class="nb">, push </span><span class="m">1</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{block}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Expanding selections}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nb">Selections of cells and wires can be expanded along connections using {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">}</span><span class="o">-</span><span class="nb">codes</span>
<span class="nb">for selecting input cones </span><span class="o">(</span><span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">ci}</span><span class="o">)</span><span class="nb">, output cones </span><span class="o">(</span><span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">co}</span><span class="o">)</span><span class="nb">, or both </span><span class="o">(</span><span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">x}</span><span class="o">)</span><span class="nb">.</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb"># select all wires that are inputs to </span><span class="s">$</span>add cells
select t:<span class="s">$</span><span class="nb">add </span><span class="c">%ci w:* %i</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">Additional constraints such as port names can be specified.</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb"># select all wires that connect a &quot;Q&quot; output with a &quot;D&quot; input</span>
<span class="nb">select c:</span><span class="o">*</span><span class="nb"> </span><span class="c">%co:+[Q] w:* %i c:* %ci:+[D] w:* %i %i</span>

<span class="nb"># select the multiplexer tree that drives the signal &#39;state&#39;</span>
<span class="nb">select state </span><span class="c">%ci*:+$mux,$pmux[A,B,Y]</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">See {</span><span class="nv">\tt</span><span class="nb"> help select} for full documentation of this expressions.</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Incremental selection}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nb">Sometimes a selection can most easily be described by a series of add</span><span class="o">/</span><span class="nb">delete operations.</span>
<span class="nb">The commands {</span><span class="nv">\tt</span><span class="nb"> select </span><span class="o">-</span><span class="nb">add} and {</span><span class="nv">\tt</span><span class="nb"> select </span><span class="o">-</span><span class="nb">del} respectively add or remove objects</span>
<span class="nb">from the current selection instead of overwriting it.</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">select </span><span class="o">-</span><span class="nb">none            # start with an empty selection</span>
<span class="nb">select </span><span class="o">-</span><span class="nb">add reg_</span><span class="o">*</span><span class="nb">       # select a bunch of objects</span>
<span class="nb">select </span><span class="o">-</span><span class="nb">del reg_</span><span class="m">42</span><span class="nb">      # but not this one</span>
<span class="nb">select </span><span class="o">-</span><span class="nb">add state </span><span class="c">%ci   # and add mor stuff</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">Within a select expression the token {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">} can be used to push the previous selection</span>
<span class="nb">on the stack.</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">select t:</span><span class="s">$</span>add t:<span class="s">$</span><span class="nb">sub    # select all </span><span class="s">$</span>add and <span class="s">$</span><span class="nb">sub cells</span>
<span class="nb">select </span><span class="c">% %ci % %d       # select only the input wires to those cells</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Creating selection variables}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nb">Selections can be stored under a name with the {</span><span class="nv">\tt</span><span class="nb"> select </span><span class="o">-</span><span class="nb">set &lt;name&gt;}</span>
<span class="nb">command. The stored selections can be used in later select expressions</span>
<span class="nb">using the syntax {</span><span class="nv">\tt</span><span class="nb"> @&lt;name&gt;}.</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">select </span><span class="o">-</span><span class="nb">set cone_a state_a </span><span class="c">%ci*:-$dff  # set @cone_a to the input cone of state_a</span>
<span class="nb">select </span><span class="o">-</span><span class="nb">set cone_b state_b </span><span class="c">%ci*:-$dff  # set @cone_b to the input cone of state_b</span>
<span class="nb">select @cone_a @cone_b </span><span class="c">%i              # select the objects that are in both cones</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">Remember that select expressions can also be used directly as arguments to most</span>
<span class="nb">commands. Some commands also except a single select argument to some options.</span>
<span class="nb">In those cases selection variables must be used to capture more complex selections.</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">dump @cone_a @cone_b</span>

<span class="nb">select </span><span class="o">-</span><span class="nb">set cone_ab @cone_a @cone_b </span><span class="c">%i</span>
<span class="nb">show </span><span class="o">-</span><span class="nb">color red @cone_ab </span><span class="o">-</span><span class="nb">color magenta @cone_a </span><span class="o">-</span><span class="nb">color blue @cone_b</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example}</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">4</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">6</span><span class="nb">pt}{</span><span class="m">7</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">select.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">7</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys, frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">select.ys}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\hfil\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="nv">\linewidth</span><span class="nb">,trim</span><span class="o">=</span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm </span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">select.pdf}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="nv">\subsection</span><span class="nb">{Advanced uses of techmap}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span>
<span class="nv">\subsectionpage</span><span class="nb"></span>
<span class="nv">\subsectionpagesuffix</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Introduction to techmap}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"></span>
<span class="nb">The {</span><span class="nv">\tt</span><span class="nb"> techmap} command replaces cells in the design with implementations given</span>
<span class="nb">as Verilog code </span><span class="o">(</span><span class="nb">called ``map files&#39;&#39;</span><span class="o">)</span><span class="nb">. It can replace Yosys&#39; internal cell</span>
<span class="nb">types </span><span class="o">(</span><span class="nb">such as {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$</span><span class="nb">or}</span><span class="o">)</span><span class="nb"> as well as user</span><span class="o">-</span><span class="nb">defined cell types.</span>
<span class="nv">\medskip\item</span><span class="nb"></span>
<span class="nb">Verilog parameters are used extensively to customize the internal cell types.</span>
<span class="nv">\medskip\item</span><span class="nb"></span>
<span class="nb">Additional special parameters are used by techmap to communicate meta</span><span class="o">-</span><span class="nb">data to the</span>
<span class="nb">map files.</span>
<span class="nv">\medskip\item</span><span class="nb"></span>
<span class="nb">Special wires are used to instruct techmap how to handle a module in the map file.</span>
<span class="nv">\medskip\item</span><span class="nb"></span>
<span class="nb">Generate blocks and recursion are powerful tools for writing map files.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example </span><span class="m">1</span><span class="o">/</span><span class="m">2</span><span class="nb">}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span>
<span class="nb">To map the Verilog OR</span><span class="o">-</span><span class="nb">reduction operator to </span><span class="m">3</span><span class="o">-</span><span class="nb">input OR gates:</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">0</span><span class="nb">.</span><span class="m">35</span><span class="nv">\linewidth</span><span class="nb">}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, lastline</span><span class="o">=</span><span class="m">24</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">red_or</span><span class="m">3</span><span class="nb">x</span><span class="m">1</span><span class="nb">_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">0</span><span class="nb">.</span><span class="m">65</span><span class="nv">\linewidth</span><span class="nb">}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">25</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">red_or</span><span class="m">3</span><span class="nb">x</span><span class="m">1</span><span class="nb">_map.v}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example </span><span class="m">2</span><span class="o">/</span><span class="m">2</span><span class="nb">}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\hfil\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">10</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm </span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">red_or</span><span class="m">3</span><span class="nb">x</span><span class="m">1</span><span class="nb">.pdf}</span>
<span class="nv">\vss</span><span class="nb"></span>
<span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">4</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys, firstline</span><span class="o">=</span><span class="m">4</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">4</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">red_or</span><span class="m">3</span><span class="nb">x</span><span class="m">1</span><span class="nb">_test.ys}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">red_or</span><span class="m">3</span><span class="nb">x</span><span class="m">1</span><span class="nb">_test.v}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Conditional techmap}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> In some cases only cells with certain properties should be substituted.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> The special wire {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">FAIL</span><span class="nv">\_</span><span class="nb">} can be used to disable a module</span>
<span class="nb">in the map file for a certain set of parameters.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> The wire {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">FAIL</span><span class="nv">\_</span><span class="nb">} must be set to a constant value. If it</span>
<span class="nb">is non</span><span class="o">-</span><span class="nb">zero then the module is disabled for this set of parameters.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Example use</span><span class="o">-</span><span class="nb">cases:</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> coarse</span><span class="o">-</span><span class="nb">grain cell types that only operate on certain bit widths</span>
<span class="nv">\item</span><span class="nb"> memory resources for different memory geometries </span><span class="o">(</span><span class="nb">width, depth, ports, etc.</span><span class="o">)</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span>
<span class="nv">\hfill\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">6</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm </span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">sym_mul.pdf}</span>
<span class="nv">\vss</span><span class="nb"></span>
<span class="nb">}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">sym_mul_map.v}</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">sym_mul_test.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">4</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">ys, lastline</span><span class="o">=</span><span class="m">4</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">sym_mul_test.ys}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Scripting in map modules}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> The special wires {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">DO</span><span class="nv">\_</span><span class="o">*</span><span class="nb">} can be used to run Yosys scripts</span>
<span class="nb">in the context of the replacement module.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> The wire that comes first in alphabetical oder is interpreted as string </span><span class="o">(</span><span class="nb">must</span>
<span class="nb">be connected to constants</span><span class="o">)</span><span class="nb"> that is executed as script. Then the wire is removed. Repeat.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> You can even call techmap recursively</span><span class="o">!</span><span class="nb"></span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Example use</span><span class="o">-</span><span class="nb">cases:</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Using always blocks in map module: call {</span><span class="nv">\tt</span><span class="nb"> proc}</span>
<span class="nv">\item</span><span class="nb"> Perform expensive optimizations </span><span class="o">(</span><span class="nb">such as {</span><span class="nv">\tt</span><span class="nb"> freduce}</span><span class="o">)</span><span class="nb"> on cells where</span>
<span class="nb">this is known to work well.</span>
<span class="nv">\item</span><span class="nb"> Interacting with custom commands.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>

<span class="nv">\scriptsize</span><span class="nb"></span>
<span class="nb">PROTIP: Commands such as {</span><span class="nv">\tt</span><span class="nb"> shell}, {</span><span class="nv">\tt</span><span class="nb"> show </span><span class="o">-</span><span class="nb">pause}, and {</span><span class="nv">\tt</span><span class="nb"> dump} can be use</span>
<span class="nb">in the {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">DO</span><span class="nv">\_</span><span class="o">*</span><span class="nb">} scripts for debugging map modules.</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\vskip</span><span class="m">4</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\hskip</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">10</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm </span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mymul.pdf}</span>
<span class="nv">\vss</span><span class="nb"></span>
<span class="nb">}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mymul_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">4</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mymul_test.v}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">ys, lastline</span><span class="o">=</span><span class="m">5</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mymul_test.ys}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">ys, firstline</span><span class="o">=</span><span class="m">7</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">12</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mymul_test.ys}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Handling constant inputs}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> The special parameters {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">CONSTMSK</span><span class="nv">\_\it</span><span class="nb"> &lt;port</span><span class="o">-</span><span class="nb">name&gt;</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">} and</span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">CONSTVAL</span><span class="nv">\_\it</span><span class="nb"> &lt;port</span><span class="o">-</span><span class="nb">name&gt;</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">} can be used to handle constant</span>
<span class="nb">input values to cells.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> The former contains </span><span class="m">1</span><span class="o">-</span><span class="nb">bits for all constant input bits on the port.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> The latter contains the constant bits or undef </span><span class="o">(</span><span class="nb">x</span><span class="o">)</span><span class="nb"> for non</span><span class="o">-</span><span class="nb">constant bits.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Example use</span><span class="o">-</span><span class="nb">cases:</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Converting arithmetic </span><span class="o">(</span><span class="nb">for example multiply to shift</span><span class="o">)</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Identify constant addresses or enable bits in memory interfaces.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\vskip</span><span class="m">5</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\hskip</span><span class="m">6</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm </span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mulshift.pdf}</span>
<span class="nv">\vss</span><span class="nb"></span>
<span class="nb">}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">4</span><span class="nb">cm</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mulshift_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">4</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mulshift_test.v}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">ys, lastline</span><span class="o">=</span><span class="m">5</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mulshift_test.ys}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Handling shorted inputs}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> The special parameters {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">BITS</span><span class="nv">\_</span><span class="nb">CONNMAP</span><span class="nv">\_</span><span class="nb">} and</span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">CONNMAP</span><span class="nv">\_\it</span><span class="nb"> &lt;port</span><span class="o">-</span><span class="nb">name&gt;</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">} can be used to handle shorted inputs.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Each bit of the port correlates to an {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">BITS</span><span class="nv">\_</span><span class="nb">CONNMAP</span><span class="nv">\_</span><span class="nb">} bits wide</span>
<span class="nb">number in {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">CONNMAP</span><span class="nv">\_\it</span><span class="nb"> &lt;port</span><span class="o">-</span><span class="nb">name&gt;</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">}.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Each unique signal bit is assigned its own number. Identical fields in the {</span><span class="nv">\tt</span><span class="nb"></span>
<span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">CONNMAP</span><span class="nv">\_\it</span><span class="nb"> &lt;port</span><span class="o">-</span><span class="nb">name&gt;</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">} parameters mean shorted signal bits.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> The numbers </span><span class="m">0</span><span class="o">-</span><span class="m">3</span><span class="nb"> are reserved for {</span><span class="nv">\tt</span><span class="nb"> </span><span class="m">0</span><span class="nb">}, {</span><span class="nv">\tt</span><span class="nb"> </span><span class="m">1</span><span class="nb">}, {</span><span class="nv">\tt</span><span class="nb"> x}, and {</span><span class="nv">\tt</span><span class="nb"> z} respectively.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Example use</span><span class="o">-</span><span class="nb">cases:</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Detecting shared clock or control signals in memory interfaces.</span>
<span class="nv">\item</span><span class="nb"> In some cases this can be used for for optimization.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\vskip</span><span class="m">4</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span>
<span class="nv">\hskip</span><span class="m">6</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm </span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">addshift.pdf}</span>
<span class="nv">\vss</span><span class="nb"></span>
<span class="nb">}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">4</span><span class="nb">cm</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">addshift_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">4</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">addshift_test.v}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">ys, lastline</span><span class="o">=</span><span class="m">5</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">addshift_test.ys}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Notes on using techmap}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Don&#39;t use positional cell parameters in map modules.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Don&#39;t try to implement basic logic optimization with techmap. </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">{</span><span class="nv">\small</span><span class="nb"> </span><span class="o">(</span><span class="nb">So the OR</span><span class="o">-</span><span class="nb">reduce using OR</span><span class="m">3</span><span class="nb">X</span><span class="m">1</span><span class="nb"> cells map was actually a bad example.</span><span class="o">)</span><span class="nb">}</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> You can use the {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$\_\,\_</span><span class="nb">}</span><span class="o">-</span><span class="nb">prefix for internal cell types to avoid</span>
<span class="nb">collisions with the user</span><span class="o">-</span><span class="nb">namespace. But always use two underscores or the</span>
<span class="nb">internal consistency checker will trigger on this cells.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Techmap has two major use cases:</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Creating good logic</span><span class="o">-</span><span class="nb">level representation of arithmetic functions. </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">This also means using dedicated hardware resources such as half</span><span class="o">-</span><span class="nb"> and full</span><span class="o">-</span><span class="nb">adder</span>
<span class="nb">cells in ASICS or dedicated carry logic in FPGAs.</span>
<span class="nv">\smallskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Mapping of coarse</span><span class="o">-</span><span class="nb">grain resources such as block memory or DSP cells.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="nv">\subsection</span><span class="nb">{Coarse</span><span class="o">-</span><span class="nb">grain synthesis}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span>
<span class="nv">\subsectionpage</span><span class="nb"></span>
<span class="nv">\subsectionpagesuffix</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Intro to coarse</span><span class="o">-</span><span class="nb">grain synthesis}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nb">In coarse</span><span class="o">-</span><span class="nb">grain synthesis the target architecture has cells of the same</span>
<span class="nb">complexity or larger complexity than the internal RTL representation.</span>

<span class="nb">For example:</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb"></span>
<span class="nb">	wire </span><span class="o">[</span><span class="m">15</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> a, b;</span>
<span class="nb">	wire </span><span class="o">[</span><span class="m">31</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> c, y;</span>
<span class="nb">	assign y </span><span class="o">=</span><span class="nb"> a </span><span class="o">*</span><span class="nb"> b </span><span class="o">+</span><span class="nb"> c;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nb">This circuit contains two cells in the RTL representation: one multiplier and</span>
<span class="nb">one adder. In some architectures this circuit can be implemented using</span>
<span class="nb">a single circuit element, for example an FPGA DSP core. Coarse grain synthesis</span>
<span class="nb">is this mapping of groups of circuit elements to larger components.</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">Fine</span><span class="o">-</span><span class="nb">grain synthesis would be matching the circuit elements to smaller</span>
<span class="nb">components, such as LUTs, gates, or half</span><span class="o">-</span><span class="nb"> and full</span><span class="o">-</span><span class="nb">adders.</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{The extract pass}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Like the {</span><span class="nv">\tt</span><span class="nb"> techmap} pass, the {</span><span class="nv">\tt</span><span class="nb"> extract} pass is called with</span>
<span class="nb">a map file. It compares the circuits inside the modules of the map file</span>
<span class="nb">with the design and looks for sub</span><span class="o">-</span><span class="nb">circuits in the design that match any</span>
<span class="nb">of the modules in the map file.</span>
<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> If a match is found, the {</span><span class="nv">\tt</span><span class="nb"> extract} pass will replace the matching</span>
<span class="nb">subcircuit with an instance of the module from the map file.</span>
<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> In a way the {</span><span class="nv">\tt</span><span class="nb"> extract} pass is the inverse of the techmap pass.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example </span><span class="m">1</span><span class="o">/</span><span class="m">2</span><span class="nb">}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\vskip</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{tikzpicture}</span>
<span class="nb">    </span><span class="nv">\node</span><span class="nb"> at </span><span class="o">(</span><span class="m">0</span><span class="nb">,</span><span class="m">0</span><span class="o">)</span><span class="nb"> {</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">00</span><span class="nb">a.pdf}};</span>
<span class="nb">    </span><span class="nv">\node</span><span class="nb"> at </span><span class="o">(</span><span class="m">3</span><span class="nb">,</span><span class="o">-</span><span class="m">3</span><span class="o">)</span><span class="nb"> {</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">8</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">00</span><span class="nb">b.pdf}};</span>
<span class="nb">    </span><span class="nv">\draw</span><span class="o">[</span><span class="nb">yshift</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm,thick,</span><span class="o">-</span><span class="nb">latex</span><span class="o">]</span><span class="nb"> </span><span class="o">(</span><span class="m">1</span><span class="nb">,</span><span class="o">-</span><span class="m">1</span><span class="o">)</span><span class="nb"> </span><span class="o">--</span><span class="nb"> </span><span class="o">(</span><span class="m">2</span><span class="nb">,</span><span class="o">-</span><span class="m">2</span><span class="o">)</span><span class="nb">;</span>
<span class="nv">\end</span><span class="nb">{tikzpicture}</span>
<span class="nv">\vss</span><span class="nb">}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">1</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_xmap.v}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">read_verilog macc_simple_test.v</span>
<span class="nb">hierarchy </span><span class="o">-</span><span class="nb">check </span><span class="o">-</span><span class="nb">top test</span>

<span class="nb">extract </span><span class="o">-</span><span class="nb">map macc_simple_xmap.v;;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example </span><span class="m">2</span><span class="o">/</span><span class="m">2</span><span class="nb">}</span>
<span class="nv">\hfil\begin</span><span class="nb">{tabular}{cc}</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\hbox</span><span class="nb"> to </span><span class="m">5</span><span class="nb">cm {</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">01</span><span class="nb">.v}}} &amp;</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\hbox</span><span class="nb"> to </span><span class="m">5</span><span class="nb">cm {</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">02</span><span class="nb">.v}}} </span><span class="nv">\\</span><span class="nb"></span>
<span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> &amp; </span><span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">01</span><span class="nb">a.pdf}} &amp;</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">02</span><span class="nb">a.pdf}} </span><span class="nv">\\</span><span class="nb"></span>
<span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> &amp; </span><span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">01</span><span class="nb">b.pdf}} &amp;</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">02</span><span class="nb">b.pdf}} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{tabular}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{The wrap</span><span class="o">-</span><span class="nb">extract</span><span class="o">-</span><span class="nb">unwrap method}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\scriptsize</span><span class="nb"></span>
<span class="nb">Often a coarse</span><span class="o">-</span><span class="nb">grain element has a constant bit</span><span class="o">-</span><span class="nb">width, but can be used to</span>
<span class="nb">implement operations with a smaller bit</span><span class="o">-</span><span class="nb">width. For example, a </span><span class="m">18</span><span class="nb">x</span><span class="m">25</span><span class="o">-</span><span class="nb">bit multiplier</span>
<span class="nb">can also be used to implement </span><span class="m">16</span><span class="nb">x</span><span class="m">20</span><span class="o">-</span><span class="nb">bit multiplication.</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">A way of mapping such elements in coarse grain synthesis is the wrap</span><span class="o">-</span><span class="nb">extract</span><span class="o">-</span><span class="nb">unwrap method:</span>

<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> {</span><span class="nv">\bf</span><span class="nb"> wrap} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">Identify candidate</span><span class="o">-</span><span class="nb">cells in the circuit and wrap them in a cell with a constant</span>
<span class="nb">wider bit</span><span class="o">-</span><span class="nb">width using {</span><span class="nv">\tt</span><span class="nb"> techmap}. The wrappers use the same parameters as the original cell, so</span>
<span class="nb">the information about the original width of the ports is preserved. </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">Then use the {</span><span class="nv">\tt</span><span class="nb"> connwrappers} command to connect up the bit</span><span class="o">-</span><span class="nb">extended in</span><span class="o">-</span><span class="nb"> and</span>
<span class="nb">outputs of the wrapper cells.</span>
<span class="nv">\item</span><span class="nb"> {</span><span class="nv">\bf</span><span class="nb"> extract} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">Now all operations are encoded using the same bit</span><span class="o">-</span><span class="nb">width as the coarse grain element. The {</span><span class="nv">\tt</span><span class="nb"></span>
<span class="nb">extract} command can be used to replace circuits with cells of the target architecture.</span>
<span class="nv">\item</span><span class="nb"> {</span><span class="nv">\bf</span><span class="nb"> unwrap} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">The remaining wrapper cell can be unwrapped using {</span><span class="nv">\tt</span><span class="nb"> techmap}.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">The following sides detail an example that shows how to map MACC operations of</span>
<span class="nb">arbitrary size to MACC cells with a </span><span class="m">18</span><span class="nb">x</span><span class="m">25</span><span class="o">-</span><span class="nb">bit multiplier and a </span><span class="m">48</span><span class="o">-</span><span class="nb">bit adder </span><span class="o">(</span><span class="nb">such as</span>
<span class="nb">the Xilinx DSP</span><span class="m">48</span><span class="nb"> cells</span><span class="o">)</span><span class="nb">.</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Example: DSP</span><span class="m">48</span><span class="nv">\_</span><span class="nb">MACC}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">1</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Preconditioning: {</span><span class="nv">\tt</span><span class="nb"> macc</span><span class="nv">\_</span><span class="nb">xilinx</span><span class="nv">\_</span><span class="nb">swap</span><span class="nv">\_</span><span class="nb">map.v} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">Make sure {</span><span class="nv">\tt</span><span class="nb"> A} is the smaller port on all multipliers</span>

<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, lastline</span><span class="o">=</span><span class="m">15</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_swap_map.v}</span>
<span class="nv">\column</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">16</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_swap_map.v}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">2</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Wrapping multipliers: {</span><span class="nv">\tt</span><span class="nb"> macc</span><span class="nv">\_</span><span class="nb">xilinx</span><span class="nv">\_</span><span class="nb">wrap</span><span class="nv">\_</span><span class="nb">map.v}</span>

<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, lastline</span><span class="o">=</span><span class="m">23</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_wrap_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">24</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">46</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_wrap_map.v}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">3</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Wrapping adders: {</span><span class="nv">\tt</span><span class="nb"> macc</span><span class="nv">\_</span><span class="nb">xilinx</span><span class="nv">\_</span><span class="nb">wrap</span><span class="nv">\_</span><span class="nb">map.v}</span>

<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">48</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">67</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_wrap_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">68</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">89</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_wrap_map.v}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">4</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Extract: {</span><span class="nv">\tt</span><span class="nb"> macc</span><span class="nv">\_</span><span class="nb">xilinx</span><span class="nv">\_</span><span class="nb">xmap.v}</span>

<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">1</span><span class="nb">,  lastline</span><span class="o">=</span><span class="m">17</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_xmap.v}</span>

<span class="nb">.. simply use the same wrapping commands on this module as on the design to create a template for the {</span><span class="nv">\tt</span><span class="nb"> extract} command.</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">5</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Unwrapping multipliers: {</span><span class="nv">\tt</span><span class="nb"> macc</span><span class="nv">\_</span><span class="nb">xilinx</span><span class="nv">\_</span><span class="nb">unwrap</span><span class="nv">\_</span><span class="nb">map.v}</span>

<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">1</span><span class="nb">,  lastline</span><span class="o">=</span><span class="m">17</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_unwrap_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">18</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">30</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_unwrap_map.v}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">6</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Unwrapping adders: {</span><span class="nv">\tt</span><span class="nb"> macc</span><span class="nv">\_</span><span class="nb">xilinx</span><span class="nv">\_</span><span class="nb">unwrap</span><span class="nv">\_</span><span class="nb">map.v}</span>

<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">32</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">48</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_unwrap_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">49</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">61</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_unwrap_map.v}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">7</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nv">\hfil\begin</span><span class="nb">{tabular}{cc}</span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">1</span><span class="nb">} &amp; {</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">2</span><span class="nb">} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\hbox</span><span class="nb"> to </span><span class="m">5</span><span class="nb">cm {</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, firstline</span><span class="o">=</span><span class="m">1</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">6</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test.v}}} &amp;</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\hbox</span><span class="nb"> to </span><span class="m">5</span><span class="nb">cm {</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, firstline</span><span class="o">=</span><span class="m">8</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">13</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test.v}}} </span><span class="nv">\\</span><span class="nb"></span>
<span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> &amp; </span><span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{tabular}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">                            read_verilog macc_xilinx_test.v</span>
<span class="nb">                            hierarchy </span><span class="o">-</span><span class="nb">check</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span>
<span class="nv">\hfil\begin</span><span class="nb">{tabular}{cc}</span>
<span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> &amp; </span><span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">1</span><span class="nb">a.pdf}} &amp;</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">a.pdf}} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{tabular}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">8</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nv">\hfil\begin</span><span class="nb">{tabular}{cc}</span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">1</span><span class="nb">} &amp; {</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">2</span><span class="nb">} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">1</span><span class="nb">a.pdf}} &amp;</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">a.pdf}} </span><span class="nv">\\</span><span class="nb"></span>
<span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> &amp; </span><span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{tabular}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">                         techmap </span><span class="o">-</span><span class="nb">map macc_xilinx_swap_map.v ;;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\hfil\begin</span><span class="nb">{tabular}{cc}</span>
<span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> &amp; </span><span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">1</span><span class="nb">b.pdf}} &amp;</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">b.pdf}} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{tabular}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">9</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Wrapping in {</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">1</span><span class="nb">}:</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span><span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">4</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">1</span><span class="nb">b.pdf}}</span><span class="nv">\vss</span><span class="nb">}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">techmap </span><span class="o">-</span><span class="nb">map macc_xilinx_wrap_map.v</span>

<span class="nb">connwrappers </span><span class="o">-</span><span class="nb">unsigned </span><span class="s">$</span><span class="nb">__</span>mul<span class="nb">_</span>wrapper <span class="k">\</span>
                            Y Y<span class="nb">_</span>WIDTH <span class="k">\</span>
             -unsigned <span class="s">$</span><span class="nb">__add_wrapper </span><span class="err">\</span><span class="nb"></span>
<span class="nb">                            Y Y_WIDTH ;;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>

<span class="nv">\vskip</span><span class="m">1</span><span class="nb">cm</span>
<span class="nv">\hfil\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="nv">\linewidth</span><span class="nb">,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">1</span><span class="nb">c.pdf}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">10</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Wrapping in {</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">2</span><span class="nb">}:</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span><span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">4</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">b.pdf}}</span><span class="nv">\vss</span><span class="nb">}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">techmap </span><span class="o">-</span><span class="nb">map macc_xilinx_wrap_map.v</span>

<span class="nb">connwrappers </span><span class="o">-</span><span class="nb">unsigned </span><span class="s">$</span><span class="nb">__</span>mul<span class="nb">_</span>wrapper <span class="k">\</span>
                            Y Y<span class="nb">_</span>WIDTH <span class="k">\</span>
             -unsigned <span class="s">$</span><span class="nb">__add_wrapper </span><span class="err">\</span><span class="nb"></span>
<span class="nb">                            Y Y_WIDTH ;;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>

<span class="nv">\vskip</span><span class="m">1</span><span class="nb">cm</span>
<span class="nv">\hfil\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="nv">\linewidth</span><span class="nb">,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">c.pdf}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">11</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Extract in {</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">1</span><span class="nb">}:</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">4</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">design </span><span class="o">-</span><span class="nb">push</span>
<span class="nb">read_verilog macc_xilinx_xmap.v</span>
<span class="nb">techmap </span><span class="o">-</span><span class="nb">map macc_xilinx_swap_map.v</span>
<span class="nb">techmap </span><span class="o">-</span><span class="nb">map macc_xilinx_wrap_map.v;;</span>
<span class="nb">design </span><span class="o">-</span><span class="nb">save __macc_xilinx_xmap</span>
<span class="nb">design </span><span class="o">-</span><span class="nb">pop</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\vss</span><span class="nb">}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">1</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">extract </span><span class="o">-</span><span class="nb">constports </span><span class="o">-</span><span class="nb">ignore_parameters </span><span class="err">\</span><span class="nb"></span>
<span class="nb">        </span><span class="o">-</span><span class="nb">map </span><span class="c">%__macc_xilinx_xmap       \</span>
<span class="nb">        </span><span class="o">-</span><span class="nb">swap </span><span class="s">$</span><span class="nb">__</span>add<span class="nb">_</span>wrapper A,B ;;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\vbox</span> to 0cm<span class="nb">{</span><span class="k">\fbox</span><span class="nb">{</span><span class="k">\includegraphics</span><span class="na">[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExAdv/macc<span class="nb">_</span>xilinx<span class="nb">_</span>test1c.pdf<span class="nb">}}</span><span class="k">\vss</span><span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>columns<span class="nb">}</span>

<span class="k">\vskip</span>2cm
<span class="k">\hfil\includegraphics</span><span class="na">[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExAdv/macc<span class="nb">_</span>xilinx<span class="nb">_</span>test1d.pdf<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">{}</span> -- 12/13<span class="nb">}</span>
Extract in <span class="nb">{</span><span class="k">\tt</span> test2<span class="nb">}</span>:
<span class="k">\begin</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>4.5cm<span class="nb">}</span>
<span class="k">\vbox</span> to 0cm<span class="nb">{</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[linewidth=5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
design -push
read<span class="nb">_</span>verilog macc<span class="nb">_</span>xilinx<span class="nb">_</span>xmap.v
techmap -map macc<span class="nb">_</span>xilinx<span class="nb">_</span>swap<span class="nb">_</span>map.v
techmap -map macc<span class="nb">_</span>xilinx<span class="nb">_</span>wrap<span class="nb">_</span>map.v;;
design -save <span class="nb">__</span>macc<span class="nb">_</span>xilinx<span class="nb">_</span>xmap
design -pop
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\vss</span><span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5.5cm<span class="nb">}</span>
<span class="k">\vskip</span>-1cm
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[linewidth=5.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
extract -constports -ignore<span class="nb">_</span>parameters <span class="k">\</span>
        -map <span class="c">%__macc_xilinx_xmap       \</span>
        -swap <span class="s">$</span><span class="nb">__add_wrapper A,B ;;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span><span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">4</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">c.pdf}}</span><span class="nv">\vss</span><span class="nb">}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>

<span class="nv">\vskip</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\hfil\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">11</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">d.pdf}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">13</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Unwrap in {</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">2</span><span class="nb">}:</span>

<span class="nv">\hfil\begin</span><span class="nb">{tikzpicture}</span>
<span class="nv">\node</span><span class="nb"> at </span><span class="o">(</span><span class="m">0</span><span class="nb">,</span><span class="m">0</span><span class="o">)</span><span class="nb"> {</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">11</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">d.pdf}};</span>
<span class="nv">\node</span><span class="nb"> at </span><span class="o">(</span><span class="m">0</span><span class="nb">,</span><span class="o">-</span><span class="m">4</span><span class="o">)</span><span class="nb"> {</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">8</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">e.pdf}};</span>
<span class="nv">\node</span><span class="nb"> at </span><span class="o">(</span><span class="m">1</span><span class="nb">,</span><span class="o">-</span><span class="m">1</span><span class="nb">.</span><span class="m">7</span><span class="o">)</span><span class="nb"> {</span><span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, frame</span><span class="o">=</span><span class="nb">single, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">techmap </span><span class="o">-</span><span class="nb">map macc_xilinx_unwrap_map.v ;;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}};</span>
<span class="nv">\draw</span><span class="o">[-</span><span class="nb">latex</span><span class="o">]</span><span class="nb"> </span><span class="o">(</span><span class="m">4</span><span class="nb">,</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">7</span><span class="o">)</span><span class="nb"> .. controls </span><span class="o">(</span><span class="m">5</span><span class="nb">,</span><span class="o">-</span><span class="m">1</span><span class="nb">.</span><span class="m">7</span><span class="o">)</span><span class="nb"> .. </span><span class="o">(</span><span class="m">4</span><span class="nb">,</span><span class="o">-</span><span class="m">2</span><span class="nb">.</span><span class="m">7</span><span class="o">)</span><span class="nb">;</span>
<span class="nv">\end</span><span class="nb">{tikzpicture}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>


<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="nv">\subsection</span><span class="nb">{Automatic design changes}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span>
<span class="nv">\subsectionpage</span><span class="nb"></span>
<span class="nv">\subsectionpagesuffix</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Changing the design from Yosys}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nb">Yosys commands can be used to change the design in memory. Examples of this are:</span>

<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> {</span><span class="nv">\bf</span><span class="nb"> Changes in design hierarchy} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">Commands such as {</span><span class="nv">\tt</span><span class="nb"> flatten} and {</span><span class="nv">\tt</span><span class="nb"> submod} can be used to change the design hierarchy, i.e.</span>
<span class="nb">flatten the hierarchy or moving parts of a module to a submodule. This has applications in synthesis</span>
<span class="nb">scripts as well as in reverse engineering and analysis.</span>

<span class="nv">\item</span><span class="nb"> {</span><span class="nv">\bf</span><span class="nb"> Behavioral changes} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">Commands such as {</span><span class="nv">\tt</span><span class="nb"> techmap} can be used to make behavioral changes to the design, for example</span>
<span class="nb">changing asynchronous resets to synchronous resets. This has applications in design space exploration</span>
<span class="o">(</span><span class="nb">evaluation of various architectures for one circuit</span><span class="o">)</span><span class="nb">.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Example: Async reset to sync reset}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nb">The following techmap map file replaces all positive</span><span class="o">-</span><span class="nb">edge async reset flip</span><span class="o">-</span><span class="nb">flops with</span>
<span class="nb">positive</span><span class="o">-</span><span class="nb">edge sync reset flip</span><span class="o">-</span><span class="nb">flops. The code is taken from the example Yosys script</span>
<span class="nb">for ASIC synthesis of the Amber ARMv</span><span class="m">2</span><span class="nb"> CPU.</span>

<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb"></span>
<span class="o">(*</span><span class="nb"> techmap_celltype </span><span class="o">=</span><span class="nb"> &quot;</span><span class="s">$</span>adff&quot; *)
module adff2dff (CLK, ARST, D, Q);

    parameter WIDTH = 1;
    parameter CLK<span class="nb">_</span>POLARITY = 1;
    parameter ARST<span class="nb">_</span>POLARITY = 1;
    parameter ARST<span class="nb">_</span>VALUE = 0;

    input CLK, ARST;
    input [WIDTH-1:0] D;
    output reg [WIDTH-1:0] Q;

    wire [1023:0] <span class="nb">_</span>TECHMAP<span class="nb">_</span>DO<span class="nb">_</span> = &quot;proc&quot;;

    wire <span class="nb">_</span>TECHMAP<span class="nb">_</span>FAIL<span class="nb">_</span> = !CLK<span class="nb">_</span>POLARITY || !ARST<span class="nb">_</span>POLARITY;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\vss</span><span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>4cm<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=Verilog]
// ..continued..


    always @(posedge CLK)
        if (ARST)
            Q &lt;= ARST<span class="nb">_</span>VALUE;
        else
             &lt;= D;

endmodule
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>columns<span class="nb">}</span>

<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Summary<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> A lot can be achieved in Yosys just with the standard set of commands.
<span class="k">\item</span> The commands <span class="nb">{</span><span class="k">\tt</span> techmap<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> extract<span class="nb">}</span> can be used to prototype many complex synthesis tasks.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>center<span class="nb">}</span>
Questions?
<span class="k">\end</span><span class="nb">{</span>center<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\url</span><span class="nb">{</span>https://yosyshq.net/yosys/<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>
</pre></div>
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