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td.linenos pre { color: #000000; background-color: #f0f0f0; padding: 0 5px 0 5px; }
span.linenos { color: #000000; background-color: #f0f0f0; padding: 0 5px 0 5px; }
td.linenos pre.special { color: #000000; background-color: #ffffc0; padding: 0 5px 0 5px; }
span.linenos.special { color: #000000; background-color: #ffffc0; padding: 0 5px 0 5px; }
.highlight .hll { background-color: #ffffcc }
.highlight { background: #ffffff; }
.highlight .c { color: #888888 } /* Comment */
.highlight .err { color: #a61717; background-color: #e3d2d2 } /* Error */
.highlight .k { color: #008800; font-weight: bold } /* Keyword */
.highlight .ch { color: #888888 } /* Comment.Hashbang */
.highlight .cm { color: #888888 } /* Comment.Multiline */
.highlight .cp { color: #cc0000; font-weight: bold } /* Comment.Preproc */
.highlight .cpf { color: #888888 } /* Comment.PreprocFile */
.highlight .c1 { color: #888888 } /* Comment.Single */
.highlight .cs { color: #cc0000; font-weight: bold; background-color: #fff0f0 } /* Comment.Special */
.highlight .gd { color: #000000; background-color: #ffdddd } /* Generic.Deleted */
.highlight .ge { font-style: italic } /* Generic.Emph */
.highlight .gr { color: #aa0000 } /* Generic.Error */
.highlight .gh { color: #333333 } /* Generic.Heading */
.highlight .gi { color: #000000; background-color: #ddffdd } /* Generic.Inserted */
.highlight .go { color: #888888 } /* Generic.Output */
.highlight .gp { color: #555555 } /* Generic.Prompt */
.highlight .gs { font-weight: bold } /* Generic.Strong */
.highlight .gu { color: #666666 } /* Generic.Subheading */
.highlight .gt { color: #aa0000 } /* Generic.Traceback */
.highlight .kc { color: #008800; font-weight: bold } /* Keyword.Constant */
.highlight .kd { color: #008800; font-weight: bold } /* Keyword.Declaration */
.highlight .kn { color: #008800; font-weight: bold } /* Keyword.Namespace */
.highlight .kp { color: #008800 } /* Keyword.Pseudo */
.highlight .kr { color: #008800; font-weight: bold } /* Keyword.Reserved */
.highlight .kt { color: #888888; font-weight: bold } /* Keyword.Type */
.highlight .m { color: #0000DD; font-weight: bold } /* Literal.Number */
.highlight .s { color: #dd2200; background-color: #fff0f0 } /* Literal.String */
.highlight .na { color: #336699 } /* Name.Attribute */
.highlight .nb { color: #003388 } /* Name.Builtin */
.highlight .nc { color: #bb0066; font-weight: bold } /* Name.Class */
.highlight .no { color: #003366; font-weight: bold } /* Name.Constant */
.highlight .nd { color: #555555 } /* Name.Decorator */
.highlight .ne { color: #bb0066; font-weight: bold } /* Name.Exception */
.highlight .nf { color: #0066bb; font-weight: bold } /* Name.Function */
.highlight .nl { color: #336699; font-style: italic } /* Name.Label */
.highlight .nn { color: #bb0066; font-weight: bold } /* Name.Namespace */
.highlight .py { color: #336699; font-weight: bold } /* Name.Property */
.highlight .nt { color: #bb0066; font-weight: bold } /* Name.Tag */
.highlight .nv { color: #336699 } /* Name.Variable */
.highlight .ow { color: #008800 } /* Operator.Word */
.highlight .w { color: #bbbbbb } /* Text.Whitespace */
.highlight .mb { color: #0000DD; font-weight: bold } /* Literal.Number.Bin */
.highlight .mf { color: #0000DD; font-weight: bold } /* Literal.Number.Float */
.highlight .mh { color: #0000DD; font-weight: bold } /* Literal.Number.Hex */
.highlight .mi { color: #0000DD; font-weight: bold } /* Literal.Number.Integer */
.highlight .mo { color: #0000DD; font-weight: bold } /* Literal.Number.Oct */
.highlight .sa { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Affix */
.highlight .sb { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Backtick */
.highlight .sc { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Char */
.highlight .dl { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Delimiter */
.highlight .sd { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Doc */
.highlight .s2 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Double */
.highlight .se { color: #0044dd; background-color: #fff0f0 } /* Literal.String.Escape */
.highlight .sh { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Heredoc */
.highlight .si { color: #3333bb; background-color: #fff0f0 } /* Literal.String.Interpol */
.highlight .sx { color: #22bb22; background-color: #f0fff0 } /* Literal.String.Other */
.highlight .sr { color: #008800; background-color: #fff0ff } /* Literal.String.Regex */
.highlight .s1 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Single */
.highlight .ss { color: #aa6600; background-color: #fff0f0 } /* Literal.String.Symbol */
.highlight .bp { color: #003388 } /* Name.Builtin.Pseudo */
.highlight .fm { color: #0066bb; font-weight: bold } /* Name.Function.Magic */
.highlight .vc { color: #336699 } /* Name.Variable.Class */
.highlight .vg { color: #dd7700 } /* Name.Variable.Global */
.highlight .vi { color: #3333bb } /* Name.Variable.Instance */
.highlight .vm { color: #336699 } /* Name.Variable.Magic */
.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */</style><div class="highlight"><pre><span></span><span class="k">\chapter</span><span class="nb">{</span>Technology Mapping<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>chapter:techmap<span class="nb">}</span>

Previous chapters outlined how HDL code is transformed into an RTL netlist. The
RTL netlist is still based on abstract coarse-grain cell types like arbitrary
width adders and even multipliers. This chapter covers how an RTL netlist is
transformed into a functionally equivalent netlist utilizing the cell types
available in the target architecture.

Technology mapping is often performed in two phases. In the first phase RTL cells
are mapped to an internal library of single-bit cells (see Sec.~<span class="k">\ref</span><span class="nb">{</span>sec:celllib<span class="nb">_</span>gates<span class="nb">}</span>).
In the second phase this netlist of internal gate types is transformed to a netlist
of gates from the target technology library.

When the target architecture provides coarse-grain cells (such as block ram
or ALUs), these must be mapped to directly form the RTL netlist, as information
on the coarse-grain structure of the design is lost when it is mapped to
bit-width gate types.

<span class="k">\section</span><span class="nb">{</span>Cell Substitution<span class="nb">}</span>

The simplest form of technology mapping is cell substitution, as performed by
the <span class="nb">{</span><span class="k">\tt</span> techmap<span class="nb">}</span> pass. This pass, when provided with a Verilog file that
implements the RTL cell types using simpler cells, simply replaces the RTL
cells with the provided implementation.

When no map file is provided, <span class="nb">{</span><span class="k">\tt</span> techmap<span class="nb">}</span> uses a built-in map file that
maps the Yosys RTL cell types to the internal gate library used by Yosys.
The curious reader may find this map file as <span class="nb">{</span><span class="k">\tt</span> techlibs/common/techmap.v<span class="nb">}</span> in
the Yosys source tree.

Additional features have been added to <span class="nb">{</span><span class="k">\tt</span> techmap<span class="nb">}</span> to allow for conditional
mapping of cells (see <span class="nb">{</span><span class="k">\tt</span> help techmap<span class="nb">}</span> or Sec.~<span class="k">\ref</span><span class="nb">{</span>cmd:techmap<span class="nb">}</span>). This can
for example be useful if the target architecture supports hardware multipliers for
certain bit-widths but not for others.

A usual synthesis flow would first use the <span class="nb">{</span><span class="k">\tt</span> techmap<span class="nb">}</span> pass to directly map
some RTL cells to coarse-grain cells provided by the target architecture (if
any) and then use techmap with the built-in default file to map the remaining
RTL cells to gate logic.

<span class="k">\section</span><span class="nb">{</span>Subcircuit Substitution<span class="nb">}</span>

Sometimes the target architecture provides cells that are more powerful than
the RTL cells used by Yosys. For example a cell in the target architecture that can
calculate the absolute-difference of two numbers does not match any single
RTL cell type but only combinations of cells.

For these cases Yosys provides the <span class="nb">{</span><span class="k">\tt</span> extract<span class="nb">}</span> pass that can match a given set
of modules against a design and identify the portions of the design that are
identical (i.e.~isomorphic subcircuits) to any of the given modules. These
matched subcircuits are then replaced by instances of the given modules.

The <span class="nb">{</span><span class="k">\tt</span> extract<span class="nb">}</span> pass also finds basic variations of the given modules,
such as swapped inputs on commutative cell types.

In addition to this the <span class="nb">{</span><span class="k">\tt</span> extract<span class="nb">}</span> pass also has limited support for
frequent subcircuit mining, i.e.~the process of finding recurring subcircuits
in the design. This has a few applications, including the design of new
coarse-grain architectures <span class="k">\cite</span><span class="nb">{</span>intersynthFdlBookChapter<span class="nb">}</span>.

The hard algorithmic work done by the <span class="nb">{</span><span class="k">\tt</span> extract<span class="nb">}</span> pass (solving the
isomorphic subcircuit problem and frequent subcircuit mining) is performed
using the SubCircuit library that can also be used stand-alone without Yosys
(see Sec.~<span class="k">\ref</span><span class="nb">{</span>sec:SubCircuit<span class="nb">}</span>).

<span class="k">\section</span><span class="nb">{</span>Gate-Level Technology Mapping<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>sec:techmap<span class="nb">_</span>extern<span class="nb">}</span>

On the gate-level the target architecture is usually described by a ``Liberty
file&#39;&#39;. The Liberty file format is an industry standard format that can be
used to describe the behaviour and other properties of standard library cells
<span class="k">\citeweblink</span><span class="nb">{</span>LibertyFormat<span class="nb">}</span>.

Mapping a design utilizing the Yosys internal gate library (e.g.~as a result
of mapping it to this representation using the <span class="nb">{</span><span class="k">\tt</span> techmap<span class="nb">}</span> pass) is
performed in two phases.

First the register cells must be mapped to the registers that are available
on the target architectures. The target architecture might not provide all
variations of d-type flip-flops with positive and negative clock edge,
high-active and low-active asynchronous set and/or reset, etc. Therefore the
process of mapping the registers might add additional inverters to the design
and thus it is important to map the register cells first.

Mapping of the register cells may be performed by using the <span class="nb">{</span><span class="k">\tt</span> dfflibmap<span class="nb">}</span>
pass. This pass expects a Liberty file as argument (using the <span class="nb">{</span><span class="k">\tt</span> -liberty<span class="nb">}</span>
option) and only uses the register cells from the Liberty file.

Secondly the combinational logic must be mapped to the target architecture.
This is done using the external program ABC <span class="k">\citeweblink</span><span class="nb">{</span>ABC<span class="nb">}</span> via the
<span class="nb">{</span><span class="k">\tt</span> abc<span class="nb">}</span> pass by using the <span class="nb">{</span><span class="k">\tt</span> -liberty<span class="nb">}</span> option to the pass. Note that
in this case only the combinatorial cells are used from the cell library.

Occasionally Liberty files contain trade secrets (such as sensitive timing
information) that cannot be shared freely. This complicates processes such as
reporting bugs in the tools involved. When the information in the Liberty file
used by Yosys and ABC are not part of the sensitive information, the additional
tool <span class="nb">{</span><span class="k">\tt</span> yosys-filterlib<span class="nb">}</span> (see Sec.~<span class="k">\ref</span><span class="nb">{</span>sec:filterlib<span class="nb">}</span>) can be used to strip
the sensitive information from the Liberty file.
</pre></div>
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