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<a id='n343' href='#n343'>343</a>
<a id='n344' href='#n344'>344</a>
<a id='n345' href='#n345'>345</a>
<a id='n346' href='#n346'>346</a>
<a id='n347' href='#n347'>347</a>
<a id='n348' href='#n348'>348</a>
<a id='n349' href='#n349'>349</a>
<a id='n350' href='#n350'>350</a>
<a id='n351' href='#n351'>351</a>
<a id='n352' href='#n352'>352</a>
<a id='n353' href='#n353'>353</a>
<a id='n354' href='#n354'>354</a>
<a id='n355' href='#n355'>355</a>
<a id='n356' href='#n356'>356</a>
<a id='n357' href='#n357'>357</a>
<a id='n358' href='#n358'>358</a>
<a id='n359' href='#n359'>359</a>
<a id='n360' href='#n360'>360</a>
<a id='n361' href='#n361'>361</a>
<a id='n362' href='#n362'>362</a>
<a id='n363' href='#n363'>363</a>
<a id='n364' href='#n364'>364</a>
<a id='n365' href='#n365'>365</a>
<a id='n366' href='#n366'>366</a>
<a id='n367' href='#n367'>367</a>
<a id='n368' href='#n368'>368</a>
<a id='n369' href='#n369'>369</a>
<a id='n370' href='#n370'>370</a>
<a id='n371' href='#n371'>371</a>
<a id='n372' href='#n372'>372</a>
<a id='n373' href='#n373'>373</a>
<a id='n374' href='#n374'>374</a>
<a id='n375' href='#n375'>375</a>
<a id='n376' href='#n376'>376</a>
<a id='n377' href='#n377'>377</a>
<a id='n378' href='#n378'>378</a>
<a id='n379' href='#n379'>379</a>
<a id='n380' href='#n380'>380</a>
<a id='n381' href='#n381'>381</a>
<a id='n382' href='#n382'>382</a>
<a id='n383' href='#n383'>383</a>
<a id='n384' href='#n384'>384</a>
<a id='n385' href='#n385'>385</a>
<a id='n386' href='#n386'>386</a>
<a id='n387' href='#n387'>387</a>
<a id='n388' href='#n388'>388</a>
<a id='n389' href='#n389'>389</a>
<a id='n390' href='#n390'>390</a>
<a id='n391' href='#n391'>391</a>
<a id='n392' href='#n392'>392</a>
<a id='n393' href='#n393'>393</a>
<a id='n394' href='#n394'>394</a>
<a id='n395' href='#n395'>395</a>
<a id='n396' href='#n396'>396</a>
<a id='n397' href='#n397'>397</a>
<a id='n398' href='#n398'>398</a>
<a id='n399' href='#n399'>399</a>
<a id='n400' href='#n400'>400</a>
<a id='n401' href='#n401'>401</a>
<a id='n402' href='#n402'>402</a>
<a id='n403' href='#n403'>403</a>
<a id='n404' href='#n404'>404</a>
<a id='n405' href='#n405'>405</a>
<a id='n406' href='#n406'>406</a>
<a id='n407' href='#n407'>407</a>
<a id='n408' href='#n408'>408</a>
<a id='n409' href='#n409'>409</a>
<a id='n410' href='#n410'>410</a>
<a id='n411' href='#n411'>411</a>
<a id='n412' href='#n412'>412</a>
<a id='n413' href='#n413'>413</a>
<a id='n414' href='#n414'>414</a>
<a id='n415' href='#n415'>415</a>
<a id='n416' href='#n416'>416</a>
<a id='n417' href='#n417'>417</a>
<a id='n418' href='#n418'>418</a>
<a id='n419' href='#n419'>419</a>
<a id='n420' href='#n420'>420</a>
<a id='n421' href='#n421'>421</a>
<a id='n422' href='#n422'>422</a>
<a id='n423' href='#n423'>423</a>
<a id='n424' href='#n424'>424</a>
<a id='n425' href='#n425'>425</a>
<a id='n426' href='#n426'>426</a>
<a id='n427' href='#n427'>427</a>
<a id='n428' href='#n428'>428</a>
<a id='n429' href='#n429'>429</a>
<a id='n430' href='#n430'>430</a>
<a id='n431' href='#n431'>431</a>
<a id='n432' href='#n432'>432</a>
<a id='n433' href='#n433'>433</a>
<a id='n434' href='#n434'>434</a>
<a id='n435' href='#n435'>435</a>
<a id='n436' href='#n436'>436</a>
<a id='n437' href='#n437'>437</a>
<a id='n438' href='#n438'>438</a>
<a id='n439' href='#n439'>439</a>
<a id='n440' href='#n440'>440</a>
<a id='n441' href='#n441'>441</a>
<a id='n442' href='#n442'>442</a>
<a id='n443' href='#n443'>443</a>
<a id='n444' href='#n444'>444</a>
<a id='n445' href='#n445'>445</a>
<a id='n446' href='#n446'>446</a>
<a id='n447' href='#n447'>447</a>
<a id='n448' href='#n448'>448</a>
<a id='n449' href='#n449'>449</a>
<a id='n450' href='#n450'>450</a>
<a id='n451' href='#n451'>451</a>
<a id='n452' href='#n452'>452</a>
<a id='n453' href='#n453'>453</a>
<a id='n454' href='#n454'>454</a>
<a id='n455' href='#n455'>455</a>
<a id='n456' href='#n456'>456</a>
<a id='n457' href='#n457'>457</a>
<a id='n458' href='#n458'>458</a>
<a id='n459' href='#n459'>459</a>
<a id='n460' href='#n460'>460</a>
<a id='n461' href='#n461'>461</a>
<a id='n462' href='#n462'>462</a>
<a id='n463' href='#n463'>463</a>
<a id='n464' href='#n464'>464</a>
<a id='n465' href='#n465'>465</a>
<a id='n466' href='#n466'>466</a>
<a id='n467' href='#n467'>467</a>
<a id='n468' href='#n468'>468</a>
<a id='n469' href='#n469'>469</a>
<a id='n470' href='#n470'>470</a>
<a id='n471' href='#n471'>471</a>
<a id='n472' href='#n472'>472</a>
<a id='n473' href='#n473'>473</a>
<a id='n474' href='#n474'>474</a>
<a id='n475' href='#n475'>475</a>
<a id='n476' href='#n476'>476</a>
<a id='n477' href='#n477'>477</a>
<a id='n478' href='#n478'>478</a>
<a id='n479' href='#n479'>479</a>
<a id='n480' href='#n480'>480</a>
<a id='n481' href='#n481'>481</a>
<a id='n482' href='#n482'>482</a>
<a id='n483' href='#n483'>483</a>
<a id='n484' href='#n484'>484</a>
<a id='n485' href='#n485'>485</a>
<a id='n486' href='#n486'>486</a>
<a id='n487' href='#n487'>487</a>
<a id='n488' href='#n488'>488</a>
<a id='n489' href='#n489'>489</a>
<a id='n490' href='#n490'>490</a>
<a id='n491' href='#n491'>491</a>
<a id='n492' href='#n492'>492</a>
<a id='n493' href='#n493'>493</a>
<a id='n494' href='#n494'>494</a>
<a id='n495' href='#n495'>495</a>
<a id='n496' href='#n496'>496</a>
<a id='n497' href='#n497'>497</a>
<a id='n498' href='#n498'>498</a>
<a id='n499' href='#n499'>499</a>
<a id='n500' href='#n500'>500</a>
<a id='n501' href='#n501'>501</a>
<a id='n502' href='#n502'>502</a>
<a id='n503' href='#n503'>503</a>
<a id='n504' href='#n504'>504</a>
<a id='n505' href='#n505'>505</a>
<a id='n506' href='#n506'>506</a>
<a id='n507' href='#n507'>507</a>
<a id='n508' href='#n508'>508</a>
<a id='n509' href='#n509'>509</a>
<a id='n510' href='#n510'>510</a>
<a id='n511' href='#n511'>511</a>
<a id='n512' href='#n512'>512</a>
<a id='n513' href='#n513'>513</a>
<a id='n514' href='#n514'>514</a>
<a id='n515' href='#n515'>515</a>
<a id='n516' href='#n516'>516</a>
<a id='n517' href='#n517'>517</a>
<a id='n518' href='#n518'>518</a>
<a id='n519' href='#n519'>519</a>
<a id='n520' href='#n520'>520</a>
<a id='n521' href='#n521'>521</a>
<a id='n522' href='#n522'>522</a>
<a id='n523' href='#n523'>523</a>
<a id='n524' href='#n524'>524</a>
<a id='n525' href='#n525'>525</a>
<a id='n526' href='#n526'>526</a>
<a id='n527' href='#n527'>527</a>
<a id='n528' href='#n528'>528</a>
<a id='n529' href='#n529'>529</a>
<a id='n530' href='#n530'>530</a>
<a id='n531' href='#n531'>531</a>
<a id='n532' href='#n532'>532</a>
<a id='n533' href='#n533'>533</a>
<a id='n534' href='#n534'>534</a>
<a id='n535' href='#n535'>535</a>
<a id='n536' href='#n536'>536</a>
<a id='n537' href='#n537'>537</a>
<a id='n538' href='#n538'>538</a>
<a id='n539' href='#n539'>539</a>
<a id='n540' href='#n540'>540</a>
<a id='n541' href='#n541'>541</a>
<a id='n542' href='#n542'>542</a>
<a id='n543' href='#n543'>543</a>
<a id='n544' href='#n544'>544</a>
<a id='n545' href='#n545'>545</a>
<a id='n546' href='#n546'>546</a>
<a id='n547' href='#n547'>547</a>
<a id='n548' href='#n548'>548</a>
<a id='n549' href='#n549'>549</a>
<a id='n550' href='#n550'>550</a>
<a id='n551' href='#n551'>551</a>
<a id='n552' href='#n552'>552</a>
<a id='n553' href='#n553'>553</a>
<a id='n554' href='#n554'>554</a>
<a id='n555' href='#n555'>555</a>
<a id='n556' href='#n556'>556</a>
<a id='n557' href='#n557'>557</a>
<a id='n558' href='#n558'>558</a>
<a id='n559' href='#n559'>559</a>
<a id='n560' href='#n560'>560</a>
<a id='n561' href='#n561'>561</a>
<a id='n562' href='#n562'>562</a>
<a id='n563' href='#n563'>563</a>
<a id='n564' href='#n564'>564</a>
<a id='n565' href='#n565'>565</a>
<a id='n566' href='#n566'>566</a>
<a id='n567' href='#n567'>567</a>
<a id='n568' href='#n568'>568</a>
<a id='n569' href='#n569'>569</a>
<a id='n570' href='#n570'>570</a>
<a id='n571' href='#n571'>571</a>
<a id='n572' href='#n572'>572</a>
<a id='n573' href='#n573'>573</a>
<a id='n574' href='#n574'>574</a>
<a id='n575' href='#n575'>575</a>
<a id='n576' href='#n576'>576</a>
<a id='n577' href='#n577'>577</a>
<a id='n578' href='#n578'>578</a>
<a id='n579' href='#n579'>579</a>
<a id='n580' href='#n580'>580</a>
<a id='n581' href='#n581'>581</a>
<a id='n582' href='#n582'>582</a>
<a id='n583' href='#n583'>583</a>
<a id='n584' href='#n584'>584</a>
<a id='n585' href='#n585'>585</a>
<a id='n586' href='#n586'>586</a>
<a id='n587' href='#n587'>587</a>
<a id='n588' href='#n588'>588</a>
<a id='n589' href='#n589'>589</a>
<a id='n590' href='#n590'>590</a>
<a id='n591' href='#n591'>591</a>
<a id='n592' href='#n592'>592</a>
<a id='n593' href='#n593'>593</a>
<a id='n594' href='#n594'>594</a>
<a id='n595' href='#n595'>595</a>
<a id='n596' href='#n596'>596</a>
<a id='n597' href='#n597'>597</a>
<a id='n598' href='#n598'>598</a>
<a id='n599' href='#n599'>599</a>
<a id='n600' href='#n600'>600</a>
<a id='n601' href='#n601'>601</a>
<a id='n602' href='#n602'>602</a>
<a id='n603' href='#n603'>603</a>
<a id='n604' href='#n604'>604</a>
<a id='n605' href='#n605'>605</a>
<a id='n606' href='#n606'>606</a>
<a id='n607' href='#n607'>607</a>
<a id='n608' href='#n608'>608</a>
<a id='n609' href='#n609'>609</a>
<a id='n610' href='#n610'>610</a>
<a id='n611' href='#n611'>611</a>
<a id='n612' href='#n612'>612</a>
<a id='n613' href='#n613'>613</a>
<a id='n614' href='#n614'>614</a>
<a id='n615' href='#n615'>615</a>
<a id='n616' href='#n616'>616</a>
<a id='n617' href='#n617'>617</a>
<a id='n618' href='#n618'>618</a>
<a id='n619' href='#n619'>619</a>
<a id='n620' href='#n620'>620</a>
<a id='n621' href='#n621'>621</a>
<a id='n622' href='#n622'>622</a>
<a id='n623' href='#n623'>623</a>
<a id='n624' href='#n624'>624</a>
<a id='n625' href='#n625'>625</a>
<a id='n626' href='#n626'>626</a>
<a id='n627' href='#n627'>627</a>
<a id='n628' href='#n628'>628</a>
<a id='n629' href='#n629'>629</a>
<a id='n630' href='#n630'>630</a>
<a id='n631' href='#n631'>631</a>
<a id='n632' href='#n632'>632</a>
<a id='n633' href='#n633'>633</a>
<a id='n634' href='#n634'>634</a>
<a id='n635' href='#n635'>635</a>
<a id='n636' href='#n636'>636</a>
<a id='n637' href='#n637'>637</a>
<a id='n638' href='#n638'>638</a>
<a id='n639' href='#n639'>639</a>
<a id='n640' href='#n640'>640</a>
<a id='n641' href='#n641'>641</a>
<a id='n642' href='#n642'>642</a>
<a id='n643' href='#n643'>643</a>
<a id='n644' href='#n644'>644</a>
<a id='n645' href='#n645'>645</a>
<a id='n646' href='#n646'>646</a>
<a id='n647' href='#n647'>647</a>
<a id='n648' href='#n648'>648</a>
<a id='n649' href='#n649'>649</a>
<a id='n650' href='#n650'>650</a>
<a id='n651' href='#n651'>651</a>
<a id='n652' href='#n652'>652</a>
<a id='n653' href='#n653'>653</a>
<a id='n654' href='#n654'>654</a>
<a id='n655' href='#n655'>655</a>
<a id='n656' href='#n656'>656</a>
<a id='n657' href='#n657'>657</a>
<a id='n658' href='#n658'>658</a>
<a id='n659' href='#n659'>659</a>
<a id='n660' href='#n660'>660</a>
<a id='n661' href='#n661'>661</a>
<a id='n662' href='#n662'>662</a>
<a id='n663' href='#n663'>663</a>
<a id='n664' href='#n664'>664</a>
<a id='n665' href='#n665'>665</a>
<a id='n666' href='#n666'>666</a>
<a id='n667' href='#n667'>667</a>
<a id='n668' href='#n668'>668</a>
<a id='n669' href='#n669'>669</a>
<a id='n670' href='#n670'>670</a>
<a id='n671' href='#n671'>671</a>
<a id='n672' href='#n672'>672</a>
<a id='n673' href='#n673'>673</a>
<a id='n674' href='#n674'>674</a>
<a id='n675' href='#n675'>675</a>
<a id='n676' href='#n676'>676</a>
<a id='n677' href='#n677'>677</a>
<a id='n678' href='#n678'>678</a>
<a id='n679' href='#n679'>679</a>
<a id='n680' href='#n680'>680</a>
<a id='n681' href='#n681'>681</a>
<a id='n682' href='#n682'>682</a>
<a id='n683' href='#n683'>683</a>
<a id='n684' href='#n684'>684</a>
<a id='n685' href='#n685'>685</a>
<a id='n686' href='#n686'>686</a>
<a id='n687' href='#n687'>687</a>
<a id='n688' href='#n688'>688</a>
<a id='n689' href='#n689'>689</a>
<a id='n690' href='#n690'>690</a>
<a id='n691' href='#n691'>691</a>
<a id='n692' href='#n692'>692</a>
<a id='n693' href='#n693'>693</a>
<a id='n694' href='#n694'>694</a>
<a id='n695' href='#n695'>695</a>
<a id='n696' href='#n696'>696</a>
<a id='n697' href='#n697'>697</a>
<a id='n698' href='#n698'>698</a>
<a id='n699' href='#n699'>699</a>
<a id='n700' href='#n700'>700</a>
<a id='n701' href='#n701'>701</a>
<a id='n702' href='#n702'>702</a>
<a id='n703' href='#n703'>703</a>
<a id='n704' href='#n704'>704</a>
<a id='n705' href='#n705'>705</a>
<a id='n706' href='#n706'>706</a>
<a id='n707' href='#n707'>707</a>
<a id='n708' href='#n708'>708</a>
<a id='n709' href='#n709'>709</a>
<a id='n710' href='#n710'>710</a>
<a id='n711' href='#n711'>711</a>
<a id='n712' href='#n712'>712</a>
<a id='n713' href='#n713'>713</a>
<a id='n714' href='#n714'>714</a>
<a id='n715' href='#n715'>715</a>
<a id='n716' href='#n716'>716</a>
<a id='n717' href='#n717'>717</a>
<a id='n718' href='#n718'>718</a>
<a id='n719' href='#n719'>719</a>
<a id='n720' href='#n720'>720</a>
<a id='n721' href='#n721'>721</a>
<a id='n722' href='#n722'>722</a>
<a id='n723' href='#n723'>723</a>
<a id='n724' href='#n724'>724</a>
<a id='n725' href='#n725'>725</a>
<a id='n726' href='#n726'>726</a>
<a id='n727' href='#n727'>727</a>
<a id='n728' href='#n728'>728</a>
<a id='n729' href='#n729'>729</a>
<a id='n730' href='#n730'>730</a>
<a id='n731' href='#n731'>731</a>
<a id='n732' href='#n732'>732</a>
<a id='n733' href='#n733'>733</a>
<a id='n734' href='#n734'>734</a>
<a id='n735' href='#n735'>735</a>
<a id='n736' href='#n736'>736</a>
<a id='n737' href='#n737'>737</a>
<a id='n738' href='#n738'>738</a>
<a id='n739' href='#n739'>739</a>
<a id='n740' href='#n740'>740</a>
<a id='n741' href='#n741'>741</a>
<a id='n742' href='#n742'>742</a>
<a id='n743' href='#n743'>743</a>
<a id='n744' href='#n744'>744</a>
<a id='n745' href='#n745'>745</a>
<a id='n746' href='#n746'>746</a>
<a id='n747' href='#n747'>747</a>
<a id='n748' href='#n748'>748</a>
<a id='n749' href='#n749'>749</a>
<a id='n750' href='#n750'>750</a>
<a id='n751' href='#n751'>751</a>
<a id='n752' href='#n752'>752</a>
<a id='n753' href='#n753'>753</a>
<a id='n754' href='#n754'>754</a>
<a id='n755' href='#n755'>755</a>
<a id='n756' href='#n756'>756</a>
<a id='n757' href='#n757'>757</a>
<a id='n758' href='#n758'>758</a>
<a id='n759' href='#n759'>759</a>
<a id='n760' href='#n760'>760</a>
<a id='n761' href='#n761'>761</a>
<a id='n762' href='#n762'>762</a>
<a id='n763' href='#n763'>763</a>
<a id='n764' href='#n764'>764</a>
<a id='n765' href='#n765'>765</a>
<a id='n766' href='#n766'>766</a>
<a id='n767' href='#n767'>767</a>
<a id='n768' href='#n768'>768</a>
<a id='n769' href='#n769'>769</a>
<a id='n770' href='#n770'>770</a>
<a id='n771' href='#n771'>771</a>
<a id='n772' href='#n772'>772</a>
<a id='n773' href='#n773'>773</a>
<a id='n774' href='#n774'>774</a>
<a id='n775' href='#n775'>775</a>
<a id='n776' href='#n776'>776</a>
<a id='n777' href='#n777'>777</a>
<a id='n778' href='#n778'>778</a>
<a id='n779' href='#n779'>779</a>
<a id='n780' href='#n780'>780</a>
<a id='n781' href='#n781'>781</a>
<a id='n782' href='#n782'>782</a>
<a id='n783' href='#n783'>783</a>
<a id='n784' href='#n784'>784</a>
<a id='n785' href='#n785'>785</a>
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<a id='n787' href='#n787'>787</a>
<a id='n788' href='#n788'>788</a>
<a id='n789' href='#n789'>789</a>
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<a id='n791' href='#n791'>791</a>
<a id='n792' href='#n792'>792</a>
<a id='n793' href='#n793'>793</a>
<a id='n794' href='#n794'>794</a>
<a id='n795' href='#n795'>795</a>
<a id='n796' href='#n796'>796</a>
<a id='n797' href='#n797'>797</a>
<a id='n798' href='#n798'>798</a>
<a id='n799' href='#n799'>799</a>
<a id='n800' href='#n800'>800</a>
<a id='n801' href='#n801'>801</a>
<a id='n802' href='#n802'>802</a>
<a id='n803' href='#n803'>803</a>
<a id='n804' href='#n804'>804</a>
<a id='n805' href='#n805'>805</a>
<a id='n806' href='#n806'>806</a>
<a id='n807' href='#n807'>807</a>
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<a id='n809' href='#n809'>809</a>
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<a id='n811' href='#n811'>811</a>
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<a id='n815' href='#n815'>815</a>
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<a id='n817' href='#n817'>817</a>
<a id='n818' href='#n818'>818</a>
<a id='n819' href='#n819'>819</a>
<a id='n820' href='#n820'>820</a>
<a id='n821' href='#n821'>821</a>
<a id='n822' href='#n822'>822</a>
<a id='n823' href='#n823'>823</a>
<a id='n824' href='#n824'>824</a>
<a id='n825' href='#n825'>825</a>
<a id='n826' href='#n826'>826</a>
<a id='n827' href='#n827'>827</a>
<a id='n828' href='#n828'>828</a>
<a id='n829' href='#n829'>829</a>
<a id='n830' href='#n830'>830</a>
<a id='n831' href='#n831'>831</a>
<a id='n832' href='#n832'>832</a>
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<a id='n834' href='#n834'>834</a>
<a id='n835' href='#n835'>835</a>
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<a id='n840' href='#n840'>840</a>
<a id='n841' href='#n841'>841</a>
<a id='n842' href='#n842'>842</a>
<a id='n843' href='#n843'>843</a>
<a id='n844' href='#n844'>844</a>
<a id='n845' href='#n845'>845</a>
<a id='n846' href='#n846'>846</a>
<a id='n847' href='#n847'>847</a>
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<a id='n849' href='#n849'>849</a>
<a id='n850' href='#n850'>850</a>
<a id='n851' href='#n851'>851</a>
<a id='n852' href='#n852'>852</a>
<a id='n853' href='#n853'>853</a>
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<a id='n855' href='#n855'>855</a>
<a id='n856' href='#n856'>856</a>
<a id='n857' href='#n857'>857</a>
<a id='n858' href='#n858'>858</a>
<a id='n859' href='#n859'>859</a>
<a id='n860' href='#n860'>860</a>
<a id='n861' href='#n861'>861</a>
<a id='n862' href='#n862'>862</a>
<a id='n863' href='#n863'>863</a>
<a id='n864' href='#n864'>864</a>
<a id='n865' href='#n865'>865</a>
<a id='n866' href='#n866'>866</a>
<a id='n867' href='#n867'>867</a>
<a id='n868' href='#n868'>868</a>
<a id='n869' href='#n869'>869</a>
<a id='n870' href='#n870'>870</a>
<a id='n871' href='#n871'>871</a>
<a id='n872' href='#n872'>872</a>
<a id='n873' href='#n873'>873</a>
<a id='n874' href='#n874'>874</a>
<a id='n875' href='#n875'>875</a>
<a id='n876' href='#n876'>876</a>
<a id='n877' href='#n877'>877</a>
<a id='n878' href='#n878'>878</a>
<a id='n879' href='#n879'>879</a>
<a id='n880' href='#n880'>880</a>
<a id='n881' href='#n881'>881</a>
<a id='n882' href='#n882'>882</a>
<a id='n883' href='#n883'>883</a>
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<a id='n889' href='#n889'>889</a>
<a id='n890' href='#n890'>890</a>
<a id='n891' href='#n891'>891</a>
<a id='n892' href='#n892'>892</a>
<a id='n893' href='#n893'>893</a>
<a id='n894' href='#n894'>894</a>
<a id='n895' href='#n895'>895</a>
<a id='n896' href='#n896'>896</a>
<a id='n897' href='#n897'>897</a>
<a id='n898' href='#n898'>898</a>
<a id='n899' href='#n899'>899</a>
<a id='n900' href='#n900'>900</a>
<a id='n901' href='#n901'>901</a>
<a id='n902' href='#n902'>902</a>
<a id='n903' href='#n903'>903</a>
<a id='n904' href='#n904'>904</a>
<a id='n905' href='#n905'>905</a>
<a id='n906' href='#n906'>906</a>
<a id='n907' href='#n907'>907</a>
<a id='n908' href='#n908'>908</a>
<a id='n909' href='#n909'>909</a>
<a id='n910' href='#n910'>910</a>
<a id='n911' href='#n911'>911</a>
<a id='n912' href='#n912'>912</a>
<a id='n913' href='#n913'>913</a>
<a id='n914' href='#n914'>914</a>
<a id='n915' href='#n915'>915</a>
<a id='n916' href='#n916'>916</a>
<a id='n917' href='#n917'>917</a>
<a id='n918' href='#n918'>918</a>
<a id='n919' href='#n919'>919</a>
<a id='n920' href='#n920'>920</a>
<a id='n921' href='#n921'>921</a>
<a id='n922' href='#n922'>922</a>
<a id='n923' href='#n923'>923</a>
<a id='n924' href='#n924'>924</a>
<a id='n925' href='#n925'>925</a>
<a id='n926' href='#n926'>926</a>
<a id='n927' href='#n927'>927</a>
<a id='n928' href='#n928'>928</a>
<a id='n929' href='#n929'>929</a>
<a id='n930' href='#n930'>930</a>
<a id='n931' href='#n931'>931</a>
<a id='n932' href='#n932'>932</a>
<a id='n933' href='#n933'>933</a>
<a id='n934' href='#n934'>934</a>
<a id='n935' href='#n935'>935</a>
<a id='n936' href='#n936'>936</a>
<a id='n937' href='#n937'>937</a>
<a id='n938' href='#n938'>938</a>
<a id='n939' href='#n939'>939</a>
<a id='n940' href='#n940'>940</a>
<a id='n941' href='#n941'>941</a>
<a id='n942' href='#n942'>942</a>
<a id='n943' href='#n943'>943</a>
<a id='n944' href='#n944'>944</a>
<a id='n945' href='#n945'>945</a>
<a id='n946' href='#n946'>946</a>
<a id='n947' href='#n947'>947</a>
<a id='n948' href='#n948'>948</a>
<a id='n949' href='#n949'>949</a>
<a id='n950' href='#n950'>950</a>
<a id='n951' href='#n951'>951</a>
<a id='n952' href='#n952'>952</a>
<a id='n953' href='#n953'>953</a>
<a id='n954' href='#n954'>954</a>
<a id='n955' href='#n955'>955</a>
<a id='n956' href='#n956'>956</a>
<a id='n957' href='#n957'>957</a>
<a id='n958' href='#n958'>958</a>
<a id='n959' href='#n959'>959</a>
<a id='n960' href='#n960'>960</a>
<a id='n961' href='#n961'>961</a>
<a id='n962' href='#n962'>962</a>
<a id='n963' href='#n963'>963</a>
<a id='n964' href='#n964'>964</a>
<a id='n965' href='#n965'>965</a>
<a id='n966' href='#n966'>966</a>
<a id='n967' href='#n967'>967</a>
<a id='n968' href='#n968'>968</a>
<a id='n969' href='#n969'>969</a>
<a id='n970' href='#n970'>970</a>
<a id='n971' href='#n971'>971</a>
<a id='n972' href='#n972'>972</a>
<a id='n973' href='#n973'>973</a>
<a id='n974' href='#n974'>974</a>
<a id='n975' href='#n975'>975</a>
<a id='n976' href='#n976'>976</a>
<a id='n977' href='#n977'>977</a>
<a id='n978' href='#n978'>978</a>
<a id='n979' href='#n979'>979</a>
<a id='n980' href='#n980'>980</a>
<a id='n981' href='#n981'>981</a>
<a id='n982' href='#n982'>982</a>
<a id='n983' href='#n983'>983</a>
<a id='n984' href='#n984'>984</a>
<a id='n985' href='#n985'>985</a>
<a id='n986' href='#n986'>986</a>
<a id='n987' href='#n987'>987</a>
<a id='n988' href='#n988'>988</a>
<a id='n989' href='#n989'>989</a>
<a id='n990' href='#n990'>990</a>
</pre></td>
<td class='lines'><pre><code>sign<span class="nb">}</span>;
		<span class="k">\node</span><span class="na">[entity]</span> (module) [right of=design, node distance=11em] <span class="nb">{</span>RTLIL::Module<span class="nb">}</span> edge [-latex] node[above] <span class="nb">{</span><span class="k">\tiny</span> 1 <span class="k">\hskip</span>3em N<span class="nb">}</span> (design);

		<span class="k">\node</span><span class="na">[entity]</span> (process) [fill=green!10, right of=module, node distance=10em] <span class="nb">{</span>RTLIL::Process<span class="nb">}</span> (process.west) edge [-latex] (module);
		<span class="k">\node</span><span class="na">[entity]</span> (memory) [fill=red!10, below of=process] <span class="nb">{</span>RTLIL::Memory<span class="nb">}</span> edge [-latex] (module);
		<span class="k">\node</span><span class="na">[entity]</span> (wire) [fill=blue!10, above of=process] <span class="nb">{</span>RTLIL::Wire<span class="nb">}</span> (wire.west) edge [-latex] (module);
		<span class="k">\node</span><span class="na">[entity]</span> (cell) [fill=blue!10, above of=wire] <span class="nb">{</span>RTLIL::Cell<span class="nb">}</span> (cell.west) edge [-latex] (module);

		<span class="k">\node</span><span class="na">[entity]</span> (case) [fill=green!10, right of=process, node distance=10em] <span class="nb">{</span>RTLIL::CaseRule<span class="nb">}</span> edge [latex-latex] (process);
		<span class="k">\node</span><span class="na">[entity]</span> (sync) [fill=green!10, above of=case] <span class="nb">{</span>RTLIL::SyncRule<span class="nb">}</span> edge [-latex] (process);
		<span class="k">\node</span><span class="na">[entity]</span> (switch) [fill=green!10, below of=case] <span class="nb">{</span>RTLIL::SwitchRule<span class="nb">}</span> edge [-latex] (case);
		<span class="k">\draw</span><span class="na">[latex-]</span> (switch.east) -- ++(1em,0) |- (case.east);
	<span class="k">\end</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>
	<span class="k">\caption</span><span class="nb">{</span>Simplified RTLIL Entity-Relationship Diagram<span class="nb">}</span>
	<span class="k">\label</span><span class="nb">{</span>fig:Overview<span class="nb">_</span>RTLIL<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>figure<span class="nb">}</span>

There is only one active RTLIL::Design object that is used by all frontends,
passes and backends called by the user, e.g.~using a synthesis script. The RTLIL::Design then contains
zero to many RTLIL::Module objects. This corresponds to modules in Verilog or entities in VHDL. Each
module in turn contains objects from three different categories:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> RTLIL::Cell and RTLIL::Wire objects represent classical netlist data.
<span class="k">\item</span> RTLIL::Process objects represent the decision trees (if-then-else statements, etc.) and synchronization
declarations (clock signals and sensitivity) from Verilog <span class="nb">{</span><span class="k">\tt</span> always<span class="nb">}</span> and VHDL <span class="nb">{</span><span class="k">\tt</span> process<span class="nb">}</span> blocks.
<span class="k">\item</span> RTLIL::Memory objects represent addressable memories (arrays).
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>sloppypar<span class="nb">}</span>
Usually the output of the synthesis procedure is a netlist, i.e. all
RTLIL::Process and RTLIL::Memory objects must be replaced by RTLIL::Cell and
RTLIL::Wire objects by synthesis passes.
<span class="k">\end</span><span class="nb">{</span>sloppypar<span class="nb">}</span>

All features of the HDL that cannot be mapped directly to these RTLIL classes must be
transformed to an RTLIL-compatible representation by the HDL frontend. This includes
Verilog-features such as generate-blocks, loops and parameters.

The following sections contain a more detailed description of the different
parts of RTLIL and rationale behind some of the design decisions.

<span class="k">\subsection</span><span class="nb">{</span>RTLIL Identifiers<span class="nb">}</span>

All identifiers in RTLIL (such as module names, port names, signal names, cell
types, etc.) follow the following naming convention: they must either start with
a backslash (<span class="k">\textbackslash</span>) or a dollar sign (<span class="k">\$</span>).

Identifiers starting with a backslash are public visible identifiers. Usually
they originate from one of the HDL input files. For example the signal name ``<span class="nb">{</span><span class="k">\tt</span> <span class="k">\textbackslash</span> sig42<span class="nb">}</span>&#39;&#39;
is most likely a signal that was declared using the name ``<span class="nb">{</span><span class="k">\tt</span> sig42<span class="nb">}</span>&#39;&#39; in an HDL input file.
On the other hand the signal name ``<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>sig42<span class="nb">}</span>&#39;&#39; is an auto-generated signal name. The backends
convert all identifiers that start with a dollar sign to identifiers that do not collide with
identifiers that start with a backslash.

This has three advantages:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> First, it is impossible that an auto-generated identifier collides with
an identifier that was provided by the user.
<span class="k">\item</span> Second, the information about which identifiers were originally
provided by the user is always available which can help guide some optimizations. For example the ``opt<span class="k">\_</span>rmunused&#39;&#39;
tries to preserve signals with a user-provided name but doesn&#39;t hesitate to delete signals that have
auto-generated names when they just duplicate other signals.
<span class="k">\item</span> Third, the delicate job of finding suitable auto-generated public visible
names is deferred to one central location. Internally auto-generated names that
may hold important information for Yosys developers can be used without
disturbing external tools. For example the Verilog backend assigns names in the form <span class="nb">{</span><span class="k">\tt</span> <span class="k">\_</span><span class="nb">{</span><span class="k">\it</span> integer<span class="nb">}</span><span class="k">\_</span><span class="nb">}</span>.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

Whitespace and control characters (any character with an ASCII code 32 or less) are not allowed
in RTLIL identifiers; most frontends and backends cannot support these characters in identifiers.

In order to avoid programming errors, the RTLIL data structures check if all identifiers start
with either a backslash or a dollar sign, and contain no whitespace or control characters.
Violating these rules results in a runtime error.

All RTLIL identifiers are case sensitive.

Some transformations, such as flattening, may have to change identifiers provided by the user
to avoid name collisions. When that happens, attribute ``<span class="nb">{</span><span class="k">\tt</span> hdlname<span class="nb">}</span>`` is attached to the object
with the changed identifier. This attribute contains one name (if emitted directly by the frontend,
or is a result of disambiguation) or multiple names separated by spaces (if a result of flattening).
All names specified in the ``<span class="nb">{</span><span class="k">\tt</span> hdlname<span class="nb">}</span>`` attribute are public and do not include the leading
``<span class="k">\textbackslash</span>``.

<span class="k">\subsection</span><span class="nb">{</span>RTLIL::Design and RTLIL::Module<span class="nb">}</span>

The RTLIL::Design object is basically just a container for RTLIL::Module objects. In addition to
a list of RTLIL::Module objects the RTLIL::Design also keeps a list of <span class="nb">{</span><span class="k">\it</span> selected objects<span class="nb">}</span>, i.e.
the objects that passes should operate on. In most cases the whole design is selected and therefore
passes operate on the whole design. But this mechanism can be useful for more complex synthesis jobs
in which only parts of the design should be affected by certain passes.

Besides the objects shown in the ER diagram in Fig.~<span class="k">\ref</span><span class="nb">{</span>fig:Overview<span class="nb">_</span>RTLIL<span class="nb">}</span> an RTLIL::Module object
contains the following additional properties:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> The module name
<span class="k">\item</span> A list of attributes
<span class="k">\item</span> A list of connections between wires
<span class="k">\item</span> An optional frontend callback used to derive parametrized variations of the module
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

The attributes can be Verilog attributes imported by the Verilog frontend or attributes assigned
by passes. They can be used to store additional metadata about modules or just mark them to be
used by certain part of the synthesis script but not by others.

Verilog and VHDL both support parametric modules (known as ``generic entities&#39;&#39; in VHDL). The RTLIL
format does not support parametric modules itself. Instead each module contains a callback function
into the AST frontend to generate a parametrized variation of the RTLIL::Module as needed. This
callback then returns the auto-generated name of the parametrized variation of the module. (A hash
over the parameters and the module name is used to prohibit the same parametrized variation from being
generated twice. For modules with only a few parameters, a name directly containing all parameters
is generated instead of a hash string.)

<span class="k">\subsection</span><span class="nb">{</span>RTLIL::Cell and RTLIL::Wire<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>sec:rtlil<span class="nb">_</span>cell<span class="nb">_</span>wire<span class="nb">}</span>

A module contains zero to many RTLIL::Cell and RTLIL::Wire objects. Objects of
these types are used to model netlists. Usually the goal of all synthesis efforts is to convert
all modules to a state where the functionality of the module is implemented only by cells
from a given cell library and wires to connect these cells with each other. Note that module
ports are just wires with a special property.

An RTLIL::Wire object has the following properties:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> The wire name
<span class="k">\item</span> A list of attributes
<span class="k">\item</span> A width (buses are just wires with a width &gt; 1)
<span class="k">\item</span> Bus direction (MSB to LSB or vice versa)
<span class="k">\item</span> Lowest valid bit index (LSB or MSB depending on bus direction)
<span class="k">\item</span> If the wire is a port: port number and direction (input/output/inout)
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

As with modules, the attributes can be Verilog attributes imported by the
Verilog frontend or attributes assigned by passes.

In Yosys, busses (signal vectors) are represented using a single wire object
with a width &gt; 1. So Yosys does not convert signal vectors to individual signals.
This makes some aspects of RTLIL more complex but enables Yosys to be used for
coarse grain synthesis where the cells of the target architecture operate on
entire signal vectors instead of single bit wires.

In Verilog and VHDL, busses may have arbitrary bounds, and LSB can have either
the lowest or the highest bit index. In RTLIL, bit 0 always corresponds to LSB;
however, information from the HDL frontend is preserved so that the bus will be
correctly indexed in error messages, backend output, constraint files, etc.

An RTLIL::Cell object has the following properties:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> The cell name and type
<span class="k">\item</span> A list of attributes
<span class="k">\item</span> A list of parameters (for parametric cells)
<span class="k">\item</span> Cell ports and the connections of ports to wires and constants
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

The connections of ports to wires are coded by assigning an RTLIL::SigSpec
to each cell port. The RTLIL::SigSpec data type is described in the next section.

<span class="k">\subsection</span><span class="nb">{</span>RTLIL::SigSpec<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>sec:rtlil<span class="nb">_</span>sigspec<span class="nb">}</span>

A ``signal&#39;&#39; is everything that can be applied to a cell port. I.e.

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Any constant value of arbitrary bit-width <span class="k">\\</span>
<span class="k">\null\hskip</span>1em For example: <span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>1337, 16&#39;b0000010100111001, 1&#39;b1, 1&#39;bx<span class="nb">}</span>
<span class="k">\item</span> All bits of a wire or a selection of bits from a wire <span class="k">\\</span>
<span class="k">\null\hskip</span>1em For example: <span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>mywire, mywire[24], mywire[15:8]<span class="nb">}</span>
<span class="k">\item</span> Concatenations of the above <span class="k">\\</span>
<span class="k">\null\hskip</span>1em For example: <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>|<span class="nb">{</span>16&#39;d1337, mywire[15:8]<span class="nb">}</span>|
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

The RTLIL::SigSpec data type is used to represent signals. The RTLIL::Cell
object contains one RTLIL::SigSpec for each cell port.

In addition, connections between wires are represented using a pair of
RTLIL::SigSpec objects. Such pairs are needed in different locations. Therefore
the type name RTLIL::SigSig was defined for such a pair.

<span class="k">\subsection</span><span class="nb">{</span>RTLIL::Process<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>sec:rtlil<span class="nb">_</span>process<span class="nb">}</span>

When a high-level HDL frontend processes behavioural code it splits it up into
data path logic (e.g.~the expression <span class="nb">{</span><span class="k">\tt</span> a + b<span class="nb">}</span> is replaced by the output of an
adder that takes <span class="nb">{</span><span class="k">\tt</span> a<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> b<span class="nb">}</span> as inputs) and an RTLIL::Process that models
the control logic of the behavioural code. Let&#39;s consider a simple example:

<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single,language=Verilog]
module ff<span class="nb">_</span>with<span class="nb">_</span>en<span class="nb">_</span>and<span class="nb">_</span>async<span class="nb">_</span>reset(clock, reset, enable, d, q);
input clock, reset, enable, d;
output reg q;
always @(posedge clock, posedge reset)
	if (reset)
		q &lt;= 0;
	else if (enable)
		q &lt;= d;
endmodule
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

In this example there is no data path and therefore the RTLIL::Module generated by
the frontend only contains a few RTLIL::Wire objects and an RTLIL::Process.
The RTLIL::Process in RTLIL syntax:

<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single,language=rtlil]
process <span class="s">$</span><span class="nb">proc</span><span class="s">$</span>ff<span class="nb">_</span>with<span class="nb">_</span>en<span class="nb">_</span>and<span class="nb">_</span>async<span class="nb">_</span>reset.v:4<span class="s">$</span><span class="m">1</span><span class="nb"></span>
<span class="nb">	assign </span><span class="s">$</span>0<span class="k">\q</span><span class="na">[0:0]</span> <span class="k">\q</span>
	switch <span class="k">\reset</span>
		case 1&#39;1
			assign <span class="s">$</span><span class="m">0</span><span class="nv">\q</span><span class="o">[</span><span class="m">0</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> </span><span class="m">1</span><span class="nb">&#39;</span><span class="m">0</span><span class="nb"></span>
<span class="nb">		case</span>
<span class="nb">			switch </span><span class="nv">\enable</span><span class="nb"></span>
<span class="nb">				case </span><span class="m">1</span><span class="nb">&#39;</span><span class="m">1</span><span class="nb"></span>
<span class="nb">					assign </span><span class="s">$</span>0<span class="k">\q</span><span class="na">[0:0]</span> <span class="k">\d</span>
				case
			end
	end
	sync posedge <span class="k">\clock</span>
		update <span class="k">\q</span> <span class="s">$</span><span class="m">0</span><span class="nv">\q</span><span class="o">[</span><span class="m">0</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"></span>
<span class="nb">	sync posedge </span><span class="nv">\reset</span><span class="nb"></span>
<span class="nb">		update </span><span class="nv">\q</span><span class="nb"> </span><span class="s">$</span>0<span class="k">\q</span><span class="na">[0:0]</span>
end
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

This RTLIL::Process contains two RTLIL::SyncRule objects, two RTLIL::SwitchRule
objects and five RTLIL::CaseRule objects. The wire <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>0<span class="k">\textbackslash</span><span class="nb">{}</span>q[0:0]<span class="nb">}</span>
is an automatically created wire that holds the next value of <span class="nb">{</span><span class="k">\tt</span> <span class="k">\textbackslash</span><span class="nb">{}</span>q<span class="nb">}</span>. The lines
<span class="s">$</span><span class="m">2</span><span class="nb"> </span><span class="nv">\dots</span><span class="nb"> </span><span class="m">12</span><span class="s">$</span> describe how <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>0<span class="k">\textbackslash</span><span class="nb">{}</span>q[0:0]<span class="nb">}</span> should be calculated. The
lines <span class="s">$</span><span class="m">13</span><span class="nb"> </span><span class="nv">\dots</span><span class="nb"> </span><span class="m">16</span><span class="s">$</span> describe how the value of <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>0<span class="k">\textbackslash</span><span class="nb">{}</span>q[0:0]<span class="nb">}</span> is used
to update <span class="nb">{</span><span class="k">\tt</span> <span class="k">\textbackslash</span><span class="nb">{}</span>q<span class="nb">}</span>.

An RTLIL::Process is a container for zero or more RTLIL::SyncRule objects and
exactly one RTLIL::CaseRule object, which is called the <span class="nb">{</span><span class="k">\it</span> root case<span class="nb">}</span>.

An RTLIL::SyncRule object contains an (optional) synchronization condition (signal and edge-type), zero or
more assignments (RTLIL::SigSig), and zero or more memory writes (RTLIL::MemWriteAction).
The <span class="nb">{</span><span class="k">\tt</span> always<span class="nb">}</span> synchronization condition is used to break combinatorial
loops when a latch should be inferred instead.

An RTLIL::CaseRule is a container for zero or more assignments (RTLIL::SigSig)
and zero or more RTLIL::SwitchRule objects. An RTLIL::SwitchRule objects is a
container for zero or more RTLIL::CaseRule objects.

In the above example the lines <span class="s">$</span><span class="m">2</span><span class="nb"> </span><span class="nv">\dots</span><span class="nb"> </span><span class="m">12</span><span class="s">$</span> are the root case. Here <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>0<span class="k">\textbackslash</span><span class="nb">{}</span>q[0:0]<span class="nb">}</span> is first
assigned the old value <span class="nb">{</span><span class="k">\tt</span> <span class="k">\textbackslash</span><span class="nb">{}</span>q<span class="nb">}</span> as default value (line 2). The root case
also contains an RTLIL::SwitchRule object (lines <span class="s">$</span><span class="m">3</span><span class="nb"> </span><span class="nv">\dots</span><span class="nb"> </span><span class="m">12</span><span class="s">$</span>). Such an object is very similar to the C <span class="nb">{</span><span class="k">\tt</span> switch<span class="nb">}</span>
statement as it uses a control signal (<span class="nb">{</span><span class="k">\tt</span> <span class="k">\textbackslash</span><span class="nb">{}</span>reset<span class="nb">}</span> in this case) to determine
which of its cases should be active. The RTLIL::SwitchRule object then contains one RTLIL::CaseRule
object per case. In this example there is a case<span class="k">\footnote</span><span class="nb">{</span>The
syntax <span class="nb">{</span><span class="k">\tt</span> 1&#39;1<span class="nb">}</span> in the RTLIL code specifies a constant with a length of one bit (the first ``1&#39;&#39;),
and this bit is a one (the second ``1&#39;&#39;).<span class="nb">}</span> for <span class="nb">{</span><span class="k">\tt</span> <span class="k">\textbackslash</span><span class="nb">{}</span>reset == 1<span class="nb">}</span> that causes
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>0<span class="k">\textbackslash</span><span class="nb">{}</span>q[0:0]<span class="nb">}</span> to be set (lines 4 and 5) and a default case that in turn contains a switch that
sets <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>0<span class="k">\textbackslash</span><span class="nb">{}</span>q[0:0]<span class="nb">}</span> to the value of <span class="nb">{</span><span class="k">\tt</span> <span class="k">\textbackslash</span><span class="nb">{}</span>d<span class="nb">}</span> if <span class="nb">{</span><span class="k">\tt</span>
<span class="k">\textbackslash</span><span class="nb">{}</span>enable<span class="nb">}</span> is active (lines <span class="s">$</span><span class="m">6</span><span class="nb"> </span><span class="nv">\dots</span><span class="nb"> </span><span class="m">11</span><span class="s">$</span>).

A case can specify zero or more compare values that will determine whether it matches. Each of the compare values
must be the exact same width as the control signal. When more than one compare value is specified, the case matches
if any of them matches the control signal; when zero compare values are specified, the case always matches (i.e.
it is the default case).

A switch prioritizes cases from first to last: multiple cases can match, but only the first matched case becomes
active. This normally synthesizes to a priority encoder. The <span class="nb">{</span><span class="k">\tt</span> parallel<span class="k">\_</span>case<span class="nb">}</span> attribute allows passes to assume
that no more than one case will match, and <span class="nb">{</span><span class="k">\tt</span> full<span class="k">\_</span>case<span class="nb">}</span> attribute allows passes to assume that exactly one
case will match; if these invariants are ever dynamically violated, the behavior is undefined. These attributes
are useful when an invariant invisible to the synthesizer causes the control signal to never take certain
bit patterns.

The lines <span class="s">$</span><span class="m">13</span><span class="nb"> </span><span class="nv">\dots</span><span class="nb"> </span><span class="m">16</span><span class="s">$</span>  then cause <span class="nb">{</span><span class="k">\tt</span> <span class="k">\textbackslash</span><span class="nb">{}</span>q<span class="nb">}</span> to be updated whenever there is
a positive clock edge on <span class="nb">{</span><span class="k">\tt</span> <span class="k">\textbackslash</span><span class="nb">{}</span>clock<span class="nb">}</span> or <span class="nb">{</span><span class="k">\tt</span> <span class="k">\textbackslash</span><span class="nb">{}</span>reset<span class="nb">}</span>.

In order to generate such a representation, the language frontend must be able to handle blocking
and nonblocking assignments correctly. However, the language frontend does not need to identify
the correct type of storage element for the output signal or generate multiplexers for the
decision tree. This is done by passes that work on the RTLIL representation. Therefore it is
relatively easy to substitute these steps with other algorithms that target different target
architectures or perform optimizations or other transformations on the decision trees before
further processing them.

One of the first actions performed on a design in RTLIL representation in most
synthesis scripts is identifying asynchronous resets. This is usually done using the <span class="nb">{</span><span class="k">\tt</span> proc<span class="k">\_</span>arst<span class="nb">}</span>
pass. This pass transforms the above example to the following RTLIL::Process:

<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single,language=rtlil]
process <span class="s">$</span><span class="nb">proc</span><span class="s">$</span>ff<span class="nb">_</span>with<span class="nb">_</span>en<span class="nb">_</span>and<span class="nb">_</span>async<span class="nb">_</span>reset.v:4<span class="s">$</span><span class="m">1</span><span class="nb"></span>
<span class="nb">	assign </span><span class="s">$</span>0<span class="k">\q</span><span class="na">[0:0]</span> <span class="k">\q</span>
	switch <span class="k">\enable</span>
		case 1&#39;1
			assign <span class="s">$</span><span class="m">0</span><span class="nv">\q</span><span class="o">[</span><span class="m">0</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> </span><span class="nv">\d</span><span class="nb"></span>
<span class="nb">		case</span>
<span class="nb">	end</span>
<span class="nb">	sync posedge </span><span class="nv">\clock</span><span class="nb"></span>
<span class="nb">		update </span><span class="nv">\q</span><span class="nb"> </span><span class="s">$</span>0<span class="k">\q</span><span class="na">[0:0]</span>
	sync high <span class="k">\reset</span>
		update <span class="k">\q</span> 1&#39;0
end
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

This pass has transformed the outer RTLIL::SwitchRule into a modified RTLIL::SyncRule object
for the <span class="nb">{</span><span class="k">\tt</span> <span class="k">\textbackslash</span><span class="nb">{}</span>reset<span class="nb">}</span> signal. Further processing converts the RTLIL::Process
into e.g.~a d-type flip-flop with asynchronous reset and a multiplexer for the enable signal:

<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single,language=rtlil]
cell <span class="s">$</span><span class="nb">adff </span><span class="s">$</span>procdff<span class="s">$</span><span class="m">6</span><span class="nb"></span>
<span class="nb">	parameter </span><span class="nv">\ARST</span><span class="nb">_POLARITY </span><span class="m">1</span><span class="nb">&#39;</span><span class="m">1</span><span class="nb"></span>
<span class="nb">	parameter </span><span class="nv">\ARST</span><span class="nb">_VALUE </span><span class="m">1</span><span class="nb">&#39;</span><span class="m">0</span><span class="nb"></span>
<span class="nb">	parameter </span><span class="nv">\CLK</span><span class="nb">_POLARITY </span><span class="m">1</span><span class="nb">&#39;</span><span class="m">1</span><span class="nb"></span>
<span class="nb">	parameter </span><span class="nv">\WIDTH</span><span class="nb"> </span><span class="m">1</span><span class="nb"></span>
<span class="nb">	connect </span><span class="nv">\ARST</span><span class="nb"> </span><span class="nv">\reset</span><span class="nb"></span>
<span class="nb">	connect </span><span class="nv">\CLK</span><span class="nb"> </span><span class="nv">\clock</span><span class="nb"></span>
<span class="nb">	connect </span><span class="nv">\D</span><span class="nb"> </span><span class="s">$</span>0<span class="k">\q</span><span class="na">[0:0]</span>
	connect <span class="k">\Q</span> <span class="k">\q</span>
end
cell <span class="s">$</span><span class="nb">mux </span><span class="s">$</span>procmux<span class="s">$</span><span class="m">3</span><span class="nb"></span>
<span class="nb">	parameter </span><span class="nv">\WIDTH</span><span class="nb"> </span><span class="m">1</span><span class="nb"></span>
<span class="nb">	connect </span><span class="nv">\A</span><span class="nb"> </span><span class="nv">\q</span><span class="nb"></span>
<span class="nb">	connect </span><span class="nv">\B</span><span class="nb"> </span><span class="nv">\d</span><span class="nb"></span>
<span class="nb">	connect </span><span class="nv">\S</span><span class="nb"> </span><span class="nv">\enable</span><span class="nb"></span>
<span class="nb">	connect </span><span class="nv">\Y</span><span class="nb"> </span><span class="s">$</span>0<span class="k">\q</span><span class="na">[0:0]</span>
end
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

Different combinations of passes may yield different results. Note that <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>adff<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span>
<span class="k">\$</span>mux<span class="nb">}</span> are internal cell types that still need to be mapped to cell types from the
target cell library.

Some passes refuse to operate on modules that still contain RTLIL::Process objects as the
presence of these objects in a module increases the complexity. Therefore the passes to translate
processes to a netlist of cells are usually called early in a synthesis script. The <span class="nb">{</span><span class="k">\tt</span> proc<span class="nb">}</span>
pass calls a series of other passes that together perform this conversion in a way that is suitable
for most synthesis tasks.

<span class="k">\subsection</span><span class="nb">{</span>RTLIL::Memory<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>sec:rtlil<span class="nb">_</span>memory<span class="nb">}</span>

For every array (memory) in the HDL code an RTLIL::Memory object is created. A
memory object has the following properties:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> The memory name
<span class="k">\item</span> A list of attributes
<span class="k">\item</span> The width of an addressable word
<span class="k">\item</span> The size of the memory in number of words
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

All read accesses to the memory are transformed to <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memrd<span class="nb">}</span> cells and all write accesses to
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memwr<span class="nb">}</span> cells by the language frontend. These cells consist of independent read- and write-ports
to the memory. Memory initialization is transformed to <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>meminit<span class="nb">}</span> cells by the language frontend.
The <span class="k">\B</span><span class="nb">{</span>MEMID<span class="nb">}</span> parameter on these cells is used to link them together and to the RTLIL::Memory object they belong to.

The rationale behind using separate cells for the individual ports versus
creating a large multiport memory cell right in the language frontend is that
the separate <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memrd<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memwr<span class="nb">}</span> cells can be consolidated using resource sharing.
As resource sharing is a non-trivial optimization problem where different synthesis tasks
can have different requirements it lends itself to do the optimisation in separate passes and merge
the RTLIL::Memory objects and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memrd<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memwr<span class="nb">}</span> cells to multiport memory blocks after resource sharing is completed.

The <span class="nb">{</span><span class="k">\tt</span> memory<span class="nb">}</span> pass performs this conversion and can (depending on the options passed
to it) transform the memories directly to d-type flip-flops and address logic or yield
multiport memory blocks (represented using <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mem<span class="nb">}</span> cells).

See Sec.~<span class="k">\ref</span><span class="nb">{</span>sec:memcells<span class="nb">}</span> for details about the memory cell types.

<span class="k">\section</span><span class="nb">{</span>Command Interface and Synthesis Scripts<span class="nb">}</span>

Yosys reads and processes commands from synthesis scripts, command line arguments and
an interactive command prompt. Yosys commands consist of a command name and an optional
whitespace separated list of arguments. Commands are terminated using the newline character
or a semicolon (<span class="nb">{</span><span class="k">\tt</span> ;<span class="nb">}</span>). Empty lines and lines starting with the hash sign (<span class="nb">{</span><span class="k">\tt</span> <span class="k">\#</span><span class="nb">}</span>) are ignored.
See Sec.~<span class="k">\ref</span><span class="nb">{</span>sec:typusecase<span class="nb">}</span> for an example synthesis script.

The command <span class="nb">{</span><span class="k">\tt</span> help<span class="nb">}</span> can be used to access the command reference manual.

Most commands can operate not only on the entire design but also specifically on <span class="nb">{</span><span class="k">\it</span> selected<span class="nb">}</span>
parts of the design. For example the command <span class="nb">{</span><span class="k">\tt</span> dump<span class="nb">}</span> will print all selected objects
in the current design while <span class="nb">{</span><span class="k">\tt</span> dump foobar<span class="nb">}</span> will only print the module <span class="nb">{</span><span class="k">\tt</span> foobar<span class="nb">}</span>
and <span class="nb">{</span><span class="k">\tt</span> dump *<span class="nb">}</span> will print the entire design regardless of the current selection.

The selection mechanism is very powerful. For example the command <span class="nb">{</span><span class="k">\tt</span> dump */t:<span class="k">\$</span>add
<span class="k">\%</span>x:+[A] */w:* <span class="k">\%</span>i<span class="nb">}</span> will print all wires that are connected to the <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span> port of
a <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>add<span class="nb">}</span> cell.  Detailed documentation of the select framework can be
found in the command reference for the <span class="nb">{</span><span class="k">\tt</span> select<span class="nb">}</span> command.

<span class="k">\section</span><span class="nb">{</span>Source Tree and Build System<span class="nb">}</span>

The Yosys source tree is organized into the following top-level directories:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> backends/<span class="nb">}</span> <span class="k">\\</span>
This directory contains a subdirectory for each of the backend modules.

<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> frontends/<span class="nb">}</span> <span class="k">\\</span>
This directory contains a subdirectory for each of the frontend modules.

<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> kernel/<span class="nb">}</span> <span class="k">\\</span>
This directory contains all the core functionality of Yosys. This includes the
functions and definitions for working with the RTLIL data structures (<span class="nb">{</span><span class="k">\tt</span>
rtlil.h<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> rtlil.cc<span class="nb">}</span>), the main() function (<span class="nb">{</span><span class="k">\tt</span> driver.cc<span class="nb">}</span>), the
internal framework for generating log messages (<span class="nb">{</span><span class="k">\tt</span> log.h<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> log.cc<span class="nb">}</span>),
the internal framework for registering and calling passes (<span class="nb">{</span><span class="k">\tt</span> register.h<span class="nb">}</span> and
<span class="nb">{</span><span class="k">\tt</span> register.cc<span class="nb">}</span>), some core commands that are not really passes (<span class="nb">{</span><span class="k">\tt</span>
select.cc<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> show.cc<span class="nb">}</span>, <span class="k">\dots</span>) and a couple of other small utility libraries.

<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> passes/<span class="nb">}</span> <span class="k">\\</span>
This directory contains a subdirectory for each pass or group of passes. For example as
of this writing the directory <span class="nb">{</span><span class="k">\tt</span> passes/opt/<span class="nb">}</span> contains the code for seven
passes: <span class="nb">{</span><span class="k">\tt</span> opt<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_</span>expr<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_</span>muxtree<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_</span>reduce<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_</span>rmdff<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_</span>rmunused<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> opt<span class="k">\_</span>merge<span class="nb">}</span>.

<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> techlibs/<span class="nb">}</span> <span class="k">\\</span>
This directory contains simulation models and standard implementations for the
cells from the internal cell library.

<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> tests/<span class="nb">}</span> <span class="k">\\</span>
This directory contains a couple of test cases. Most of the smaller tests are executed
automatically when <span class="nb">{</span><span class="k">\tt</span> make test<span class="nb">}</span> is called. The larger tests must be executed
manually. Most of the larger tests require downloading external HDL source code
and/or external tools. The tests range from comparing simulation results of the synthesized
design to the original sources to logic equivalence checking of entire CPU cores.

<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>sloppypar<span class="nb">}</span>
The top-level Makefile includes <span class="nb">{</span><span class="k">\tt</span> frontends/*/Makefile.inc<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> passes/*/Makefile.inc<span class="nb">}</span>
and <span class="nb">{</span><span class="k">\tt</span> backends/*/Makefile.inc<span class="nb">}</span>. So when extending Yosys it is enough to create
a new directory in <span class="nb">{</span><span class="k">\tt</span> frontends/<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> passes/<span class="nb">}</span> or <span class="nb">{</span><span class="k">\tt</span> backends/<span class="nb">}</span> with your sources
and a <span class="nb">{</span><span class="k">\tt</span> Makefile.inc<span class="nb">}</span>. The Yosys kernel automatically detects all commands linked with
Yosys. So it is not needed to add additional commands to a central list of commands.
<span class="k">\end</span><span class="nb">{</span>sloppypar<span class="nb">}</span>

Good starting points for reading example source code to learn how to write passes
are <span class="nb">{</span><span class="k">\tt</span> passes/opt/opt<span class="k">\_</span>rmdff.cc<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> passes/opt/opt<span class="k">\_</span>merge.cc<span class="nb">}</span>.

See the top-level README file for a quick <span class="nb">{</span><span class="k">\it</span> Getting Started<span class="nb">}</span> guide and build
instructions. The Yosys build is based solely on Makefiles.

Users of the Qt Creator IDE can generate a QT Creator project file using <span class="nb">{</span><span class="k">\tt</span>
make qtcreator<span class="nb">}</span>. Users of the Eclipse IDE can use the ``Makefile Project with
Existing Code&#39;&#39; project type in the Eclipse ``New Project&#39;&#39; dialog (only
available after the CDT plugin has been installed) to create an Eclipse project
in order to programming extensions to Yosys or just browse the Yosys code base.
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