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</pre></td>
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.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */</style><div class="highlight"><pre><span></span><span class="k">\chapter</span><span class="nb">{</span>Internal Cell Library<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>chapter:celllib<span class="nb">}</span>

Most of the passes in Yosys operate on netlists, i.e.~they only care about the RTLIL::Wire and RTLIL::Cell
objects in an RTLIL::Module. This chapter discusses the cell types used by Yosys to represent a behavioural
design internally.

This chapter is split in two parts. In the first part the internal RTL cells are covered. These cells
are used to represent the design on a coarse grain level. Like in the original HDL code on this level the
cells operate on vectors of signals and complex cells like adders exist. In the second part the internal
gate cells are covered. These cells are used to represent the design on a fine-grain gate-level. All cells
from this category operate on single bit signals.

<span class="k">\section</span><span class="nb">{</span>RTL Cells<span class="nb">}</span>

Most of the RTL cells closely resemble the operators available in HDLs such as
Verilog or VHDL. Therefore Verilog operators are used in the following sections
to define the behaviour of the RTL cells.

Note that all RTL cells have parameters indicating the size of inputs and outputs. When
passes modify RTL cells they must always keep the values of these parameters in sync with
the size of the signals connected to the inputs and outputs.

Simulation models for the RTL cells can be found in the file <span class="nb">{</span><span class="k">\tt</span> techlibs/common/simlib.v<span class="nb">}</span> in the Yosys
source tree.

<span class="k">\subsection</span><span class="nb">{</span>Unary Operators<span class="nb">}</span>

All unary RTL cells have one input port <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span> and one output port <span class="k">\B</span><span class="nb">{</span>Y<span class="nb">}</span>. They also
have the following parameters:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>A<span class="k">\_</span>SIGNED<span class="nb">}</span> <span class="k">\\</span>
Set to a non-zero value if the input <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span> is signed and therefore should be sign-extended
when needed.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>A<span class="k">\_</span>WIDTH<span class="nb">}</span> <span class="k">\\</span>
The width of the input port <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span>.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>Y<span class="k">\_</span>WIDTH<span class="nb">}</span> <span class="k">\\</span>
The width of the output port <span class="k">\B</span><span class="nb">{</span>Y<span class="nb">}</span>.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

Table~<span class="k">\ref</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>unary<span class="nb">}</span> lists all cells for unary RTL operators.

<span class="k">\begin</span><span class="nb">{</span>table<span class="nb">}</span>[t!]
<span class="k">\hfil</span>
<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}{</span>ll<span class="nb">}</span>
Verilog <span class="nb">&amp;</span> Cell Type <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y =  ~A ; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>not<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y =  +A ; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>pos<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y =  -A ; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>neg<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y =  <span class="nb">&amp;</span>A ; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>and<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y =  |A ; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>or<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y =  <span class="nb">^</span>A ; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>xor<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = ~<span class="nb">^</span>A ; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>xnor<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y =  |A ; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>bool<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y =  !A ; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>logic<span class="k">\_</span>not<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span>Cell types for unary operators with their corresponding Verilog expressions.<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>unary<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>table<span class="nb">}</span>

Note that <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>or<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>bool<span class="nb">}</span> actually represent the same
logic function. But the HDL frontends generate them in different situations. A
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>or<span class="nb">}</span> cell is generated when the prefix <span class="nb">{</span><span class="k">\tt</span> |<span class="nb">}</span> operator is being used. A
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>bool<span class="nb">}</span> cell is generated when a bit vector is used as a condition in
an <span class="nb">{</span><span class="k">\tt</span> if<span class="nb">}</span>-statement or <span class="nb">{</span><span class="k">\tt</span> ?:<span class="nb">}</span>-expression.

<span class="k">\subsection</span><span class="nb">{</span>Binary Operators<span class="nb">}</span>

All binary RTL cells have two input ports <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span> and <span class="k">\B</span><span class="nb">{</span>B<span class="nb">}</span> and one output port <span class="k">\B</span><span class="nb">{</span>Y<span class="nb">}</span>. They
also have the following parameters:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>A<span class="k">\_</span>SIGNED<span class="nb">}</span> <span class="k">\\</span>
Set to a non-zero value if the input <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span> is signed and therefore should be sign-extended
when needed.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>A<span class="k">\_</span>WIDTH<span class="nb">}</span> <span class="k">\\</span>
The width of the input port <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span>.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>B<span class="k">\_</span>SIGNED<span class="nb">}</span> <span class="k">\\</span>
Set to a non-zero value if the input <span class="k">\B</span><span class="nb">{</span>B<span class="nb">}</span> is signed and therefore should be sign-extended
when needed.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>B<span class="k">\_</span>WIDTH<span class="nb">}</span> <span class="k">\\</span>
The width of the input port <span class="k">\B</span><span class="nb">{</span>B<span class="nb">}</span>.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>Y<span class="k">\_</span>WIDTH<span class="nb">}</span> <span class="k">\\</span>
The width of the output port <span class="k">\B</span><span class="nb">{</span>Y<span class="nb">}</span>.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

Table~<span class="k">\ref</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>binary<span class="nb">}</span> lists all cells for binary RTL operators.

<span class="k">\subsection</span><span class="nb">{</span>Multiplexers<span class="nb">}</span>

Multiplexers are generated by the Verilog HDL frontend for <span class="nb">{</span><span class="k">\tt</span>
?:<span class="nb">}</span>-expressions. Multiplexers are also generated by the <span class="nb">{</span><span class="k">\tt</span> proc<span class="nb">}</span> pass to map the decision trees
from RTLIL::Process objects to logic.

The simplest multiplexer cell type is <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mux<span class="nb">}</span>. Cells of this type have a <span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> parameter
and data inputs <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span> and <span class="k">\B</span><span class="nb">{</span>B<span class="nb">}</span> and a data output <span class="k">\B</span><span class="nb">{</span>Y<span class="nb">}</span>, all of the specified width. This cell also
has a single bit control input <span class="k">\B</span><span class="nb">{</span>S<span class="nb">}</span>. If <span class="k">\B</span><span class="nb">{</span>S<span class="nb">}</span> is 0 the value from the <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span> input is sent to
the output, if it is 1 the value from the <span class="k">\B</span><span class="nb">{</span>B<span class="nb">}</span> input is sent to the output. So the <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mux<span class="nb">}</span>
cell implements the function <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = S ? B : A;.

The <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>pmux<span class="nb">}</span> cell is used to multiplex between many inputs using a one-hot select signal. Cells
of this type have a <span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> and a <span class="k">\B</span><span class="nb">{</span>S<span class="k">\_</span>WIDTH<span class="nb">}</span> parameter and inputs <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span>, <span class="k">\B</span><span class="nb">{</span>B<span class="nb">}</span>, and <span class="k">\B</span><span class="nb">{</span>S<span class="nb">}</span> and
an output <span class="k">\B</span><span class="nb">{</span>Y<span class="nb">}</span>. The <span class="k">\B</span><span class="nb">{</span>S<span class="nb">}</span> input is <span class="k">\B</span><span class="nb">{</span>S<span class="k">\_</span>WIDTH<span class="nb">}</span> bits wide. The <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span> input and the output are both
<span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> bits wide and the <span class="k">\B</span><span class="nb">{</span>B<span class="nb">}</span> input is <span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span>*<span class="k">\B</span><span class="nb">{</span>S<span class="k">\_</span>WIDTH<span class="nb">}</span> bits wide. When all bits of
<span class="k">\B</span><span class="nb">{</span>S<span class="nb">}</span> are zero, the value from <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span> input is sent to the output. If the <span class="s">$</span><span class="nb">n</span><span class="s">$</span>&#39;th bit from <span class="k">\B</span><span class="nb">{</span>S<span class="nb">}</span> is
set, the value <span class="s">$</span><span class="nb">n</span><span class="s">$</span>&#39;th <span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> bits wide slice of the <span class="k">\B</span><span class="nb">{</span>B<span class="nb">}</span> input is sent to the output. When more
than one bit from <span class="k">\B</span><span class="nb">{</span>S<span class="nb">}</span> is set the output is undefined. Cells of this type are used to model
``parallel cases&#39;&#39; (defined by using the <span class="nb">{</span><span class="k">\tt</span> parallel<span class="k">\_</span>case<span class="nb">}</span> attribute or detected by
an optimization).

Behavioural code with cascaded <span class="nb">{</span><span class="k">\tt</span> if-then-else<span class="nb">}</span>- and <span class="nb">{</span><span class="k">\tt</span> case<span class="nb">}</span>-statements
usually results in trees of multiplexer cells. Many passes (from various
optimizations to FSM extraction) heavily depend on these multiplexer trees to
understand dependencies between signals. Therefore optimizations should not
break these multiplexer trees (e.g.~by replacing a multiplexer between a
calculated signal and a constant zero with an <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>and<span class="nb">}</span> gate).

<span class="k">\begin</span><span class="nb">{</span>table<span class="nb">}</span>[t!]
<span class="k">\hfil</span>
<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}</span>[t]<span class="nb">{</span>ll<span class="nb">}</span>
Verilog <span class="nb">&amp;</span> Cell Type <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A  <span class="nb">&amp;</span> B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>and<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A  | B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>or<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A  <span class="nb">^</span> B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>xor<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A ~<span class="nb">^</span> B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>xnor<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A &lt;&lt; B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>shl<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A &gt;&gt; B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>shr<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A &lt;&lt;&lt; B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>sshl<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A &gt;&gt;&gt; B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>sshr<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A <span class="nb">&amp;&amp;</span> B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>logic<span class="k">\_</span>and<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A || B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>logic<span class="k">\_</span>or<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A === B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>eqx<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A !== B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>nex<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\hfil</span>
<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}</span>[t]<span class="nb">{</span>ll<span class="nb">}</span>
Verilog <span class="nb">&amp;</span> Cell Type <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A &lt;  B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>lt<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A &lt;= B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>le<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A == B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>eq<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A != B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>ne<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A &gt;= B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>ge<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A &gt;  B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>gt<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A  + B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>add<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A  - B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>sub<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A  * B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mul<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A  / B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>div<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A  <span class="c">% B; &amp; {\tt \$mod} \\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A ** B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>pow<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span>Cell types for binary operators with their corresponding Verilog expressions.<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>binary<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>table<span class="nb">}</span>

<span class="k">\subsection</span><span class="nb">{</span>Registers<span class="nb">}</span>

D-Type Flip-Flops are represented by <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dff<span class="nb">}</span> cells. These cells have a clock port <span class="k">\B</span><span class="nb">{</span>CLK<span class="nb">}</span>,
an input port <span class="k">\B</span><span class="nb">{</span>D<span class="nb">}</span> and an output port <span class="k">\B</span><span class="nb">{</span>Q<span class="nb">}</span>. The following parameters are available for <span class="k">\$</span>dff
cells:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> <span class="k">\\</span>
The width of input <span class="k">\B</span><span class="nb">{</span>D<span class="nb">}</span> and output <span class="k">\B</span><span class="nb">{</span>Q<span class="nb">}</span>.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>CLK<span class="k">\_</span>POLARITY<span class="nb">}</span> <span class="k">\\</span>
Clock is active on the positive edge if this parameter has the value <span class="nb">{</span><span class="k">\tt</span> 1&#39;b1<span class="nb">}</span> and on the negative
edge if this parameter is <span class="nb">{</span><span class="k">\tt</span> 1&#39;b0<span class="nb">}</span>.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

D-Type Flip-Flops with asynchronous resets are represented by <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>adff<span class="nb">}</span> cells. As the <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dff<span class="nb">}</span>
cells they have <span class="k">\B</span><span class="nb">{</span>CLK<span class="nb">}</span>, <span class="k">\B</span><span class="nb">{</span>D<span class="nb">}</span> and <span class="k">\B</span><span class="nb">{</span>Q<span class="nb">}</span> ports. In addition they also have a single-bit <span class="k">\B</span><span class="nb">{</span>ARST<span class="nb">}</span>
input port for the reset pin and the following additional two parameters:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>ARST<span class="k">\_</span>POLARITY<span class="nb">}</span> <span class="k">\\</span>
The asynchronous reset is high-active if this parameter has the value <span class="nb">{</span><span class="k">\tt</span> 1&#39;b1<span class="nb">}</span> and low-active
if this parameter is <span class="nb">{</span><span class="k">\tt</span> 1&#39;b0<span class="nb">}</span>.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>ARST<span class="k">\_</span>VALUE<span class="nb">}</span> <span class="k">\\</span>
The state of <span class="k">\B</span><span class="nb">{</span>Q<span class="nb">}</span> will be set to this value when the reset is active.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

Note that the <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>adff<span class="nb">}</span> cell can only be used when the reset value is constant.

<span class="k">\begin</span><span class="nb">{</span>sloppypar<span class="nb">}</span>
Usually these cells are generated by the <span class="nb">{</span><span class="k">\tt</span> proc<span class="nb">}</span> pass using the information
in the designs RTLIL::Process objects.
<span class="k">\end</span><span class="nb">{</span>sloppypar<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>fixme<span class="nb">}</span>
Add information about <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>sr<span class="nb">}</span> cells (set-reset flip-flops) and d-type latches.
<span class="k">\end</span><span class="nb">{</span>fixme<span class="nb">}</span>

<span class="k">\subsection</span><span class="nb">{</span>Memories<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>sec:memcells<span class="nb">}</span>

Memories are either represented using RTLIL::Memory objects and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memrd<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memwr<span class="nb">}</span> cells
or simply by using <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mem<span class="nb">}</span> cells.

In the first alternative the RTLIL::Memory objects hold the general metadata for the memory (bit width,
size in number of words, etc.) and for each port a <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memrd<span class="nb">}</span> (read port) or <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memwr<span class="nb">}</span> (write port)
cell is created. Having individual cells for read and write ports has the advantage that they can be
consolidated using resource sharing passes. In some cases this drastically reduces the number of required
ports on the memory cell.

The <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memrd<span class="nb">}</span> cells have a clock input <span class="k">\B</span><span class="nb">{</span>CLK<span class="nb">}</span>, an enable input <span class="k">\B</span><span class="nb">{</span>EN<span class="nb">}</span>, an
address input <span class="k">\B</span><span class="nb">{</span>ADDR<span class="nb">}</span>, and a data output <span class="k">\B</span><span class="nb">{</span>DATA<span class="nb">}</span>. They also have the
following parameters:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>MEMID<span class="nb">}</span> <span class="k">\\</span>
The name of the RTLIL::Memory object that is associated with this read port.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>ABITS<span class="nb">}</span> <span class="k">\\</span>
The number of address bits (width of the <span class="k">\B</span><span class="nb">{</span>ADDR<span class="nb">}</span> input port).

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> <span class="k">\\</span>
The number of data bits (width of the <span class="k">\B</span><span class="nb">{</span>DATA<span class="nb">}</span> output port).

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>CLK<span class="k">\_</span>ENABLE<span class="nb">}</span> <span class="k">\\</span>
When this parameter is non-zero, the clock is used. Otherwise this read port is asynchronous and
the <span class="k">\B</span><span class="nb">{</span>CLK<span class="nb">}</span> input is not used.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>CLK<span class="k">\_</span>POLARITY<span class="nb">}</span> <span class="k">\\</span>
Clock is active on the positive edge if this parameter has the value <span class="nb">{</span><span class="k">\tt</span> 1&#39;b1<span class="nb">}</span> and on the negative
edge if this parameter is <span class="nb">{</span><span class="k">\tt</span> 1&#39;b0<span class="nb">}</span>.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>TRANSPARENT<span class="nb">}</span> <span class="k">\\</span>
If this parameter is set to <span class="nb">{</span><span class="k">\tt</span> 1&#39;b1<span class="nb">}</span>, a read and write to the same address in the same cycle will
return the new value. Otherwise the old value is returned.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

The <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memwr<span class="nb">}</span> cells have a clock input <span class="k">\B</span><span class="nb">{</span>CLK<span class="nb">}</span>, an enable input <span class="k">\B</span><span class="nb">{</span>EN<span class="nb">}</span> (one
enable bit for each data bit), an address input <span class="k">\B</span><span class="nb">{</span>ADDR<span class="nb">}</span> and a data input
<span class="k">\B</span><span class="nb">{</span>DATA<span class="nb">}</span>. They also have the following parameters:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>MEMID<span class="nb">}</span> <span class="k">\\</span>
The name of the RTLIL::Memory object that is associated with this read port.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>ABITS<span class="nb">}</span> <span class="k">\\</span>
The number of address bits (width of the <span class="k">\B</span><span class="nb">{</span>ADDR<span class="nb">}</span> input port).

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> <span class="k">\\</span>
The number of data bits (width of the <span class="k">\B</span><span class="nb">{</span>DATA<span class="nb">}</span> output port).

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>CLK<span class="k">\_</span>ENABLE<span class="nb">}</span> <span class="k">\\</span>
When this parameter is non-zero, the clock is used. Otherwise this read port is asynchronous and
the <span class="k">\B</span><span class="nb">{</span>CLK<span class="nb">}</span> input is not used.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>CLK<span class="k">\_</span>POLARITY<span class="nb">}</span> <span class="k">\\</span>
Clock is active on positive edge if this parameter has the value <span class="nb">{</span><span class="k">\tt</span> 1&#39;b1<span class="nb">}</span> and on the negative
edge if this parameter is <span class="nb">{</span><span class="k">\tt</span> 1&#39;b0<span class="nb">}</span>.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>PRIORITY<span class="nb">}</span> <span class="k">\\</span>
The cell with the higher integer value in this parameter wins a write conflict.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

The HDL frontend models a memory using RTLIL::Memory objects and asynchronous
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memrd<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memwr<span class="nb">}</span> cells. The <span class="nb">{</span><span class="k">\tt</span> memory<span class="nb">}</span> pass (i.e.~its various sub-passes) migrates
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dff<span class="nb">}</span> cells into the <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memrd<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memwr<span class="nb">}</span> cells making them synchronous, then
converts them to a single <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mem<span class="nb">}</span> cell and (optionally) maps this cell type
to <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dff<span class="nb">}</span> cells for the individual words and multiplexer-based address decoders for the read and
write interfaces. When the last step is disabled or not possible, a <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mem<span class="nb">}</span> cell is left in the design.

The <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mem<span class="nb">}</span> cell provides the following parameters:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>MEMID<span class="nb">}</span> <span class="k">\\</span>
The name of the original RTLIL::Memory object that became this <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mem<span class="nb">}</span> cell.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>SIZE<span class="nb">}</span> <span class="k">\\</span>
The number of words in the memory.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>ABITS<span class="nb">}</span> <span class="k">\\</span>
The number of address bits.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> <span class="k">\\</span>
The number of data bits per word.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS<span class="nb">}</span> <span class="k">\\</span>
The number of read ports on this memory cell.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>CLK<span class="k">\_</span>ENABLE<span class="nb">}</span> <span class="k">\\</span>
This parameter is <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, containing a clock enable bit for each read port.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>CLK<span class="k">\_</span>POLARITY<span class="nb">}</span> <span class="k">\\</span>
This parameter is <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, containing a clock polarity bit for each read port.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>TRANSPARENT<span class="nb">}</span> <span class="k">\\</span>
This parameter is <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, containing a transparent bit for each read port.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>PORTS<span class="nb">}</span> <span class="k">\\</span>
The number of write ports on this memory cell.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>CLK<span class="k">\_</span>ENABLE<span class="nb">}</span> <span class="k">\\</span>
This parameter is <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, containing a clock enable bit for each write port.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>CLK<span class="k">\_</span>POLARITY<span class="nb">}</span> <span class="k">\\</span>
This parameter is <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, containing a clock polarity bit for each write port.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

The <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mem<span class="nb">}</span> cell has the following ports:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>CLK<span class="nb">}</span> <span class="k">\\</span>
This input is <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, containing all clock signals for the read ports.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>EN<span class="nb">}</span> <span class="k">\\</span>
This input is <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, containing all enable signals for the read ports.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>ADDR<span class="nb">}</span> <span class="k">\\</span>
This input is <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS<span class="nb">}</span>*<span class="k">\B</span><span class="nb">{</span>ABITS<span class="nb">}</span> bits wide, containing all address signals for the read ports.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>DATA<span class="nb">}</span> <span class="k">\\</span>
This input is <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS<span class="nb">}</span>*<span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> bits wide, containing all data signals for the read ports.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>CLK<span class="nb">}</span> <span class="k">\\</span>
This input is <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, containing all clock signals for the write ports.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>EN<span class="nb">}</span> <span class="k">\\</span>
This input is <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>PORTS<span class="nb">}</span>*<span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> bits wide, containing all enable signals for the write ports.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>ADDR<span class="nb">}</span> <span class="k">\\</span>
This input is <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>PORTS<span class="nb">}</span>*<span class="k">\B</span><span class="nb">{</span>ABITS<span class="nb">}</span> bits wide, containing all address signals for the write ports.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>DATA<span class="nb">}</span> <span class="k">\\</span>
This input is <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>PORTS<span class="nb">}</span>*<span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> bits wide, containing all data signals for the write ports.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

The <span class="nb">{</span><span class="k">\tt</span> techmap<span class="nb">}</span> pass can be used to manually map <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mem<span class="nb">}</span> cells to
specialized memory cells on the target architecture, such as block ram resources
on an FPGA.

<span class="k">\subsection</span><span class="nb">{</span>Finite State Machines<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>fixme<span class="nb">}</span>
Add a brief description of the <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>fsm<span class="nb">}</span> cell type.
<span class="k">\end</span><span class="nb">{</span>fixme<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>Gates<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>sec:celllib<span class="nb">_</span>gates<span class="nb">}</span>

For gate level logic networks, fixed function single bit cells are used that do
not provide any parameters.

Simulation models for these cells can be found in the file <span class="nb">{</span><span class="k">\tt</span> techlibs/common/simcells.v<span class="nb">}</span> in the Yosys
source tree.

<span class="k">\begin</span><span class="nb">{</span>table<span class="nb">}</span>[t]
<span class="k">\hfil</span>
<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}</span>[t]<span class="nb">{</span>ll<span class="nb">}</span>
Verilog <span class="nb">&amp;</span> Cell Type <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = ~A;    <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>NOT<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A <span class="nb">&amp;</span> B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>AND<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A | B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>OR<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A <span class="nb">^</span> B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>XOR<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = S ? B : A; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>MUX<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; always @(negedge C) Q &lt;= D; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>N<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; always @(posedge C) Q &lt;= D; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>P<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\hfil</span>
<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}</span>[t]<span class="nb">{</span>llll<span class="nb">}</span>
<span class="s">$</span><span class="nb">ClkEdge</span><span class="s">$</span> <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">RstLvl</span><span class="s">$</span> <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">RstVal</span><span class="s">$</span> <span class="nb">&amp;</span> Cell Type <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>NN0<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>NN1<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>NP0<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>NP1<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>PN0<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>PN1<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>PP0<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>PP1<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span>Cell types for gate level logic networks<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>gates<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>table<span class="nb">}</span>

Table~<span class="k">\ref</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>gates<span class="nb">}</span> lists all cell types used for gate level logic. The cell types
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>NOT<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>AND<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>OR<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>XOR<span class="k">\_</span><span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>MUX<span class="k">\_</span><span class="nb">}</span>
are used to model combinatorial logic. The cell types <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>N<span class="k">\_</span><span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>P<span class="k">\_</span><span class="nb">}</span>
represent d-type flip-flops.

The cell types <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>NN0<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>NN1<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>NP0<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>NP1<span class="k">\_</span><span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>PN0<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>PN1<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>PP0<span class="k">\_</span><span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>PP1<span class="k">\_</span><span class="nb">}</span> implement
d-type flip-flops with asynchronous resets. The values in the table for these cell types relate to the
following Verilog code template, where <span class="k">\lstinline</span><span class="na">[mathescape,language=Verilog]</span>;<span class="s">$</span><span class="nb">RstEdge</span><span class="s">$</span>; is <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge;
if <span class="k">\lstinline</span><span class="na">[mathescape,language=Verilog]</span>;<span class="s">$</span><span class="nb">RstLvl</span><span class="s">$</span>; if <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1;, and <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge;
otherwise.

<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[mathescape,language=Verilog]
	always @(<span class="s">$</span><span class="nb">ClkEdge</span><span class="s">$</span> C, <span class="s">$</span><span class="nb">RstEdge</span><span class="s">$</span> R)
		if (R == <span class="s">$</span><span class="nb">RstLvl</span><span class="s">$</span>)
			Q &lt;= <span class="s">$</span><span class="nb">RstVa</span><span class="s">$</span>l;
		else
			Q &lt;= D;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

In most cases gate level logic networks are created from RTL networks using the <span class="nb">{</span><span class="k">\tt</span> techmap<span class="nb">}</span> pass. The flip-flop cells
from the gate level logic network can be mapped to physical flip-flop cells from a Liberty file using the <span class="nb">{</span><span class="k">\tt</span> dfflibmap<span class="nb">}</span>
pass. The combinatorial logic cells can be mapped to physical cells from a Liberty file via ABC <span class="k">\citeweblink</span><span class="nb">{</span>ABC<span class="nb">}</span>
using the <span class="nb">{</span><span class="k">\tt</span> abc<span class="nb">}</span> pass.

<span class="k">\begin</span><span class="nb">{</span>fixme<span class="nb">}</span>
Add information about <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>assert<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>assume<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>live<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>fair<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>cover<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>equiv<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>initstate<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>anyconst<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>anyseq<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>allconst<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>allseq<span class="nb">}</span> cells.
<span class="k">\end</span><span class="nb">{</span>fixme<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>fixme<span class="nb">}</span>
Add information about <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>slice<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>concat<span class="nb">}</span> cells.
<span class="k">\end</span><span class="nb">{</span>fixme<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>fixme<span class="nb">}</span>
Add information about <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>lut<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>sop<span class="nb">}</span> cells.
<span class="k">\end</span><span class="nb">{</span>fixme<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>fixme<span class="nb">}</span>
Add information about <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>alu<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>macc<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>fa<span class="nb">}</span>, and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>lcu<span class="nb">}</span> cells.
<span class="k">\end</span><span class="nb">{</span>fixme<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>fixme<span class="nb">}</span>
Add information about <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>ff<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>FF<span class="k">\_</span><span class="nb">}</span> cells.
<span class="k">\end</span><span class="nb">{</span>fixme<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>fixme<span class="nb">}</span>
Add information about <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dffe<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dffsr<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dlatch<span class="nb">}</span>, and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dlatchsr<span class="nb">}</span> cells.
<span class="k">\end</span><span class="nb">{</span>fixme<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>fixme<span class="nb">}</span>
Add information about <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFE<span class="k">\_</span>??<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSR<span class="k">\_</span>???<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DLATCH<span class="k">\_</span>?<span class="k">\_</span><span class="nb">}</span>, and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DLATCHSR<span class="k">\_</span>???<span class="k">\_</span><span class="nb">}</span> cells.
<span class="k">\end</span><span class="nb">{</span>fixme<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>fixme<span class="nb">}</span>
Add information about <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>NAND<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>NOR<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>XNOR<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>ANDNOT<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>ORNOT<span class="k">\_</span><span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>AOI3<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>OAI3<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>AOI4<span class="k">\_</span><span class="nb">}</span>, and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>OAI4<span class="k">\_</span><span class="nb">}</span> cells.
<span class="k">\end</span><span class="nb">{</span>fixme<span class="nb">}</span>
</pre></div>
</code></pre></td></tr></table>
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