module syn_reset (clk,reset,a,c); input clk; input reset; input a; output c; wire clk; wire reset; wire a; reg c; always @ (posedge clk ) if ( reset == 1'b1) begin c <= 0; end else begin c <= a; end endmodule eed' href='http://git.panaceas.org/cgit/iCE40/nextpnr/atom/3rdparty/googletest/googlemock/include/gmock/gmock-generated-actions.h?h=master' type='application/atom+xml'/>
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