/* * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ // ============================================================================ // LCU (* techmap_celltype = "$lcu" *) module _80_xilinx_lcu (P, G, CI, CO); parameter WIDTH = 2; (* force_downto *) input [WIDTH-1:0] P, G; input CI; (* force_downto *) output [WIDTH-1:0] CO; wire _TECHMAP_FAIL_ = WIDTH <= 2; genvar i; generate if (`LUT_SIZE == 4) begin (* force_downto *) wire [WIDTH-1:0] C = {CO, CI}; (* force_downto *) wire [WIDTH-1:0] S = P & ~G; generate for (i = 0; i < WIDTH; i = i + 1) begin:slice MUXCY muxcy ( .CI(C[i]), .DI(G[i]), .S(S[i]), .O(CO[i]) ); end endgenerate end else begin localparam CARRY4_COUNT = (WIDTH + 3) / 4; localparam MAX_WIDTH = CARRY4_COUNT * 4; localparam PAD_WIDTH = MAX_WIDTH - WIDTH; (* force_downto *) wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, P & ~G}; (* force_downto *) wire [MAX_WIDTH-1:0] GG = {{PAD_WIDTH{1'b0}}, G}; (* force_downto *) wire [MAX_WIDTH-1:0] C; assign CO = C; generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice if (i == 0) begin CARRY4 carry4 ( .CYINIT(CI), .CI (1'd0), .DI (GG[i*4 +: 4]), .S (S [i*4 +: 4]), .CO (C [i*4 +: 4]), ); end else begin CARRY4 carry4 ( .CYINIT(1'd0), .CI (C [i*4 - 1]), .DI (GG[i*4 +: 4]), .S (S [i*4 +: 4]), .CO (C [i*4 +: 4]), ); end end endgenerate end endgenerate endmodule // ============================================================================ // ALU (* techmap_celltype = "$alu" *) module _80_xilinx_alu (A, B, CI, BI, X, Y, CO); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 1; parameter B_WIDTH = 1; parameter Y_WIDTH = 1; parameter _TECHMAP_CONSTVAL_CI_ = 0; parameter _TECHMAP_CONSTMSK_CI_ = 0; (* force_downto *) input [A_WIDTH-1:0] A; (* force_downto *) input [B_WIDTH-1:0] B; (* force_downto *) output [Y_WIDTH-1:0] X, Y; input CI, BI; (* force_downto *) output [Y_WIDTH-1:0] CO; wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; (* force_downto *) wire [Y_WIDTH-1:0] A_buf, B_buf; \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); (* force_downto *) wire [Y_WIDTH-1:0] AA = A_buf; (* force_downto *) wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; genvar i; generate if (`LUT_SIZE == 4) begin (* force_downto *) wire [Y_WIDTH-1:0] C = {CO, CI}; (* force_downto *) wire [Y_WIDTH-1:0] S = {AA ^ BB}; genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice MUXCY muxcy ( .CI(C[i]), .DI(AA[i]), .S(S[i]), .O(CO[i]) ); XORCY xorcy ( .CI(C[i]), .LI(S[i]), .O(Y[i]) ); end endgenerate end else begin localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4; localparam MAX_WIDTH = CARRY4_COUNT * 4; localparam PAD_WIDTH = MAX_WIDTH - Y_WIDTH; (* force_downto *) wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, AA ^ BB}; (* force_downto *) wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA}; (* force_downto *) wire [MAX_WIDTH-1:0] O; (* force_downto *) wire [MAX_WIDTH-1:0] C; assign Y = O, CO = C; genvar i; generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice if (i == 0) begin CARRY4 carry4 ( .CYINIT(CI), .CI (1'd0), .DI (DI[i*4 +: 4]), .S (S [i*4 +: 4]), .O (O [i*4 +: 4]), .CO (C [i*4 +: 4]) ); end else begin CARRY4 carry4 ( .CYINIT(1'd0), .CI (C [i*4 - 1]), .DI (DI[i*4 +: 4]), .S (S [i*4 +: 4]), .O (O [i*4 +: 4]), .CO (C [i*4 +: 4]) ); end end endgenerate end endgenerate assign X = S; endmodule d='n9' href='#n9'>9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177