read_verilog test_arith.v synth_ice40 rename test gate read_verilog test_arith.v rename test gold miter -equiv -flatten -make_outputs gold gate miter sat -verify -prove trigger 0 -show-ports miter synth_ice40 -top gate read_verilog test_arith.v rename test gold miter -equiv -flatten -make_outputs gold gate miter sat -verify -prove trigger 0 -show-ports miter title='iCE40/yosys Git repository'/>
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path: root/techlibs/xilinx/lutrams.txt
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