module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); parameter [63:0]INIT = 64'bx; input CLK1; input [3:0] A1ADDR; output [3:0] A1DATA; input [3:0] B1ADDR; input [3:0] B1DATA; input B1EN; EG_LOGIC_DRAM16X4 #( `include "lutram_init_16x4.vh" ) _TECHMAP_REPLACE_ ( .di(B1DATA), .waddr(B1ADDR), .wclk(CLK1), .we(B1EN), .raddr(A1ADDR), .do(A1DATA) ); endmodule ='vcs-git' href='ssh://git@git.panaceas.org/git/iCE40/yosys' title='iCE40/yosys Git repository'/>
aboutsummaryrefslogtreecommitdiffstats
path: root/tests/tools/autotest.mk
blob: e0f2bcdc1b6e6d47f58c895dcaa2bd111c27a090 (plain) 
1
2
3
4
5
6
7
8
9
10
11
12
13