// // yosys -- Yosys Open SYnthesis Suite // // Copyright (C) 2018 Serge Bazanski // // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. // // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. // /// Protobuf definition of Yosys RTLIL dump/restore format for RTL designs. syntax = "proto3"; package yosys.pb; // Port direction. enum Direction { DIRECTION_INVALID = 0; DIRECTION_INPUT = 1; DIRECTION_OUTPUT = 2; DIRECTION_INOUT = 3; } // A freeform parameter/attribute value. message Parameter { oneof value { int64 int = 1; string str = 2; } } // A signal in the design - either a unique identifier for one, or a constant // driver (low or high). message Signal { // A constant signal driver in the design. enum ConstantDriver { CONSTANT_DRIVER_INVALID = 0; CONSTANT_DRIVER_LOW = 1; CONSTANT_DRIVER_HIGH = 2; CONSTANT_DRIVER_Z = 3; CONSTANT_DRIVER_X = 4; } oneof type { // Signal uniquely identified by ID number. int64 id = 1; // Constant driver. ConstantDriver constant = 2; } } // A vector of signals. message BitVector { repeated Signal signal = 1; } // A netlist module. message Module { // Freeform attributes. map attribute = 1; // Named ports in this module. message Port { Direction direction = 1; BitVector bits = 2; } map port = 2; // Named cells in this module. message Cell { // Set to true when the name of this cell is automatically created and // likely not of interest for a regular user. bool hide_name = 1; string type = 2; // Set if this module has an AIG model available. string model = 3; // Freeform parameters. map parameter = 4; // Freeform attributes. map attribute = 5; /// Ports of the cell. // Direction of the port, if interface is known. map port_direction = 6; // Connection of named port to signal(s). map connection = 7; } map cell = 3; // Nets in this module. message Netname { // Set to true when the name of this net is automatically created and // likely not of interest for a regular user. bool hide_name = 1; // Signal(s) that make up this net. BitVector bits = 2; // Freeform attributes. map attributes = 3; } repeated Netname netname = 4; } // And-Inverter-Graph model. message Model { message Node { // Type of AIG node - or, what its' value is. enum Type { TYPE_INVALID = 0; // The node's value is the value of the specified input port bit. TYPE_PORT = 1; // The node's value is the inverted value of the specified input // port bit. TYPE_NPORT = 2; // The node's value is the ANDed value of specified nodes. TYPE_AND = 3; // The node's value is the NANDed value of specified nodes. TYPE_NAND = 4; // The node's value is a constant 1. TYPE_TRUE = 5; // The node's value is a constant 0. TYPE_FALSE = 6; }; Type type = 1; message Port { // Name of port. string portname = 1; // Bit index in port. int64 bitindex = 2; } message Gate { // Node index of left side of operation. int64 left = 1; // Node index of right side of operation. int64 right = 2; } oneof node { // Set for PORT, NPORT Port port = 2; // Set for AND, NAND. Gate gate = 3; } // Set when the node drives given output port(s). message OutPort { // Name of port. string name = 1; // Bit index in port. int64 bit_index = 2; } repeated OutPort out_port = 4; } // List of AIG nodes - each is explicitely numbered by its' index in this // array. repeated Node node = 1; } // A Yosys design netlist dumped from RTLIL. message Design { // Human-readable freeform 'remark' string. string creator = 1; // List of named modules in design. map modules = 2; // List of named AIG models in design (if AIG export enabled). map models = 3; } n81' href='#n81'>81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453